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Notes For V2.10-0
WARNING: V2.10 has reorganized and renamed some of the definition files for the PDP-10, PDP-11, and VAX. Be sure to delete all previous source files before you unpack the Zip archive, or unpack it into a new directory structure. WARNING: V2.10 has a new, more comprehensive save file format. Restoring save files from previous releases will cause 'invalid register' errors and loss of CPU option flags, device enable/ disable flags, unit online/offline flags, and unit writelock flags. WARNING: If you are using Visual Studio .NET through the IDE, be sure to turn off the /Wp64 flag in the project settings, or dozens of spurious errors will be generated. WARNING: Compiling Ethernet support under Windows requires extra steps; see the Ethernet readme file. Ethernet support is currently available only for Windows, Linux, NetBSD, and OpenBSD. 1. New Features 1.1 SCP and Libraries - The VT emulation package has been replaced by the capability to remote the console to a Telnet session. Telnet clients typically have more complete and robust VT100 emulation. - Simulated devices may now have statically allocated buffers, in addition to dynamically allocated buffers or disk-based data stores. - The DO command now takes substitutable arguments (max 9). In command files, %n represents substitutable argument n. - The initial command line is now interpreted as the command name and substitutable arguments for a DO command. This is backward compatible to prior versions. - The initial command line parses switches. -Q is interpreted as quiet mode; informational messages are suppressed. - The HELP command now takes an optional argument. HELP <cmd> types help on the specified command. - Hooks have been added for implementing GUI-based consoles, as well as simulator-specific command extensions. A few internal data structures and definitions have changed. - Two new routines (tmxr_open_master, tmxr_close_master) have been added to sim_tmxr.c. The calling sequence for sim_accept_conn has been changed in sim_sock.c. - The calling sequence for the VM boot routine has been modified to add an additional parameter. - SAVE now saves, and GET now restores, controller and unit flags. - Library sim_ether.c has been added for Ethernet support. 1.2 VAX - Non-volatile RAM (NVR) can behave either like a memory or like a disk-based peripheral. If unattached, it behaves like memory and is saved and restored by SAVE and RESTORE, respectively. If attached, its contents are loaded from disk by ATTACH and written back to disk at DETACH and EXIT. - SHOW <device> VECTOR displays the device's interrupt vector. A few devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The TK50 (TMSCP tape) has been added. - The DEQNA/DELQA (Qbus Ethernet controllers) have been added. - Autoconfiguration support has been added. - The paper tape reader has been removed from vax_stddev.c and now references a common implementation file, dec_pt.h. - Examine and deposit switches now work on all devices, not just the CPU. - Device address conflicts are not detected until simulation starts. 1.3 PDP-11 - SHOW <device> VECTOR displays the device's interrupt vector. Most devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk), RX211 (double density floppy), and KW11P programmable clock have been added. - The DEQNA/DELQA (Qbus Ethernet controllers) have been added. - Autoconfiguration support has been added. - The paper tape reader has been removed from pdp11_stddev.c and now references a common implementation file, dec_pt.h. - Device bootstraps now use the actual CSR specified by the SET ADDRESS command, rather than just the default CSR. Note that PDP-11 operating systems may NOT support booting with non-standard addresses. - Specifying more than 256KB of memory, or changing the bus configuration, causes all peripherals that are not compatible with the current bus configuration to be disabled. - Device address conflicts are not detected until simulation starts. 1.4 PDP-10 - SHOW <device> VECTOR displays the device's interrupt vector. A few devices allow the vector to be changed with SET <device> VECTOR=nnn. - SHOW CPU IOSPACE displays the I/O space address map. - The RX211 (double density floppy) has been added; it is off by default. - The paper tape now references a common implementation file, dec_pt.h. - Device address conflicts are not detected until simulation starts. 1.5 PDP-1 - DECtape (then known as MicroTape) support has been added. - The line printer and DECtape can be disabled and enabled. 1.6 PDP-8 - The RX28 (double density floppy) has been added as an option to the existing RX8E controller. - SHOW <device> DEVNO displays the device's device number. Most devices allow the device number to be changed with SET <device> DEVNO=nnn. - Device number conflicts are not detected until simulation starts. 1.7 IBM 1620 - The IBM 1620 simulator has been released. 1.8 AltairZ80 - A hard drive has been added for increased storage. - Several bugs have been fixed. 1.9 HP 2100 - The 12845A has been added and made the default line printer (LPT). The 12653A has been renamed LPS and is off by default. It also supports the diagnostic functions needed to run the DCPC and DMS diagnostics. - The 12557A/13210A disk defaults to the 13210A (7900/7901). - The 12559A magtape is off by default. - New CPU options (EAU/NOEAU) enable/disable the extended arithmetic instructions for the 2116. These instructions are standard on the 2100 and 21MX. - New CPU options (MPR/NOMPR) enable/disable memory protect for the 2100 and 21MX. - New CPU options (DMS/NODMS) enable/disable the dynamic mapping instructions for the 21MX. - The 12539 timebase generator autocalibrates. 1.10 Simulated Magtapes - Simulated magtapes recognize end of file and the marker 0xFFFFFFFF as end of medium. Only the TMSCP tape simulator can generate an end of medium marker. - The error handling in simulated magtapes was overhauled to be consistent through all simulators. 1.11 Simulated DECtapes - Added support for RT11 image file format (256 x 16b) to DECtapes. 2. Release Notes 2.1 Bugs Fixed - TS11/TSV05 was not simulating the XS0_MOT bit, causing failures under VMS. In addition, two of the CTL options were coded interchanged. - IBM 1401 tape was not setting a word mark under group mark for load mode reads. This caused the diagnostics to crash. - SCP bugs in ssh_break and set_logon were fixed (found by Dave Hittner). - Numerous bugs in the HP 2100 extended arithmetic, floating point, 21MX, DMS, and IOP instructions were fixed. Bugs were also fixed in the memory protect and DMS functions. The moving head disks (DP, DQ) were revised to simulate the hardware more accurately. Missing functions in DQ (address skip, read address) were added. 2.2 HP 2100 Debugging - The HP 2100 CPU nows runs all of the CPU diagnostics. - The peripherals run most of the peripheral diagnostics. There is still a problem in overlapped seek operation on the disks. See the file hp2100_diag.txt for details. 3. In Progress These simulators are not finished and are available in a separate Zip archive distribution. - Interdata 16b/32b: coded, partially tested. See the file id_diag.txt for details. - SDS 940: coded, partially tested.
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
df6475181c
commit
2c2dd5ea33
@@ -25,6 +25,10 @@
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cpu PDP-11 CPU (J-11 microprocessor)
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17-Oct-02 RMS Fixed bug in examine/deposit (found by Hans Pufal)
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08-Oct-02 RMS Revised to build dib_tab dynamically
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Added SHOW IOSPACE
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09-Sep-02 RMS Added KW11P support
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14-Jul-02 RMS Fixed bug in MMR0 error status load
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03-Jun-02 RMS Fixed relocation add overflow, added PS<15:12> = 1111
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special case logic to MFPI and removed it from MTPI
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@@ -184,11 +188,10 @@
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Because the PSW can be explicitly written as address 17777776,
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all instructions must update PSW before executing their last write.
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4. Adding I/O devices. This requires modifications to three modules:
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4. Adding I/O devices. These modules must be modified:
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pdp11_defs.h add interrupt request definitions
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pdp11_io.c add to dib_tab
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pdp11_sys.c add to sim_devices
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pdp11_defs.h add device address and interrupt definitions
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pdp11_sys.c add to sim_devices table entry
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*/
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/* Definitions */
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@@ -277,9 +280,10 @@ int32 dsmask[4] = { MMR3_KDS, MMR3_SDS, 0, MMR3_UDS }; /* dspace enables */
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extern int32 sim_interval;
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extern UNIT *sim_clock_queue;
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extern UNIT clk_unit;
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extern UNIT clk_unit, pclk_unit;
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extern int32 sim_int_char;
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extern int32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
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extern DEVICE *sim_devices[];
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/* Function declarations */
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@@ -287,6 +291,7 @@ t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_reset (DEVICE *dptr);
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t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat cpu_set_bus (UNIT *uptr, int32 val, char *cptr, void *desc);
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int32 GeteaB (int32 spec);
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int32 GeteaW (int32 spec);
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int32 relocR (int32 addr);
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@@ -310,6 +315,8 @@ t_stat MMR3_wr (int32 data, int32 addr, int32 access);
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t_stat ubm_rd (int32 *data, int32 addr, int32 access);
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t_stat ubm_wr (int32 data, int32 addr, int32 access);
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extern t_stat build_dib_tab (int32 ubm);
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extern t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc);
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extern t_stat iopageR (int32 *data, uint32 addr, int32 access);
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extern t_stat iopageW (int32 data, uint32 addr, int32 access);
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extern int32 calc_ints (int32 nipl, int32 trq);
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@@ -336,12 +343,12 @@ int32 trap_clear[TRAP_V_MAX] = { /* trap clears */
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/* Fixed I/O address table entries */
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DIB cpu0_dib = { 1, IOBA_CPU, IOLN_CPU, &CPU_rd, &CPU_wr };
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DIB cpu1_dib = { 1, IOBA_APR, IOLN_APR, &APR_rd, &APR_wr };
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DIB cpu2_dib = { 1, IOBA_APR1, IOLN_APR1, &APR_rd, &APR_wr };
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DIB cpu3_dib = { 1, IOBA_SRMM, IOLN_SRMM, &SR_MMR012_rd, &SR_MMR012_wr };
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DIB cpu4_dib = { 1, IOBA_MMR3, IOLN_MMR3, &MMR3_rd, &MMR3_wr };
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DIB ubm_dib = { 0, IOBA_UBM, IOLN_UBM, &ubm_rd, &ubm_wr };
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DIB cpu0_dib = { IOBA_CPU, IOLN_CPU, &CPU_rd, &CPU_wr, 0 };
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DIB cpu1_dib = { IOBA_APR, IOLN_APR, &APR_rd, &APR_wr, 0 };
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DIB cpu2_dib = { IOBA_APR1, IOLN_APR1, &APR_rd, &APR_wr, 0 };
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DIB cpu3_dib = { IOBA_SRMM, IOLN_SRMM, &SR_MMR012_rd, &SR_MMR012_wr, 0 };
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DIB cpu4_dib = { IOBA_MMR3, IOLN_MMR3, &MMR3_rd, &MMR3_wr, 0 };
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DIB ubm_dib = { IOBA_UBM, IOLN_UBM, &ubm_rd, &ubm_wr, 0 };
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/* CPU data structures
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@@ -395,7 +402,7 @@ REG cpu_reg[] = {
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{ ORDATA (STOP_TRAPS, stop_trap, TRAP_V_MAX) },
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{ FLDATA (STOP_VECA, stop_vecabort, 0) },
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{ FLDATA (STOP_SPA, stop_spabort, 0) },
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{ ORDATA (DBGLOG, cpu_log, 16), REG_HIDDEN },
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{ HRDATA (DBGLOG, cpu_log, 16), REG_HIDDEN },
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{ ORDATA (FAC0H, FR[0].h, 32) },
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{ ORDATA (FAC0L, FR[0].l, 32) },
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{ ORDATA (FAC1H, FR[1].h, 32) },
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@@ -512,10 +519,6 @@ REG cpu_reg[] = {
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{ GRDATA (UDPAR7, APRFILE[077], 8, 16, 16) },
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{ GRDATA (UDPDR7, APRFILE[077], 8, 16, 0) },
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{ BRDATA (UBMAP, ub_map, 8, 22, UBM_LNT_LW) },
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{ FLDATA (18B_ADDR, cpu_unit.flags, UNIT_V_18B), REG_HRO },
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{ FLDATA (UB_MAP, cpu_unit.flags, UNIT_V_UBM), REG_HRO },
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{ FLDATA (RH11, cpu_unit.flags, UNIT_V_RH11), REG_HRO },
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{ FLDATA (CIS, cpu_unit.flags, UNIT_V_CIS), REG_HRO },
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{ BRDATA (PCQ, pcq, 8, 16, PCQ_SIZE), REG_RO+REG_CIRC },
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{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
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{ ORDATA (WRU, sim_int_char, 8) },
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@@ -524,9 +527,9 @@ REG cpu_reg[] = {
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MTAB cpu_mod[] = {
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{ UNIT_MAP, UNIT_18B, "18b addressing", "18B", NULL },
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{ UNIT_MAP, UNIT_UBM, "22b Unibus + RH70", "URH70", NULL },
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{ UNIT_MAP, UNIT_UBM + UNIT_RH11, "22b Unibus + RH11", "URH11", NULL },
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{ UNIT_MAP, 0, "22b addressing", "22B", NULL },
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{ UNIT_MAP, UNIT_UBM, "22b Unibus + RH70", "URH70", &cpu_set_bus },
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{ UNIT_MAP, UNIT_UBM + UNIT_RH11, "22b Unibus + RH11", "URH11", &cpu_set_bus },
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{ UNIT_MAP, 0, "22b addressing", "22B", &cpu_set_bus },
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{ UNIT_CIS, UNIT_CIS, "CIS", "CIS", NULL },
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{ UNIT_CIS, 0, "no CIS", "NOCIS", NULL },
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{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size},
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@@ -548,6 +551,8 @@ MTAB cpu_mod[] = {
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{ UNIT_MSIZE, 2097152, NULL, "2M", &cpu_set_size},
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{ UNIT_MSIZE, 3145728, NULL, "3M", &cpu_set_size},
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{ UNIT_MSIZE, 4186112, NULL, "4M", &cpu_set_size},
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
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NULL, &show_iospace },
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{ 0 } };
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DEVICE cpu_dev = {
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@@ -573,8 +578,12 @@ void cis11 (int32 IR);
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5. Interrupt system
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*/
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if (cpu_unit.flags & UNIT_UBM) ubm_dib.enb = 1; /* enb/dis map */
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else ubm_dib.enb = 0;
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cpu_18b = cpu_unit.flags & UNIT_18B; /* export cnf flgs */
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cpu_ubm = cpu_unit.flags & UNIT_UBM;
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cpu_rh11 = cpu_unit.flags & UNIT_RH11;
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cpu_bme = (MMR3 & MMR3_BME) && cpu_ubm;
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reason = build_dib_tab (cpu_ubm); /* build, chk dib_tab */
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if (reason != SCPE_OK) return reason;
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cm = (PSW >> PSW_V_CM) & 03; /* call calc_is,ds */
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pm = (PSW >> PSW_V_PM) & 03;
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rs = (PSW >> PSW_V_RS) & 01;
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@@ -593,14 +602,11 @@ isenable = calc_is (cm);
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dsenable = calc_ds (cm);
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CPU_wr (PIRQ, 017777772, WRITE); /* rewrite PIRQ */
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cpu_bme = (MMR3 & MMR3_BME) && (cpu_unit.flags & UNIT_UBM);
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cpu_18b = cpu_unit.flags & UNIT_18B; /* export cnf flgs */
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cpu_ubm = cpu_unit.flags & UNIT_UBM;
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cpu_rh11 = cpu_unit.flags & UNIT_RH11;
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trap_req = calc_ints (ipl, trap_req); /* upd int req */
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trapea = 0;
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reason = 0;
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sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init line clock */
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sim_rtcn_init (pclk_unit.wait, TMR_PCLK); /* init prog clock */
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/* Abort handling
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@@ -1689,7 +1695,7 @@ PSW = (cm << PSW_V_CM) | (pm << PSW_V_PM) | (rs << PSW_V_RS) |
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for (i = 0; i < 6; i++) REGFILE[i][rs] = R[i];
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STACKFILE[cm] = SP;
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saved_PC = PC & 0177777;
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pcq_r -> qptr = pcq_p; /* update pc q ptr */
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pcq_r->qptr = pcq_p; /* update pc q ptr */
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return reason;
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}
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@@ -1805,7 +1811,6 @@ case 2: /* (R)+ */
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if (update_MM) MMR1 = calc_MMR1 ((delta << 3) | reg);
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return (adr | ds);
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case 3: /* @(R)+ */
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adr = R[reg];
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R[reg] = ((adr = R[reg]) + 2) & 0177777;
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if (update_MM) MMR1 = calc_MMR1 (020 | reg);
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adr = ReadW (adr | ds);
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@@ -2086,7 +2091,7 @@ return pa;
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sw = switches
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Outputs:
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pa = physical address
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On aborts, this routine returns -1
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On aborts, this routine returns MAXMEMSIZE
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*/
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int32 relocC (int32 va, int32 sw)
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@@ -2104,8 +2109,8 @@ if (MMR0 & MMR0_MME) { /* if mmgt */
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apr = APRFILE[apridx]; /* with va<18:13> */
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dbn = va & VA_BN; /* extr block num */
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plf = (apr & PDR_PLF) >> 2; /* extr page length */
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if ((apr & PDR_PRD) == 0) return -1; /* not readable? */
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if ((apr & PDR_ED)? dbn < plf: dbn > plf) return -1;
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if ((apr & PDR_PRD) == 0) return MAXMEMSIZE; /* not readable? */
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if ((apr & PDR_ED)? dbn < plf: dbn > plf) return MAXMEMSIZE;
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pa = ((va & VA_DF) + ((apr >> 10) & 017777700)) & PAMASK;
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if ((MMR3 & MMR3_M22E) == 0) {
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pa = pa & 0777777;
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@@ -2171,7 +2176,7 @@ if (pa & 1) return SCPE_OK;
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MMR3 = data & MMR3_RW;
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if (cpu_unit.flags & UNIT_18B)
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MMR3 = MMR3 & ~(MMR3_BME + MMR3_M22E); /* for UNIX V6 */
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cpu_bme = (MMR3 & MMR3_BME) && (cpu_unit.flags & UNIT_UBM);
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cpu_bme = (MMR3 & MMR3_BME) && cpu_ubm;
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dsenable = calc_ds (cm);
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return SCPE_OK;
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}
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@@ -2364,7 +2369,7 @@ wait_state = 0;
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if (M == NULL) M = calloc (MEMSIZE >> 1, sizeof (unsigned int16));
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if (M == NULL) return SCPE_MEM;
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pcq_r = find_reg ("PCQ", NULL, dptr);
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if (pcq_r) pcq_r -> qptr = 0;
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if (pcq_r) pcq_r->qptr = 0;
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else return SCPE_IERR;
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for (i = 0; i < UBM_LNT_LW; i++) ub_map[i] = 0;
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sim_brk_types = sim_brk_dflt = SWMASK ('E');
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@@ -2382,7 +2387,7 @@ if (vptr == NULL) return SCPE_ARG;
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if (sw & SWMASK ('V')) { /* -v */
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if (addr >= VASIZE) return SCPE_NXM;
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addr = relocC (addr, sw); /* relocate */
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if (addr < 0) return SCPE_REL; }
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if (addr >= MAXMEMSIZE) return SCPE_REL; }
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if (addr < MEMSIZE) {
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*vptr = M[addr >> 1] & 0177777;
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return SCPE_OK; }
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@@ -2399,7 +2404,7 @@ t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
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if (sw & SWMASK ('V')) { /* -v */
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if (addr >= VASIZE) return SCPE_NXM;
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addr = relocC (addr, sw); /* relocate */
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if (addr < 0) return SCPE_REL; }
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if (addr >= MAXMEMSIZE) return SCPE_REL; }
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if (addr < MEMSIZE) {
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M[addr >> 1] = val & 0177777;
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return SCPE_OK; }
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@@ -2413,7 +2418,7 @@ t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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int32 mc = 0;
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t_addr i, clim;
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unsigned int16 *nM = NULL;
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unsigned int16 *nM;
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if ((val <= 0) || (val > MAXMEMSIZE) || ((val & 07777) != 0))
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return SCPE_ARG;
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@@ -2427,4 +2432,26 @@ for (i = 0; i < clim; i = i + 2) nM[i >> 1] = M[i >> 1];
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free (M);
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M = nM;
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MEMSIZE = val;
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return SCPE_OK; }
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return cpu_set_bus (uptr, (cpu_unit.flags & UNIT_MAP) | 1, cptr, desc); }
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/* Bus configuration, disable Unibus or Qbus devices */
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t_stat cpu_set_bus (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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DEVICE *dptr;
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uint32 i, target;
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if ((MEMSIZE <= UNIMEMSIZE) || (val & UNIT_18B) ||
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(!(val & 1) && ((uint32) val == (cpu_unit.flags & UNIT_MAP)))) return SCPE_OK;
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if (val & UNIT_MAP) target = DEV_QBUS; /* going to Ubus? */
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else target = DEV_UBUS; /* going to Qbus */
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for (i = 0; (dptr = sim_devices[i]) != NULL; i++) {
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if ((dptr->flags & DEV_DISABLE) && /* disable-able? */
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!(dptr->flags & DEV_DIS) && /* enabled? */
|
||||
((dptr->flags & (DEV_QBUS|DEV_UBUS)) == target)) {
|
||||
printf ("Disabling %s\n", dptr->name);
|
||||
if (sim_log) fprintf (sim_log, "Disabling %s\n", dptr->name);
|
||||
dptr->flags = dptr->flags | DEV_DIS; } }
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user