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Notes For V3.9
The makefile now works for Linux and most Unix's. However, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.9-0 1.1.1 SCP and libraries - added *nix READLINE support (Mark Pizzolato) - added "SHOW SHOW" and "SHOW <dev> SHOW" commands (Mark Pizzolato) - added support for BREAK key on Windows (Mark Pizzolato) 1.1.2 PDP-8 - floating point processor is now enabled 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h. 3. Status Report This is the last release of SimH for which I will be sole editor. After this release, the source is moving to a public repository: under the general editorship of Dave Hittner and Mark Pizzolato. The status of the individual simulators is as follows: 3.1 PDP-1 Stable and working; runs available software. 3.2 PDP-4/7/9/15 Stable and working; runs available software. 3.3 PDP-8 Stable and working; runs available software. 3.4 PDP-10 [KS-10 only] Stable and working; runs available software. 3.5 PDP-11 Stable and working; runs available system software. The emulation of individual models has numerous errors of detail, which prevents many diagnostics from running correctly. 3.6 VAX-11/780 Stable and working; runs available software. 3.7 MicroVAX 3900 (VAX) Stable and working; runs available software. Thanks to the kind generosity of Camiel Vanderhoeven, this simulator has been verified with AXE, the VAX architectural exerciser. 3.8 Nova Stable and working; runs available software. 3.9 Eclipse Stable and working, but not really supported. There is no Eclipse-specific software available under a hobbyist license. 3.10 Interdata 16b Stable and working, but no software for it has been found, other than diagnostics. 3.11 Interdata 32b Stable and working; runs 32b UNIX and diagnostics. 3.12 IBM 1401 Stable and working; runs available software. 3.13 IBM 1620 Hand debug only. No software for it has been found or tested. 3.14 IBM 7094 Stable and working as a stock system; runs IBSYS. The CTSS extensions have not been debugged. 3.15 IBM S/3 Stable and working, but not really supported. Runs available software. 3.16 IBM 1130 Stable and working; runs available software. Supported and edited by Brian Knittel. 3.17 HP 2100/1000 Stable and working; runs available software. Supported and edited by Dave Bryan. 3.18 Honeywell 316/516 Stable and working; runs available software. 3.19 GRI-909/99 Hand debug only. No software for it has been found or tested. 3.20 SDS-940 Hand debug only, and a few diagnostics. 3.21 LGP-30 Unfinished; hand debug only. Does not run available software, probably due to my misunderstanding of the LGP-30 operational procedures. 3.22 Altair (original 8080 version) Stable and working, but not really supported. Runs available software. 3.23 AltairZ80 (Z80 version) Stable and working; runs available software. Supported and edited by Peter Schorn. 3.24 SWTP 6800 Stable and working; runs available software. Supported and edited by Bill Beech 3.25 Sigma 32b Incomplete; more work is needed on the peripherals for accuracy. 3.26 Alpha Incomplete; essentially just an EV-5 (21164) chip emulator. 4. Suggestions for Future Work 4.1 General Structure - Multi-threading, to allow true concurrency between SCP and the simulator - Graphics device support, particularly for the PDP-1 and PDP-11 4.2 Current Simulators - PDP-1 graphics, to run Space War - PDP-11 GT40 graphics, to run Lunar Lander - PDP-15 MUMPS-15 - Interdata native OS debug, both 16b and 32b - SDS 940 timesharing operating system debug - IBM 7094 CTSS feature debug and operating system debug - IBM 1620 debug and software - GRI-909 software - Sigma 32b completion and debug - LGP-30 debug 4.3 Possible Future Simulators - Data General MV8000 (if a hobbyist license can be obtained for AOS) - Alpha simulator - HP 3000 (16b) simulator with MPE
This commit is contained in:
Mark Pizzolato
@@ -1,6 +1,6 @@
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/* pdp11_defs.h: PDP-11 simulator definitions
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Copyright (c) 1993-2010, Robert M Supnik
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Copyright (c) 1993-2011, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -26,6 +26,7 @@
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The author gratefully acknowledges the help of Max Burnet, Megan Gentry,
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and John Wilson in resolving questions about the PDP-11
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11-Dec-11 RMS Fixed priority of PIRQ vs IO; added INT_INTERNALn
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22-May-10 RMS Added check for 64b definitions
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19-Nov-08 RMS Moved I/O support routines to I/O library
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16-May-08 RMS Added KE11A, DC11 support
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@@ -628,61 +629,65 @@ typedef struct pdp_dib DIB;
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#define IOBA_PSW (IOPAGEBASE + 017776) /* PSW */
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#define IOLN_PSW 002
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/* Interrupt assignments; within each level, priority is right to left */
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/* Interrupt assignments; within each level, priority is right to left
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PIRQn has the highest priority with a level and is always bit <0>
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On level 6, the clock is second highest priority */
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#define IPL_HLVL 8 /* # int levels */
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#define IPL_HMIN 4 /* lowest IO int level */
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#define INT_V_PIR7 0 /* BR7 */
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#define INT_V_CLK 0 /* BR6 */
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#define INT_V_PCLK 1
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#define INT_V_DTA 2
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#define INT_V_TA 3
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#define INT_V_PIR6 4
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#define INT_V_PIR6 0 /* BR6 */
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#define INT_V_CLK 1
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#define INT_V_PCLK 2
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#define INT_V_DTA 3
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#define INT_V_TA 4
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#define INT_V_RK 0 /* BR5 */
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#define INT_V_RL 1
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#define INT_V_RX 2
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#define INT_V_TM 3
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#define INT_V_RP 4
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#define INT_V_TS 5
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#define INT_V_HK 6
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#define INT_V_RQ 7
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#define INT_V_DZRX 8
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#define INT_V_DZTX 9
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#define INT_V_TQ 10
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#define INT_V_RY 11
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#define INT_V_XQ 12
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#define INT_V_XU 13
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#define INT_V_TU 14
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#define INT_V_RF 15
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#define INT_V_RC 16
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#define INT_V_PIR5 17
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#define INT_V_PIR5 0 /* BR5 */
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#define INT_V_RK 1
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#define INT_V_RL 2
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#define INT_V_RX 3
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#define INT_V_TM 4
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#define INT_V_RP 5
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#define INT_V_TS 6
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#define INT_V_HK 7
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#define INT_V_RQ 8
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#define INT_V_DZRX 9
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#define INT_V_DZTX 10
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#define INT_V_TQ 11
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#define INT_V_RY 12
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#define INT_V_XQ 13
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#define INT_V_XU 14
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#define INT_V_TU 15
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#define INT_V_RF 16
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#define INT_V_RC 17
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#define INT_V_TTI 0 /* BR4 */
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#define INT_V_TTO 1
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#define INT_V_PTR 2
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#define INT_V_PTP 3
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#define INT_V_LPT 4
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#define INT_V_VHRX 5
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#define INT_V_VHTX 6
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#define INT_V_CR 7
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#define INT_V_DLI 8
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#define INT_V_DLO 9
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#define INT_V_DCI 10
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#define INT_V_DCO 11
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#define INT_V_PIR4 12
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#define INT_V_PIR4 0 /* BR4 */
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#define INT_V_TTI 1
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#define INT_V_TTO 2
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#define INT_V_PTR 3
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#define INT_V_PTP 4
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#define INT_V_LPT 5
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#define INT_V_VHRX 6
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#define INT_V_VHTX 7
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#define INT_V_CR 8
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#define INT_V_DLI 9
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#define INT_V_DLO 10
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#define INT_V_DCI 11
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#define INT_V_DCO 12
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#define INT_V_PIR3 0 /* BR3 */
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#define INT_V_PIR2 0 /* BR2 */
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#define INT_V_PIR1 0 /* BR1 */
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#define INT_PIR7 (1u << INT_V_PIR7)
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#define INT_PIR6 (1u << INT_V_PIR6)
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#define INT_CLK (1u << INT_V_CLK)
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#define INT_PCLK (1u << INT_V_PCLK)
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#define INT_DTA (1u << INT_V_DTA)
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#define INT_TA (1u << INT_V_TA)
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#define INT_PIR6 (1u << INT_V_PIR6)
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#define INT_PIR5 (1u << INT_V_PIR5)
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#define INT_RK (1u << INT_V_RK)
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#define INT_RL (1u << INT_V_RL)
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#define INT_RX (1u << INT_V_RX)
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@@ -700,11 +705,11 @@ typedef struct pdp_dib DIB;
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#define INT_TU (1u << INT_V_TU)
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#define INT_RF (1u << INT_V_RF)
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#define INT_RC (1u << INT_V_RC)
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#define INT_PIR5 (1u << INT_V_PIR5)
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#define INT_PTR (1u << INT_V_PTR)
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#define INT_PTP (1u << INT_V_PTP)
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#define INT_PIR4 (1u << INT_V_PIR4)
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#define INT_TTI (1u << INT_V_TTI)
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#define INT_TTO (1u << INT_V_TTO)
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#define INT_PTR (1u << INT_V_PTR)
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#define INT_PTP (1u << INT_V_PTP)
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#define INT_LPT (1u << INT_V_LPT)
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#define INT_VHRX (1u << INT_V_VHRX)
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#define INT_VHTX (1u << INT_V_VHTX)
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@@ -713,11 +718,18 @@ typedef struct pdp_dib DIB;
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#define INT_DLO (1u << INT_V_DLO)
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#define INT_DCI (1u << INT_V_DCI)
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#define INT_DCO (1u << INT_V_DCO)
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#define INT_PIR4 (1u << INT_V_PIR4)
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#define INT_PIR3 (1u << INT_V_PIR3)
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#define INT_PIR2 (1u << INT_V_PIR2)
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#define INT_PIR1 (1u << INT_V_PIR1)
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#define INT_INTERNAL7 (INT_PIR7)
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#define INT_INTERNAL6 (INT_PIR6 | INT_CLK)
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#define INT_INTERNAL5 (INT_PIR5)
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#define INT_INTERNAL4 (INT_PIR4)
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#define INT_INTERNAL3 (INT_PIR3)
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#define INT_INTERNAL2 (INT_PIR2)
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#define INT_INTERNAL1 (INT_PIR1)
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#define IPL_CLK 6 /* int pri levels */
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#define IPL_PCLK 6
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#define IPL_DTA 6
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