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Notes For V3.9
The makefile now works for Linux and most Unix's. However, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.9-0 1.1.1 SCP and libraries - added *nix READLINE support (Mark Pizzolato) - added "SHOW SHOW" and "SHOW <dev> SHOW" commands (Mark Pizzolato) - added support for BREAK key on Windows (Mark Pizzolato) 1.1.2 PDP-8 - floating point processor is now enabled 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h. 3. Status Report This is the last release of SimH for which I will be sole editor. After this release, the source is moving to a public repository: under the general editorship of Dave Hittner and Mark Pizzolato. The status of the individual simulators is as follows: 3.1 PDP-1 Stable and working; runs available software. 3.2 PDP-4/7/9/15 Stable and working; runs available software. 3.3 PDP-8 Stable and working; runs available software. 3.4 PDP-10 [KS-10 only] Stable and working; runs available software. 3.5 PDP-11 Stable and working; runs available system software. The emulation of individual models has numerous errors of detail, which prevents many diagnostics from running correctly. 3.6 VAX-11/780 Stable and working; runs available software. 3.7 MicroVAX 3900 (VAX) Stable and working; runs available software. Thanks to the kind generosity of Camiel Vanderhoeven, this simulator has been verified with AXE, the VAX architectural exerciser. 3.8 Nova Stable and working; runs available software. 3.9 Eclipse Stable and working, but not really supported. There is no Eclipse-specific software available under a hobbyist license. 3.10 Interdata 16b Stable and working, but no software for it has been found, other than diagnostics. 3.11 Interdata 32b Stable and working; runs 32b UNIX and diagnostics. 3.12 IBM 1401 Stable and working; runs available software. 3.13 IBM 1620 Hand debug only. No software for it has been found or tested. 3.14 IBM 7094 Stable and working as a stock system; runs IBSYS. The CTSS extensions have not been debugged. 3.15 IBM S/3 Stable and working, but not really supported. Runs available software. 3.16 IBM 1130 Stable and working; runs available software. Supported and edited by Brian Knittel. 3.17 HP 2100/1000 Stable and working; runs available software. Supported and edited by Dave Bryan. 3.18 Honeywell 316/516 Stable and working; runs available software. 3.19 GRI-909/99 Hand debug only. No software for it has been found or tested. 3.20 SDS-940 Hand debug only, and a few diagnostics. 3.21 LGP-30 Unfinished; hand debug only. Does not run available software, probably due to my misunderstanding of the LGP-30 operational procedures. 3.22 Altair (original 8080 version) Stable and working, but not really supported. Runs available software. 3.23 AltairZ80 (Z80 version) Stable and working; runs available software. Supported and edited by Peter Schorn. 3.24 SWTP 6800 Stable and working; runs available software. Supported and edited by Bill Beech 3.25 Sigma 32b Incomplete; more work is needed on the peripherals for accuracy. 3.26 Alpha Incomplete; essentially just an EV-5 (21164) chip emulator. 4. Suggestions for Future Work 4.1 General Structure - Multi-threading, to allow true concurrency between SCP and the simulator - Graphics device support, particularly for the PDP-1 and PDP-11 4.2 Current Simulators - PDP-1 graphics, to run Space War - PDP-11 GT40 graphics, to run Lunar Lander - PDP-15 MUMPS-15 - Interdata native OS debug, both 16b and 32b - SDS 940 timesharing operating system debug - IBM 7094 CTSS feature debug and operating system debug - IBM 1620 debug and software - GRI-909 software - Sigma 32b completion and debug - LGP-30 debug 4.3 Possible Future Simulators - Data General MV8000 (if a hobbyist license can be obtained for AOS) - Alpha simulator - HP 3000 (16b) simulator with MPE
This commit is contained in:
Mark Pizzolato
566
alpha/alpha_ev5_tlb.c
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566
alpha/alpha_ev5_tlb.c
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@@ -0,0 +1,566 @@
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/* alpha_ev5_tlb.c - Alpha EV5 TLB simulator
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Copyright (c) 2003-2006, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
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||||
The above copyright notice and this permission notice shall be included in
|
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all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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EV5 was the second generation Alpha CPU. It was a four-way, in order issue
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CPU with onchip primary instruction and data caches, an onchip second level
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cache, and support for an offchip third level cache. EV56 was a shrink, with
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added support for byte and word operations. EV56PC was a version of EV56
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without the onchip second level cache.
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This module contains the routines for
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itlb_lookup lookup vpn in instruction TLB
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itlb_load load pte into instruction TLB
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itlb_read read pte from instruction TLB using NLU pointer
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itlb_set_asn set iasn
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itlb_set_cm set icm
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itlb_set_spage set ispage
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dtlb_lookup lookup vpn in data TLB
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dtlb_load load pte into data TLB
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dtlb_read read pte from data TLB using NLU pointer
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dtlb_set_asn set dasn
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dtlb_set_cm set dcm
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dtlb_set_spage set dspage
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tlb_ia TLB invalidate all
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tlb_is TLB invalidate single
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tlb_set_cm TLB set current mode
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*/
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#include "alpha_defs.h"
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#include "alpha_ev5_defs.h"
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#define ITLB_SORT qsort (itlb, ITLB_SIZE, sizeof (TLBENT), &tlb_comp);
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#define DTLB_SORT qsort (dtlb, DTLB_SIZE, sizeof (TLBENT), &tlb_comp);
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#define TLB_ESIZE (sizeof (TLBENT)/sizeof (uint32))
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#define MM_RW(x) (((x) & PTE_FOW)? EXC_W: EXC_R)
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uint32 itlb_cm = 0; /* current modes */
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uint32 itlb_spage = 0; /* superpage enables */
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uint32 itlb_asn = 0;
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uint32 itlb_nlu = 0;
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TLBENT i_mini_tlb;
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TLBENT itlb[ITLB_SIZE];
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uint32 dtlb_cm = 0;
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uint32 dtlb_spage = 0;
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uint32 dtlb_asn = 0;
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uint32 dtlb_nlu = 0;
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TLBENT d_mini_tlb;
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TLBENT dtlb[DTLB_SIZE];
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uint32 cm_eacc = ACC_E (MODE_K); /* precomputed */
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uint32 cm_racc = ACC_R (MODE_K); /* access checks */
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uint32 cm_wacc = ACC_W (MODE_K);
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uint32 cm_macc = ACC_M (MODE_K);
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extern t_uint64 p1;
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extern jmp_buf save_env;
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uint32 mm_exc (uint32 macc);
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void tlb_inval (TLBENT *tlbp);
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t_stat itlb_reset (void);
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t_stat dtlb_reset (void);
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int tlb_comp (const void *e1, const void *e2);
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t_stat tlb_reset (DEVICE *dptr);
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/* TLB data structures
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tlb_dev pager device descriptor
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tlb_unit pager units
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tlb_reg pager register list
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*/
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UNIT tlb_unit = { UDATA (NULL, 0, 0) };
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REG tlb_reg[] = {
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{ HRDATA (ICM, itlb_cm, 2) },
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{ HRDATA (ISPAGE, itlb_spage, 2), REG_HRO },
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{ HRDATA (IASN, itlb_asn, ITB_ASN_WIDTH) },
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{ HRDATA (INLU, itlb_nlu, ITLB_WIDTH) },
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{ BRDATA (IMINI, &i_mini_tlb, 16, 32, TLB_ESIZE) },
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{ BRDATA (ITLB, itlb, 16, 32, ITLB_SIZE*TLB_ESIZE) },
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{ HRDATA (DCM, dtlb_cm, 2) },
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{ HRDATA (DSPAGE, dtlb_spage, 2), REG_HRO },
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{ HRDATA (DASN, dtlb_asn, DTB_ASN_WIDTH) },
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{ HRDATA (DNLU, dtlb_nlu, DTLB_WIDTH) },
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{ BRDATA (DMINI, &d_mini_tlb, 16, 32, TLB_ESIZE) },
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{ BRDATA (DTLB, dtlb, 16, 32, DTLB_SIZE*TLB_ESIZE) },
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{ NULL }
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};
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DEVICE tlb_dev = {
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"TLB", &tlb_unit, tlb_reg, NULL,
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1, 0, 0, 1, 0, 0,
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NULL, NULL, &tlb_reset,
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NULL, NULL, NULL
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};
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/* Translate address, instruction, data, and console
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Inputs:
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va = virtual address
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acc = (VAX only) access mode
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Outputs:
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pa = translation buffer index
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*/
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t_uint64 trans_i (t_uint64 va)
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{
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uint32 va_sext = VA_GETSEXT (va);
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uint32 vpn = VA_GETVPN (va);
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TLBENT *tlbp;
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if ((va_sext != 0) && (va_sext != VA_M_SEXT)) /* invalid virt addr? */
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ABORT1 (va, EXC_BVA + EXC_E);
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if ((itlb_spage & SPEN_43) && VPN_GETSP43 (vpn) == 2) { /* 43b superpage? */
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if (itlb_cm != MODE_K) ABORT1 (va, EXC_ACV + EXC_E);
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return (va & SP43_MASK);
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}
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if ((itlb_spage & SPEN_32) && (VPN_GETSP32 (vpn) == 0x1FFE)) {
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if (itlb_cm != MODE_K) ABORT1 (va, EXC_ACV + EXC_E);
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return (va & SP32_MASK); /* 32b superpage? */
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}
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if (!(tlbp = itlb_lookup (vpn))) /* lookup vpn; miss? */
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ABORT1 (va, EXC_TBM + EXC_E); /* abort reference */
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if (cm_eacc & ~tlbp->pte) /* check access */
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ABORT1 (va, mm_exc (cm_eacc & ~tlbp->pte) | EXC_E);
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return PHYS_ADDR (tlbp->pfn, va); /* return phys addr */
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}
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t_uint64 trans_d (t_uint64 va, uint32 acc)
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{
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uint32 va_sext = VA_GETSEXT (va);
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uint32 vpn = VA_GETVPN (va);
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TLBENT *tlbp;
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if ((va_sext != 0) && (va_sext != VA_M_SEXT)) /* invalid virt addr? */
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ABORT1 (va, EXC_BVA + MM_RW (acc));
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if ((dtlb_spage & SPEN_43) && (VPN_GETSP43 (vpn) == 2)) {
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if (dtlb_cm != MODE_K) ABORT1 (va, EXC_ACV + MM_RW (acc));
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return (va & SP43_MASK); /* 43b superpage? */
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}
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if ((dtlb_spage & SPEN_32) && (VPN_GETSP32 (vpn) == 0x1FFE)) {
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if (dtlb_cm != MODE_K) ABORT1 (va, EXC_ACV + MM_RW (acc));
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return (va & SP32_MASK); /* 32b superpage? */
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}
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if (!(tlbp = dtlb_lookup (vpn))) /* lookup vpn; miss? */
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ABORT1 (va, EXC_TBM + MM_RW (acc)); /* abort reference */
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if (acc & ~tlbp->pte) /* check access */
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ABORT1 (va, mm_exc (acc & ~tlbp->pte) | MM_RW (acc));
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return PHYS_ADDR (tlbp->pfn, va); /* return phys addr */
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}
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/* Generate a memory management error code, based on the access check bits not
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set in PTE
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- If the access check bits, without FOx and V, fail, then ACV
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- If FOx set, then FOx
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- Otherwise, TNV */
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uint32 mm_exc (uint32 not_set)
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{
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uint32 tacc;
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tacc = not_set & ~(PTE_FOR | PTE_FOW | PTE_FOE | PTE_V);
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if (tacc) return EXC_ACV;
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tacc = not_set & (PTE_FOR | PTE_FOW | PTE_FOE);
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if (tacc) return EXC_FOX;
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return EXC_TNV;
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}
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/* TLB invalidate single */
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void tlb_is (t_uint64 va, uint32 flags)
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{
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uint32 va_sext = VA_GETSEXT (va);
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uint32 vpn = VA_GETVPN (va);
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TLBENT *itlbp, *dtlbp;
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if ((va_sext != 0) && (va_sext != VA_M_SEXT)) return;
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if ((flags & TLB_CI) && (itlbp = itlb_lookup (vpn))) {
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tlb_inval (itlbp);
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tlb_inval (&i_mini_tlb);
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ITLB_SORT;
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}
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if ((flags & TLB_CD) && (dtlbp = dtlb_lookup (vpn))) {
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tlb_inval (dtlbp);
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tlb_inval (&d_mini_tlb);
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DTLB_SORT;
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}
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return;
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}
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/* TLB invalidate all */
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void tlb_ia (uint32 flags)
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{
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uint32 i;
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if (flags & TLB_CA) {
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if (flags & TLB_CI) itlb_reset ();
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if (flags & TLB_CD) dtlb_reset ();
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return;
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}
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if (flags & TLB_CI) {
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for (i = 0; i < ITLB_SIZE; i++) {
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if (!(itlb[i].pte & PTE_ASM)) tlb_inval (&itlb[i]);
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}
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tlb_inval (&i_mini_tlb);
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ITLB_SORT;
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}
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if (flags & TLB_CD) {
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for (i = 0; i < DTLB_SIZE; i++) {
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if (!(dtlb[i].pte & PTE_ASM)) tlb_inval (&dtlb[i]);
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}
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tlb_inval (&d_mini_tlb);
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DTLB_SORT;
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}
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return;
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}
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/* TLB lookup */
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TLBENT *itlb_lookup (uint32 vpn)
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{
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int32 p, hi, lo;
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if (vpn == i_mini_tlb.tag) return &i_mini_tlb;
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lo = 0; /* initial bounds */
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hi = ITLB_SIZE - 1;
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do {
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p = (lo + hi) >> 1; /* probe */
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if ((itlb_asn == itlb[p].asn) &&
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(((vpn ^ itlb[p].tag) &
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~((uint32) itlb[p].gh_mask)) == 0)) { /* match to TLB? */
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i_mini_tlb.tag = vpn;
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i_mini_tlb.pte = itlb[p].pte;
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i_mini_tlb.pfn = itlb[p].pfn;
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itlb_nlu = itlb[p].idx + 1;
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if (itlb_nlu >= ITLB_SIZE) itlb_nlu = 0;
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return &i_mini_tlb;
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}
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if ((itlb_asn < itlb[p].asn) ||
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((itlb_asn == itlb[p].asn) && (vpn < itlb[p].tag)))
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hi = p - 1; /* go down? p is upper */
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else lo = p + 1; /* go up? p is lower */
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}
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while (lo <= hi);
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return NULL;
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}
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TLBENT *dtlb_lookup (uint32 vpn)
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{
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int32 p, hi, lo;
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if (vpn == d_mini_tlb.tag) return &d_mini_tlb;
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lo = 0; /* initial bounds */
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hi = DTLB_SIZE - 1;
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do {
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p = (lo + hi) >> 1; /* probe */
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if ((dtlb_asn == dtlb[p].asn) &&
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(((vpn ^ dtlb[p].tag) &
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~((uint32) dtlb[p].gh_mask)) == 0)) { /* match to TLB? */
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d_mini_tlb.tag = vpn;
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d_mini_tlb.pte = dtlb[p].pte;
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d_mini_tlb.pfn = dtlb[p].pfn;
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dtlb_nlu = dtlb[p].idx + 1;
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if (dtlb_nlu >= DTLB_SIZE) dtlb_nlu = 0;
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return &d_mini_tlb;
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}
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if ((dtlb_asn < dtlb[p].asn) ||
|
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((dtlb_asn == dtlb[p].asn) && (vpn < dtlb[p].tag)))
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hi = p - 1; /* go down? p is upper */
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else lo = p + 1; /* go up? p is lower */
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}
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while (lo <= hi);
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return NULL;
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}
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/* Load TLB entry at NLU pointer, advance NLU pointer */
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TLBENT *itlb_load (uint32 vpn, t_uint64 l3pte)
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{
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uint32 i, gh;
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|
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for (i = 0; i < ITLB_SIZE; i++) {
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if (itlb[i].idx == itlb_nlu) {
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TLBENT *tlbp = itlb + i;
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itlb_nlu = itlb_nlu + 1;
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if (itlb_nlu >= ITLB_SIZE) itlb_nlu = 0;
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tlbp->tag = vpn;
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tlbp->pte = (uint32) (l3pte & PTE_MASK) ^ (PTE_FOR|PTE_FOR|PTE_FOE);
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tlbp->pfn = ((uint32) (l3pte >> PTE_V_PFN)) & PFN_MASK;
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tlbp->asn = itlb_asn;
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gh = PTE_GETGH (tlbp->pte);
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tlbp->gh_mask = (1u << (3 * gh)) - 1;
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tlb_inval (&i_mini_tlb);
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ITLB_SORT;
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return tlbp;
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}
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}
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fprintf (stderr, "%%ITLB entry not found, itlb_nlu = %d\n", itlb_nlu);
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ABORT (-SCPE_IERR);
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return NULL;
|
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}
|
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|
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TLBENT *dtlb_load (uint32 vpn, t_uint64 l3pte)
|
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{
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uint32 i, gh;
|
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for (i = 0; i < DTLB_SIZE; i++) {
|
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if (dtlb[i].idx == dtlb_nlu) {
|
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TLBENT *tlbp = dtlb + i;
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dtlb_nlu = dtlb_nlu + 1;
|
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if (dtlb_nlu >= ITLB_SIZE) dtlb_nlu = 0;
|
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tlbp->tag = vpn;
|
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tlbp->pte = (uint32) (l3pte & PTE_MASK) ^ (PTE_FOR|PTE_FOR|PTE_FOE);
|
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tlbp->pfn = ((uint32) (l3pte >> PTE_V_PFN)) & PFN_MASK;
|
||||
tlbp->asn = dtlb_asn;
|
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gh = PTE_GETGH (tlbp->pte);
|
||||
tlbp->gh_mask = (1u << (3 * gh)) - 1;
|
||||
tlb_inval (&d_mini_tlb);
|
||||
DTLB_SORT;
|
||||
return tlbp;
|
||||
}
|
||||
}
|
||||
fprintf (stderr, "%%DTLB entry not found, dtlb_nlu = %d\n", dtlb_nlu);
|
||||
ABORT (-SCPE_IERR);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Read TLB entry at NLU pointer, advance NLU pointer */
|
||||
|
||||
t_uint64 itlb_read (void)
|
||||
{
|
||||
uint8 i;
|
||||
|
||||
for (i = 0; i < ITLB_SIZE; i++) {
|
||||
if (itlb[i].idx == itlb_nlu) {
|
||||
TLBENT *tlbp = itlb + i;
|
||||
itlb_nlu = itlb_nlu + 1;
|
||||
if (itlb_nlu >= ITLB_SIZE) itlb_nlu = 0;
|
||||
return (((t_uint64) tlbp->pfn) << PTE_V_PFN) |
|
||||
((tlbp->pte ^ (PTE_FOR|PTE_FOR|PTE_FOE)) & PTE_MASK);
|
||||
}
|
||||
}
|
||||
fprintf (stderr, "%%ITLB entry not found, itlb_nlu = %d\n", itlb_nlu);
|
||||
ABORT (-SCPE_IERR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
t_uint64 dtlb_read (void)
|
||||
{
|
||||
uint8 i;
|
||||
|
||||
for (i = 0; i < DTLB_SIZE; i++) {
|
||||
if (dtlb[i].idx == dtlb_nlu) {
|
||||
TLBENT *tlbp = dtlb + i;
|
||||
dtlb_nlu = dtlb_nlu + 1;
|
||||
if (dtlb_nlu >= DTLB_SIZE) dtlb_nlu = 0;
|
||||
return (((t_uint64) tlbp->pfn) << PTE_V_PFN) |
|
||||
((tlbp->pte ^ (PTE_FOR|PTE_FOR|PTE_FOE)) & PTE_MASK);
|
||||
}
|
||||
}
|
||||
fprintf (stderr, "%%DTLB entry not found, dtlb_nlu = %d\n", dtlb_nlu);
|
||||
ABORT (-SCPE_IERR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Set ASN - rewrite TLB globals with correct ASN */
|
||||
|
||||
void itlb_set_asn (uint32 asn)
|
||||
{
|
||||
int32 i;
|
||||
|
||||
itlb_asn = asn;
|
||||
for (i = 0; i < ITLB_SIZE; i++) {
|
||||
if (itlb[i].pte & PTE_ASM) itlb[i].asn = asn;
|
||||
}
|
||||
tlb_inval (&i_mini_tlb);
|
||||
ITLB_SORT;
|
||||
return;
|
||||
}
|
||||
|
||||
void dtlb_set_asn (uint32 asn)
|
||||
{
|
||||
int32 i;
|
||||
|
||||
dtlb_asn = asn;
|
||||
for (i = 0; i < DTLB_SIZE; i++) {
|
||||
if (dtlb[i].pte & PTE_ASM) dtlb[i].asn = asn;
|
||||
}
|
||||
tlb_inval (&d_mini_tlb);
|
||||
DTLB_SORT;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set superpage */
|
||||
|
||||
void itlb_set_spage (uint32 spage)
|
||||
{
|
||||
itlb_spage = spage;
|
||||
return;
|
||||
}
|
||||
|
||||
void dtlb_set_spage (uint32 spage)
|
||||
{
|
||||
dtlb_spage = spage;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set current mode */
|
||||
|
||||
void itlb_set_cm (uint32 mode)
|
||||
{
|
||||
itlb_cm = mode;
|
||||
cm_eacc = ACC_E (mode);
|
||||
return;
|
||||
}
|
||||
|
||||
void dtlb_set_cm (uint32 mode)
|
||||
{
|
||||
dtlb_cm = mode;
|
||||
cm_racc = ACC_R (mode);
|
||||
cm_wacc = ACC_W (mode);
|
||||
return;
|
||||
}
|
||||
|
||||
uint32 tlb_set_cm (int32 cm)
|
||||
{
|
||||
if (cm >= 0) {
|
||||
itlb_set_cm (cm);
|
||||
dtlb_set_cm (cm);
|
||||
return cm;
|
||||
}
|
||||
itlb_set_cm (itlb_cm);
|
||||
dtlb_set_cm (dtlb_cm);
|
||||
return dtlb_cm;
|
||||
}
|
||||
|
||||
/* Invalidate TLB entry */
|
||||
|
||||
void tlb_inval (TLBENT *tlbp)
|
||||
{
|
||||
tlbp->tag = INV_TAG;
|
||||
tlbp->pte = 0;
|
||||
tlbp->pfn = 0;
|
||||
tlbp->asn = tlbp->idx;
|
||||
tlbp->gh_mask = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Compare routine for qsort */
|
||||
|
||||
int tlb_comp (const void *e1, const void *e2)
|
||||
{
|
||||
TLBENT *t1 = (TLBENT *) e1;
|
||||
TLBENT *t2 = (TLBENT *) e2;
|
||||
|
||||
if (t1->asn > t2->asn) return +1;
|
||||
if (t1->asn < t2->asn) return -1;
|
||||
if (t1->tag > t2->tag) return +1;
|
||||
if (t1->tag < t2->tag) return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ITLB reset */
|
||||
|
||||
t_stat itlb_reset (void)
|
||||
{
|
||||
int32 i;
|
||||
|
||||
itlb_nlu = 0;
|
||||
for (i = 0; i < ITLB_SIZE; i++) {
|
||||
itlb[i].tag = INV_TAG;
|
||||
itlb[i].pte = 0;
|
||||
itlb[i].pfn = 0;
|
||||
itlb[i].asn = i;
|
||||
itlb[i].gh_mask = 0;
|
||||
itlb[i].idx = i;
|
||||
}
|
||||
tlb_inval (&i_mini_tlb);
|
||||
return SCPE_OK;
|
||||
}
|
||||
/* DTLB reset */
|
||||
|
||||
t_stat dtlb_reset (void)
|
||||
{
|
||||
int32 i;
|
||||
|
||||
dtlb_nlu = 0;
|
||||
for (i = 0; i < DTLB_SIZE; i++) {
|
||||
dtlb[i].tag = INV_TAG;
|
||||
dtlb[i].pte = 0;
|
||||
dtlb[i].pfn = 0;
|
||||
dtlb[i].asn = i;
|
||||
dtlb[i].gh_mask = 0;
|
||||
dtlb[i].idx = i;
|
||||
}
|
||||
tlb_inval (&d_mini_tlb);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* SimH reset */
|
||||
|
||||
t_stat tlb_reset (DEVICE *dptr)
|
||||
{
|
||||
itlb_reset ();
|
||||
dtlb_reset ();
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Show TLB entry or entries */
|
||||
|
||||
t_stat cpu_show_tlb (FILE *of, UNIT *uptr, int32 val, void *desc)
|
||||
{
|
||||
t_addr lo, hi;
|
||||
uint32 lnt;
|
||||
TLBENT *tlbp;
|
||||
DEVICE *dptr;
|
||||
char *cptr = (char *) desc;
|
||||
|
||||
lnt = (val)? DTLB_SIZE: ITLB_SIZE;
|
||||
dptr = find_dev_from_unit (uptr);
|
||||
if (dptr == NULL) return SCPE_IERR;
|
||||
if (cptr) {
|
||||
cptr = get_range (dptr, cptr, &lo, &hi, 10, lnt, 0);
|
||||
if ((cptr == NULL) || (*cptr != 0)) return SCPE_ARG;
|
||||
}
|
||||
else {
|
||||
lo = 0;
|
||||
hi = lnt - 1;
|
||||
}
|
||||
tlbp = (val)? dtlb + lo: itlb + lo;
|
||||
|
||||
do {
|
||||
fprintf (of, "TLB %02d\tTAG=%02X/%08X, ", (uint32) lo, tlbp->asn, tlbp->tag);
|
||||
fprintf (of, "MASK=%X, INDX=%d, ", tlbp->gh_mask, tlbp->idx);
|
||||
fprintf (of, "PTE=%04X, PFN=%08X\n", tlbp->pte, tlbp->pfn);
|
||||
tlbp++;
|
||||
lo++;
|
||||
} while (lo <= hi);
|
||||
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user