From 3f8533d957f444e9ad3b70c17d119ac89f459e41 Mon Sep 17 00:00:00 2001 From: Bob Supnik Date: Thu, 7 Sep 2017 09:52:00 -0700 Subject: [PATCH] H316, I7094, NOVA, PDP1, PDP10, PDP8, SDS: Coverity singleton errors Most history routines defined a local sim_eval of the proper length, but the erroneous ones were fixed length machines that defined an integer variable instead of an integer array of length 1. The VAX used the global sim_eval. The changes follow the VAX practice. --- H316/h316_cpu.c | 9 +++++---- I7094/i7094_cpu.c | 11 ++++++----- NOVA/nova_cpu.c | 9 +++++---- PDP1/pdp1_cpu.c | 9 +++++---- PDP10/pdp10_cpu.c | 7 ++++--- PDP8/pdp8_cpu.c | 7 ++++--- SDS/sds_cpu.c | 7 ++++--- 7 files changed, 33 insertions(+), 26 deletions(-) diff --git a/H316/h316_cpu.c b/H316/h316_cpu.c index 4dd6cc4a..c3d440fc 100644 --- a/H316/h316_cpu.c +++ b/H316/h316_cpu.c @@ -1,6 +1,6 @@ /* h316_cpu.c: Honeywell 316/516 CPU simulator - Copyright (c) 1999-2015, Robert M. Supnik + Copyright (c) 1999-2017, Robert M. Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ cpu H316/H516 CPU + 07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY) 21-May-13 RLA Add IMP/TIP support Move SMK/OTK instructions here (from CLK) Make SET CPU DMA work as documented @@ -1757,7 +1758,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc) { int32 cr, k, di, op, lnt; char *cptr = (char *) desc; -t_value sim_eval; +extern t_value *sim_eval; t_stat r; InstHistory *h; static uint8 has_opnd[16] = { @@ -1786,8 +1787,8 @@ for (k = 0; k < lnt; k++) { /* print specified */ if (h->pc & HIST_EA) fprintf (st, "%05o ", h->ea); else fprintf (st, " "); - sim_eval = h->ir; - if ((fprint_sym (st, h->pc & X_AMASK, &sim_eval, + sim_eval[0] = h->ir; + if ((fprint_sym (st, h->pc & X_AMASK, sim_eval, &cpu_unit, SWMASK ('M'))) > 0) fprintf (st, "(undefined) %06o", h->ir); op = I_GETOP (h->ir) & 017; /* base op */ diff --git a/I7094/i7094_cpu.c b/I7094/i7094_cpu.c index 64c406db..f466f78b 100644 --- a/I7094/i7094_cpu.c +++ b/I7094/i7094_cpu.c @@ -1,6 +1,6 @@ /* i7094_cpu.c: IBM 7094 CPU simulator - Copyright (c) 2003-2011, Robert M. Supnik + Copyright (c) 2003-2017, Robert M. Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ cpu 7094 central processor + 07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY) 31-Dec-11 RMS Select traps have priority over protect traps Added SRI, SPI Fixed user mode and relocation from CTSS RPQ documentation @@ -2400,9 +2401,9 @@ t_stat cpu_fprint_one_inst (FILE *st, uint32 pc, uint32 rpt, uint32 ea, t_uint64 ir, t_uint64 ac, t_uint64 mq, t_uint64 si, t_uint64 opnd) { int32 ch; -t_value sim_eval; +extern t_value *sim_eval; -sim_eval = ir; +sim_eval[0] = ir; if (pc & HIST_PC) { /* instruction? */ fputs ("CPU ", st); fprintf (st, "%05o ", (int)(pc & AMASK)); @@ -2420,7 +2421,7 @@ if (pc & HIST_PC) { /* instruction? */ if (ir & INST_T_DEC) fprintf (st, " "); else fprintf (st, "%05o ", ea); - if (fprint_sym (st, pc & AMASK, &sim_eval, &cpu_unit, SWMASK ('M')) > 0) { + if (fprint_sym (st, pc & AMASK, sim_eval, &cpu_unit, SWMASK ('M')) > 0) { fputs ("(undefined) ", st); fprint_val (st, ir, 8, 36, PV_RZRO); } @@ -2436,7 +2437,7 @@ else if ((ch = HIST_CH (pc))) { /* channel? */ fprintf (st, "%05o ", (int)(pc & AMASK)); fputs (" ", st); fprintf (st, "%05o ", (int)(ea & AMASK)); - if (fprint_sym (st, pc & AMASK, &sim_eval, &cpu_unit, + if (fprint_sym (st, pc & AMASK, sim_eval, &cpu_unit, (ch_dev[ch - 1].flags & DEV_7909)? SWMASK ('N'): SWMASK ('I')) > 0) { fputs ("(undefined) ", st); fprint_val (st, ir, 8, 36, PV_RZRO); diff --git a/NOVA/nova_cpu.c b/NOVA/nova_cpu.c index 16b83b15..05c63ab9 100644 --- a/NOVA/nova_cpu.c +++ b/NOVA/nova_cpu.c @@ -1,6 +1,6 @@ /* nova_cpu.c: NOVA CPU simulator - Copyright (c) 1993-2013, Robert M. Supnik + Copyright (c) 1993-2017, Robert M. Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ cpu Nova central processor + 07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY) 17-Mar-13 RMS Added clarifying brances to IND_STEP macro (Dave Bryan) 04-Jul-07 BKR DEV_SET/CLR macros now used, support for non-existant devices added @@ -1372,7 +1373,7 @@ return ( SCPE_OK ) ; int hist_fprintf( FILE * fp, int itemNum, Hist_entry * hptr ) { -t_value sim_eval ; +extern t_value *sim_eval ; if ( hptr ) { @@ -1394,8 +1395,8 @@ if ( hptr ) fprintf( fp, "%06o %06o ", SP, FP ) ; } - sim_eval = (hptr->ir & 0xFFFF) ; - if ( (fprint_sym(fp, (hptr->pc & AMASK), &sim_eval, &cpu_unit, SWMASK ('M'))) > 0 ) + sim_eval[0] = (hptr->ir & 0xFFFF) ; + if ( (fprint_sym(fp, (hptr->pc & AMASK), sim_eval, &cpu_unit, SWMASK ('M'))) > 0 ) { fprintf( fp, "(undefined) %04o", (hptr->ir & 0xFFFF) ) ; } diff --git a/PDP1/pdp1_cpu.c b/PDP1/pdp1_cpu.c index 7e52241c..03ffc81e 100644 --- a/PDP1/pdp1_cpu.c +++ b/PDP1/pdp1_cpu.c @@ -1,6 +1,6 @@ /* pdp1_cpu.c: PDP-1 CPU simulator - Copyright (c) 1993-2015, Robert M. Supnik + Copyright (c) 1993-2017, Robert M. Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ cpu PDP-1 central processor + 07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY) 27-Mar-15 RMS Backported changes from GitHub master 21-Mar-12 RMS Fixed & vs && in Ea_ch (Michael Bloom) 30-May-07 RMS Fixed typo in SBS clear (Norm Lastovica) @@ -1665,7 +1666,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc) int32 ov, pf, op, k, di, lnt; char *cptr = (char *) desc; t_stat r; -t_value sim_eval; +extern t_value *sim_eval; InstHistory *h; if (hst_lnt == 0) /* enabled? */ @@ -1691,8 +1692,8 @@ for (k = 0; k < lnt; k++) { /* print specified */ if ((op < 032) && (op != 007)) /* mem ref instr */ fprintf (st, "%06o ", h->ea); else fprintf (st, " "); - sim_eval = h->ir; - if ((fprint_sym (st, h->pc & AMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0) + sim_eval[0] = h->ir; + if ((fprint_sym (st, h->pc & AMASK, sim_eval, &cpu_unit, SWMASK ('M'))) > 0) fprintf (st, "(undefined) %06o", h->ir); else if (op < 030) /* mem ref instr */ fprintf (st, " [%06o]", h->opnd); diff --git a/PDP10/pdp10_cpu.c b/PDP10/pdp10_cpu.c index 37f0c1d0..98d63c91 100644 --- a/PDP10/pdp10_cpu.c +++ b/PDP10/pdp10_cpu.c @@ -25,6 +25,7 @@ cpu KS10 central processor + 07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY) 14-Jan-17 RMS Fixed bugs in 1-proceed 09-Feb-16 RMS Fixed nested indirects and executes (Tim Litt) 25-Mar-12 RMS Added missing parameters to prototypes (Mark Pizzolato) @@ -2478,7 +2479,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc) int32 k, di, lnt; char *cptr = (char *) desc; t_stat r; -t_value sim_eval; +extern t_value *sim_eval; InstHistory *h; if (hst_lnt == 0) /* enabled? */ @@ -2500,8 +2501,8 @@ for (k = 0; k < lnt; k++) { /* print specified */ fprint_val (st, h->ac, 8, 36, PV_RZRO); fputs (" ", st); fprintf (st, "%06o ", h->ea); - sim_eval = h->ir; - if ((fprint_sym (st, h->pc & AMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0) { + sim_eval[0] = h->ir; + if ((fprint_sym (st, h->pc & AMASK, sim_eval, &cpu_unit, SWMASK ('M'))) > 0) { fputs ("(undefined) ", st); fprint_val (st, h->ir, 8, 36, PV_RZRO); } diff --git a/PDP8/pdp8_cpu.c b/PDP8/pdp8_cpu.c index 8c6808a6..ee681dc4 100644 --- a/PDP8/pdp8_cpu.c +++ b/PDP8/pdp8_cpu.c @@ -25,6 +25,7 @@ cpu central processor + 07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY) 09-Mar-17 RMS Fixed PCQ_ENTRY for interrupts (COVERITY) 13-Feb-17 RMS RESET clear L'AC, per schematics 28-Jan-17 RMS Renamed switch register variable to SR, per request @@ -1576,7 +1577,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc) int32 l, k, di, lnt; char *cptr = (char *) desc; t_stat r; -t_value sim_eval; +extern t_value *sim_eval; InstHistory *h; if (hst_lnt == 0) /* enabled? */ @@ -1599,8 +1600,8 @@ for (k = 0; k < lnt; k++) { /* print specified */ if (h->ir < 06000) fprintf (st, "%05o ", h->ea); else fprintf (st, " "); - sim_eval = h->ir; - if ((fprint_sym (st, h->pc & ADDRMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0) + sim_eval[0] = h->ir; + if ((fprint_sym (st, h->pc & ADDRMASK, sim_eval, &cpu_unit, SWMASK ('M'))) > 0) fprintf (st, "(undefined) %04o", h->ir); if (h->ir < 04000) fprintf (st, " [%04o]", h->opnd); diff --git a/SDS/sds_cpu.c b/SDS/sds_cpu.c index f8c8f6ed..8acda63e 100644 --- a/SDS/sds_cpu.c +++ b/SDS/sds_cpu.c @@ -26,6 +26,7 @@ cpu central processor rtc real time clock + 07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY) 09-Mar-17 RMS trap_P not set if mem mgt trap during fetch (COVERITY) 28-Apr-07 RMS Removed clock initialization 29-Dec-06 RMS Fixed breakpoint variable declarations @@ -1746,7 +1747,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc) int32 ov, k, di, lnt; char *cptr = (char *) desc; t_stat r; -t_value sim_eval; +extern t_value *sim_eval; InstHistory *h; static char *cyc[] = { " ", " ", "INT", "TRP" }; static char *modes = "NMU?"; @@ -1772,8 +1773,8 @@ for (k = 0; k < lnt; k++) { /* print specified */ if (h->ea & HIST_NOEA) fprintf (st, " "); else fprintf (st, "%05o ", h->ea); - sim_eval = h->ir; - if ((fprint_sym (st, h->pc, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0) + sim_eval[0] = h->ir; + if ((fprint_sym (st, h->pc, sim_eval, &cpu_unit, SWMASK ('M'))) > 0) fprintf (st, "(undefined) %08o", h->ir); fputc ('\n', st); /* end line */ } /* end else instruction */