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Notes For V2.10-4

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1. New Features in 2.10-4

1.1 SCP and Libraries

- Added .ini startup file capability (suggested by Hans Pufal).
- Added multiple switch evaluation points (suggested by Hans Pufal).
- Added multiple command per action.
- Added new library, sim_tape.c, for magtape emulation.

1.2 PDP-11

- Added user-defined disk capacity to RQ.
- Addec choice of controllers to TQ.
- Added user-defined tape capacity to TQ.

1.3 Interdata

- Added SHOW SELCH n command to display selector channel state.

1.4 Line Frequency Clocks (H316, Interdata, Nova, PDP-8, PDP-11,
    PDP-18B, SDS)

- Added SET <device> {50HZ/60HZ}, to set the line frequency.

1.5 DEC Console Input (PDP-8, PDP-11, PDP-18B, VAX)

- Added SET TTI CTRL-C, to generate ^C from SIMH prompt (^C
  crashes simulators compiled with Windows Visual C++).

1.6 Magtapes

- Revised to use magtape library for consistency.

2. Bugs Fixed in 2.10-4

- SCP: fixed bug in multiword deposits to files
- Interdata disks: fixed bug in cylinder overflow on writes
- Interdata tape: fixed bug, read error did not stop selector
  channel
- Interdata precision clock: improved autocalibrate algorithm
  for UNIX V7.
- Nova fixed head disk: fixed autosize algorithm.
- PDP-11 RQ and TQ: fixed bugs in queue process and in vector
  calculation for VAXen.
- PDP-11 TQ: fixed overly strict implementation of illegal
  modifiers check.
- PDP-11 RY: fixed autosize algorithm.
- PDP-18B CPU: fixed three EAE bugs (found by Hans Pufal).
- PDP-18B MT: fixed bugs in interrupt handling, BOT error handling.
- PDP-18B RF: removed extra bit from disk address, fixed autosize
  algorithm.
- PDP-18B SYS: fixed bug in FMTASC usage (found by Hans Pufal).
- PDP-8 MT: fixed bug in BOT error handling.
- PDP-8 DF, RF, RX: fixed autosize algorithm.

3. New Features in 2.10 vs prior releases

3.1 SCP and Libraries

- The VT emulation package has been replaced by the capability
  to remote the console to a Telnet session.  Telnet clients
  typically have more complete and robust VT100 emulation.
- Simulated devices may now have statically allocated buffers,
  in addition to dynamically allocated buffers or disk-based
  data stores.
- The DO command now takes substitutable arguments (max 9).
  In command files, %n represents substitutable argument n.
- The initial command line is now interpreted as the command
  name and substitutable arguments for a DO command.  This is
  backward compatible to prior versions.
- The initial command line parses switches.  -Q is interpreted
  as quiet mode; informational messages are suppressed.
- The HELP command now takes an optional argument.  HELP <cmd>
  types help on the specified command.
- Hooks have been added for implementing GUI-based consoles,
  as well as simulator-specific command extensions.  A few
  internal data structures and definitions have changed.
- Two new routines (tmxr_open_master, tmxr_close_master) have
  been added to sim_tmxr.c.  The calling sequence for
  sim_accept_conn has been changed in sim_sock.c.
- The calling sequence for the VM boot routine has been modified
  to add an additional parameter.
- SAVE now saves, and GET now restores, controller and unit flags.
- Library sim_ether.c has been added for Ethernet support.
- The EVAL command will evaluate a symbolic type-in and display
  it in numeric form.
- The ! command (with no arguments) will launch the host operating
  system command shell.  The ! command (with an argument) executes
  the argument as a host operating system command.  (Code from
  Mark Pizzolato)
- Telnet sessions now recognize BREAK.  How a BREAK is transmitted
  dependent on the particular Telnet client.  (Code from Mark
  Pizzolato)
- The sockets library includes code for active connections as
  well as listening connections.
- The RESTORE command will restore saved memory size, if the
  simulator supports dynamic memory resizing.
- Added dynamic extension of the breakpoint table.
- Added breakpoint actions.
- Added VMS support for ! (from Mark Pizzolato).

3.2 VAX

- Non-volatile RAM (NVR) can behave either like a memory or like
  a disk-based peripheral.  If unattached, it behaves like memory
  and is saved and restored by SAVE and RESTORE, respectively.
  If attached, its contents are loaded from disk by ATTACH and
  written back to disk at DETACH and EXIT.
- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape) has been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from vax_stddev.c and
  now references a common implementation file, dec_pt.h.
- Examine and deposit switches now work on all devices, not just
  the CPU.
- Device address conflicts are not detected until simulation starts.
- If the VAX console is attached to a Telnet session, BREAK is
  interpreted as console halt.
- The SET/SHOW HISTORY commands enable and display a history of
  the most recently executed instructions.  (Code from Mark
  Pizzolato)

3.3 PDP-11

- SHOW <device> VECTOR displays the device's interrupt vector.
  Most devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk),
  RX211 (double density floppy), and KW11P programmable clock
  have been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from pdp11_stddev.c and
  now references a common implementation file, dec_pt.h.
- Device bootstraps now use the actual CSR specified by the
  SET ADDRESS command, rather than just the default CSR.  Note
  that PDP-11 operating systems may NOT support booting with
  non-standard addresses.
- Specifying more than 256KB of memory, or changing the bus
  configuration, causes all peripherals that are not compatible
  with the current bus configuration to be disabled.
- Device address conflicts are not detected until simulation starts.
- The PDP-11 implements a stub DEUNA/DELUA (XU).  The real XU
  module will be included in a later release.

3.4 PDP-10

- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The RX211 (double density floppy) has been added; it is off
  by default.
- The paper tape now references a common implementation file,
  dec_pt.h.
- Device address conflicts are not detected until simulation starts.
- The PDP-10 implements a stub DEUNA/DELUA (XU).  The real XU
  module will be included in a later release.

3.5 PDP-1

- DECtape (then known as MicroTape) support has been added.
- The line printer and DECtape can be disabled and enabled.
- The PDP-1 supports the Type 24 serial drum (based on recently
  discovered documents).

3.6 18b PDP's

- The PDP-4 supports the Type 24 serial drum (based on recently
  discovered documents).
- Added RB09 fixed head disk for the PDP-9.
- Added LP09 line printer for the PDP-9 and PDP-15.
- Added variable size support and autosizing to the RF15/RF09.

3.7 PDP-8

- The RX28 (double density floppy) has been added as an option to
  the existing RX8E controller.
- SHOW <device> DEVNO displays the device's device number.  Most
  devices allow the device number to be changed with SET <device>
  DEVNO=nnn.
- Device number conflicts are not detected until simulation starts.
- Added variable size support and autosizing to the DF32 and RF08.

3.8 Nova

- Added variable size support and autosizing to the Novadisk.

3.9 AltairZ80

- A hard drive has been added for increased storage.
- Several bugs have been fixed.

3.10 HP 2100

- The 12845A has been added and made the default line printer (LPT).
  The 12653A has been renamed LPS and is off by default.  It also
  supports the diagnostic functions needed to run the DCPC and DMS
  diagnostics.
- The 12557A/13210A disk defaults to the 13210A (7900/7901).
- The 12559A magtape is off by default.
- New CPU options (EAU/NOEAU) enable/disable the extended arithmetic
  instructions for the 2116.  These instructions are standard on
  the 2100 and 21MX.
- New CPU options (MPR/NOMPR) enable/disable memory protect for the
  2100 and 21MX.
- New CPU options (DMS/NODMS) enable/disable the dynamic mapping
  instructions for the 21MX.
- The 12539 timebase generator autocalibrates.
- The IOP microinstruction set is supported for the 21MX as well
  as the 2100.
- The HP2100 supports the Access Interprocessor Link (IPL).

3.11 Simulated Magtapes

- Simulated magtapes recognize end of file and the marker
  0xFFFFFFFF as end of medium.  Only the TMSCP tape simulator
  can generate an end of medium marker.
- The error handling in simulated magtapes was overhauled to be
  consistent through all simulators.

3.12 Simulated DECtapes

- Added support for RT11 image file format (256 x 16b) to DECtapes.

3.13 Terminals Multiplexors

- BREAK detection was added to the HP, DEC, and Interdata terminal
  multiplexors.

4. Bugs Fixed in 2.10 vs prior releases

- TS11/TSV05 was not simulating the XS0_MOT bit, causing failures
  under VMS.  In addition, two of the CTL options were coded
  interchanged.
- IBM 1401 tape was not setting a word mark under group mark for
  load mode reads.  This caused the diagnostics to crash.
- SCP bugs in ssh_break and set_logon were fixed (found by Dave
  Hittner).
- Numerous bugs in the HP 2100 extended arithmetic, floating point,
  21MX, DMS, and IOP instructions were fixed.  Bugs were also fixed
  in the memory protect and DMS functions.  The moving head disks
  (DP, DQ) were revised to simulate the hardware more accurately.
  Missing functions in DQ (address skip, read address) were added.
- PDP-10 tape wouldn't boot, and then wouldn't read (reported by
  Michael Thompson and Harris Newman, respectively)
- PDP-1 typewriter is half duplex, with only one shift state for
  both input and output (found by Derek Peschel)
- PDP-11 console must default to 7b for early UNIX compatibility.
- PDP-11/VAX TMSCP emulator was using the wrong packet length for
  read/write end packets.
- Telnet IAC+IAC processing was fixed, both for input and output
  (found by Mark Pizzolato).
- PDP-11/VAX Ethernet setting flag bits wrong for chained
  descriptors (found by Mark Pizzolato).
- 18b PDP RF15/RF09: fixed IOT decoding and address wraparound
  logic (found by Hans Pufal).
- 18b PDP RP15: fixed IOT decoding and command initiation.
- HP2100 IPL: changed to full duplex (found by Mike Gemeny).
- HP2100 CPU: fixed last cycle bug in DMA outpout (found by Mike
  Gemeny).
- Interdata 16b CPU: fixed bug in SETM, SETMR (found by Mark
  Pizzolato).

5. General Notes

WARNING: The build procedures have changed.  There is only one UNIX
makefile.  To compile without Ethernet support, simply type

	gmake {target|all}

To compile with Ethernet support, type

	gmake USE_NETWORK=1 {target|all}

The Mingw batch files require Mingw release 2 and invoke the Unix
makefile.  There are still separate batch files for compilation
with or without Ethernet support.

WARNING: V2.10 has reorganized and renamed some of the definition
files for the PDP-10, PDP-11, and VAX.  Be sure to delete all
previous source files before you unpack the Zip archive, or
unpack it into a new directory structure.

WARNING: V2.10 has a new, more comprehensive save file format.
Restoring save files from previous releases will cause 'invalid
register' errors and loss of CPU option flags, device enable/
disable flags, unit online/offline flags, and unit writelock
flags.

WARNING: If you are using Visual Studio .NET through the IDE,
be sure to turn off the /Wp64 flag in the project settings, or
dozens of spurious errors will be generated.

WARNING: Compiling Ethernet support under Windows requires
extra steps; see the Ethernet readme file.  Ethernet support is
currently available only for Windows, Linux, NetBSD, and OpenBSD.
This commit is contained in:
Bob Supnik
2003-03-03 18:55:00 -08:00
committed by Mark Pizzolato
parent f20f5c629d
commit 43385c9616
72 changed files with 3065 additions and 2189 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
Interdata/id16_dboot.c
View File

@@ -303,23 +303,27 @@ static uint8 dboot_rom[] = {
struct dboot_id {
char *name;
uint32 sw;
uint32 cap;
uint32 dtype;
uint32 offset;
uint32 adder;
};
static struct dboot_id dboot_tab[] = {
{ "DP", 2, 0x31, o_DP0 },
{ "DP", 9, 0x33, o_DP0 },
{ "DM", 64, 0x35, o_ID0 },
{ "DM", 244, 0x36, o_ID0 },
{ "DP", 0, 2, 0x31, o_DP0, 0 },
{ "DP", SWMASK ('F'), 9, 0x32, o_DP0, o_DPF },
{ "DP", 0, 9, 0x33, o_DP0, 0 },
{ "DM", 0, 64, 0x35, o_ID0, 0 },
{ "DM", 0, 244, 0x36, o_ID0, 0 },
{ NULL } };
t_stat id_dboot (int32 u, DEVICE *dptr)
{
extern DIB pt_dib, sch_dib;
extern uint32 PC;
uint32 i, typ, ctlno, off, cap, sch_dev;
extern int32 sim_switches;
uint32 i, typ, ctlno, off, add, cap, sch_dev;
UNIT *uptr;
DIB *ddib = (DIB *) dptr->ctxt; /* get disk DIB */
@@ -331,13 +335,15 @@ for (i = typ = 0; dboot_tab[i].name != NULL; i++) {
if ((strcmp (dboot_tab[i].name, dptr->name) == 0) &&
(dboot_tab[i].cap == cap)) {
typ = dboot_tab[i].dtype;
off = dboot_tab[i].offset; } }
off = dboot_tab[i].offset;
add = dboot_tab[i].adder;
break; } }
if (typ == 0) return SCPE_NOFNC;
IOWriteBlk (DBOOT_BEG, DBOOT_LEN, dboot_rom); /* copy boot */
IOWriteB (AL_DEV, pt_dib.dno); /* bin input dev */
IOWriteB (AL_IOC, 0x99);
IOWriteB (AL_DSKU, ctlno + ((u + 1) * off)); /* disk param */
IOWriteB (AL_DSKU, ctlno + ((u + 1) * off) + add); /* disk param */
IOWriteB (AL_DSKT, typ);
IOWriteB (AL_DSKC, ctlno);
IOWriteB (AL_SCH, sch_dev);

149
Interdata/id16_sys.c
View File

@@ -22,6 +22,8 @@
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
27-Feb-03 RMS Added relative addressing support
*/
#include "id_defs.h"
@@ -42,8 +44,8 @@ extern UNIT cpu_unit;
extern REG cpu_reg[];
extern uint16 *M;
t_stat fprint_sym_m (FILE *of, t_addr addr, t_value *val);
t_stat parse_sym_m (char *cptr, t_addr addr, t_value *val);
t_stat fprint_sym_m (FILE *of, t_addr addr, t_value *val, t_bool cf);
t_stat parse_sym_m (char *cptr, t_addr addr, t_value *val, t_bool cf);
extern t_stat lp_load (FILE *fileref, char *cptr, char *fnam);
extern pt_dump (FILE *of, char *cptr, char *fnam);
@@ -297,7 +299,7 @@ if ((sw & SWMASK ('A')) || (sw & SWMASK ('C'))) { /* char format? */
return -(vp - 1); } /* return # chars */
if (sw & SWMASK ('M')) { /* inst format? */
r = fprint_sym_m (of, addr, val); /* decode inst */
r = fprint_sym_m (of, addr, val, uptr == &cpu_unit); /* decode inst */
if (r <= 0) return r; }
GETNUM (num, lnt); /* get number */
@@ -311,14 +313,15 @@ return -(vp - 1);
of = output stream
addr = current PC
*val = values to decode
cf = true if decoding for CPU
Outputs:
return = if >= 0, error code
if < 0, number of extra bytes retired
*/
t_stat fprint_sym_m (FILE *of, t_addr addr, t_value *val)
t_stat fprint_sym_m (FILE *of, t_addr addr, t_value *val, t_bool cf)
{
uint32 i, j, k, inst, r1, r2, ea, tgt, vp;
uint32 i, j, k, inst, r1, r2, ea, vp;
vp = 0;
GETNUM (inst, 2); /* first 16b */
@@ -328,40 +331,39 @@ for (i = 0; opcode[i] != NULL; i++) { /* loop thru ops */
if ((opc_val[i] & 0xFFFF) == (inst & masks[j])) { /* match? */
r1 = (inst >> 4) & 0xF;
r2 = inst & 0xF;
fprintf (of, "%s ", opcode[i]); /* print opcode */
switch (j) { /* case on class */
case I_V_MR: /* mask-register */
fprintf (of, "%s %-X,R%d", opcode[i], r1, r2);
return -1;
fprintf (of, "%-X,R%d", r1, r2);
return -1;
case I_V_RR: /* register-register */
case I_V_FF: /* floating-floating */
fprintf (of, "%s R%d,R%d", opcode[i], r1, r2);
return -1;
fprintf (of, "R%d,R%d", r1, r2);
return -1;
case I_V_SI: /* short immediate */
fprintf (of, "%s R%d,%-X", opcode[i], r1, r2);
return -1;
fprintf (of, "R%d,%-X", r1, r2);
return -1;
case I_V_SB: /* short branch */
if (inst & MSK_SBF) tgt = addr + r2 + r2;
else tgt = addr - r2 - r2;
fprintf (of, "%s %-X,%-X", opcode[i], r1, tgt);
return -1;
fprintf (of, "%-X,", r1);
case I_V_SX: /* ext short branch */
if (inst & MSK_SBF) tgt = addr + r2 + r2;
else tgt = addr - r2 - r2;
fprintf (of, "%s %-X", opcode[i], tgt);
return -1;
if (cf) fprintf (of, "%-X", ((inst & MSK_SBF)?
(addr + r2 + r2): (addr - r2 - r2)));
else fprintf (of, ((inst & MSK_SBF)?
".+%-X": ".-%X"), r2 + r2);
return -1;
case I_V_R: /* register */
fprintf (of, "%s R%d", opcode[i], r2);
return -1;
fprintf (of, "R%d", r2);
return -1;
case I_V_MX: /* mask-memory */
fprintf (of, "%s %-X,%-X", opcode[i], r1, ea);
break;
fprintf (of, "%-X,%-X", r1, ea);
break;
case I_V_RX: /* register-memory */
case I_V_FX: /* floating-memory */
fprintf (of, "%s R%d,%-X", opcode[i], r1, ea);
break;
fprintf (of, "R%d,%-X", r1, ea);
break;
case I_V_X: /* memory */
fprintf (of, "%s %-X", opcode[i], ea);
break; } /* end case */
fprintf (of, "%-X", ea);
break; } /* end case */
if (r2) fprintf (of, "(R%d)", r2);
return -3; } /* end if */
} /* end for */
@@ -398,6 +400,41 @@ if ((rtype == R_F) && (reg & 1)) return -1;
*optr = cptr + 1;
return reg;
}
/* Address
Inputs:
*cptr = pointer to input string
**tptr = pointer to moved pointer
*ea = effective address
*rel = relative flag
addr = base address
cf = true if parsing for CPU
Outputs:
status = SCPE_OK if ok, else error code
*/
t_stat get_addr (char *cptr, char **tptr, t_addr *ea, t_bool *rel,
t_addr addr, t_bool cf)
{
int32 sign = 1;
*ea = 0;
if (*cptr == '.') { /* relative? */
*rel = TRUE;
cptr++;
if (cf) *ea = addr;
if (*cptr == '+') cptr++; /* .+? */
else if (*cptr == '-') { /* .-? */
sign = -1;
cptr++; }
else return SCPE_OK; }
else *rel = FALSE;
errno = 0;
*ea = *ea + (sign * ((int32) strtoul (cptr, tptr, 16)));
if (errno || (cptr == *tptr)) return SCPE_ARG;
return SCPE_OK;
}
#define PUTNUM(d,n) for (k = n; k > 0; k--) \
val[vp++] = (d >> ((k - 1) * 8)) & 0xFF
@@ -431,9 +468,8 @@ if ((sw & SWMASK ('A')) || (sw & SWMASK ('C'))) { /* char format? */
val[vp++] = *cptr++; }
return -(vp - 1); } /* return # chars */
if (uptr == &cpu_unit) { /* cpu only */
r = parse_sym_m (cptr, addr, val); /* try to parse inst */
if (r <= 0) return r; }
r = parse_sym_m (cptr, addr, val, uptr == &cpu_unit); /* try to parse inst */
if (r <= 0) return r;
num = (int32) get_uint (cptr, rdx, maxv[lnt], &r); /* get number */
if (r != SCPE_OK) return r;
@@ -447,15 +483,17 @@ return -(lnt - 1);
*cptr = pointer to input string
addr = current PC
*val = pointer to output values
cf = true if parsing for CPU
Outputs:
status = > 0 error code
<= 0 -number of extra words
*/
t_stat parse_sym_m (char *cptr, t_addr addr, t_value *val)
t_stat parse_sym_m (char *cptr, t_addr addr, t_value *val, t_bool cf)
{
uint32 i, j, k, t, df, db, inst, ea, vp;
int32 r1, r2;
uint32 i, j, k, t, df, db, inst, vp;
int32 st, r1, r2;
t_bool rel;
t_stat r;
char *tptr, gbuf[CBUFSIZE];
@@ -488,9 +526,9 @@ case I_V_R: /* register */
case I_V_FX: /* float-memory */
case I_V_MX: case I_V_RX: /* mask/reg-mem */
case I_V_X: /* memory */
errno = 0;
ea = strtoul (gbuf, &tptr, 16); /* get address */
if (errno || (gbuf == tptr)) return SCPE_ARG; /* error? */
r = get_addr (gbuf, &tptr, &t, &rel, addr, cf); /* get addr */
if ((r != SCPE_OK) || (t > PAMASK16) ||
(!cf && rel)) return SCPE_ARG;
if (*tptr == '(') { /* index? */
if ((r2 = get_reg (tptr + 1, &tptr, R_R)) < 0)
return SCPE_ARG;
@@ -498,23 +536,34 @@ case I_V_X: /* memory */
inst = inst | r2; } /* or in R2 */
if (*tptr != 0) return SCPE_ARG;
PUTNUM (inst, 2);
PUTNUM (ea, 2);
PUTNUM (t, 2);
return -3;
case I_V_SB: case I_V_SX: /* short branches */
t = get_uint (gbuf, 16, DMASK16, &r); /* get addr */
if ((r != SCPE_OK) || (t & 1)) return r; /* error if odd */
db = (addr - t) & 0x1F; /* back displ */
df = (t - addr) & 0x1F; /* fwd displ */
if ((t == ((addr - db) & VAMASK16)) && /* back work and */
((j == I_V_SX) || !(inst & MSK_SBF))) { /* ext or back br? */
inst = inst | (db >> 1); /* or in back displ */
break; }
if ((t == ((addr + df) & VAMASK16)) && /* fwd work and */
((j == I_V_SX) || (inst & MSK_SBF))) { /* ext or fwd br? */
inst = inst | (df >> 1) | MSK_SBF; /* or in fwd displ */
break; }
return SCPE_ARG; } /* end case */
r = get_addr (gbuf, &tptr, &t, &rel, addr, cf); /* get addr */
if ((r != SCPE_OK) || (t & 1) || *tptr) /* error if odd */
return SCPE_ARG;
st = t; /* signed version */
if (cf) { /* for CPU? */
db = (addr - t) & 0x1F; /* back displ */
df = (t - addr) & 0x1F; /* fwd displ */
if ((t == ((addr - db) & VAMASK16)) && /* back work and */
((j == I_V_SX) || !(inst & MSK_SBF))) /* ext or back br? */
inst = inst | (db >> 1); /* or in back displ */
else if ((t == ((addr + df) & VAMASK16)) && /* fwd work and */
((j == I_V_SX) || (inst & MSK_SBF))) /* ext or fwd br? */
inst = inst | (df >> 1) | MSK_SBF; /* or in fwd displ */
else return SCPE_ARG; }
else if (rel) { /* periph, must be rel */
if ((st <= 0) && (st >= -0x1F) && /* relative back? */
((j == I_V_SX) || !(inst & MSK_SBF)))
inst = inst | ((-st & 0x1F) >> 1);
else if ((st >= 0) && (st < 0x1F) && /* relative fwd? */
((j == I_V_SX) || (inst & MSK_SBF)))
inst = inst | ((t & 0x1F) >> 1);
else return SCPE_ARG; }
else return SCPE_ARG; /* periph & ~rel, err */
} /* end case */
PUTNUM (inst, 2);
return -1;

37
Interdata/id32_cpu.c
View File

@@ -1,6 +1,6 @@
/* id32_cpu.c: Interdata 32b CPU simulator
Copyright (c) 2000-2002, Robert M. Supnik
Copyright (c) 2000-2003, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -740,7 +740,7 @@ case 0x63: /* LRA - RX */
break;
case 0x40: /* STH - RX */
WriteH (ea, R[r1] & DMASK16, VW); /* store register */
WriteH (ea, R[r1], VW); /* store register */
break;
case 0x50: /* ST - RX */
@@ -775,7 +775,7 @@ case 0x92: /* STBR - NO */
R[r2] = (R[r2] & ~DMASK8) | (R[r1] & DMASK8); /* store byte */
break;
case 0xD2: /* STB - RX */
WriteB (ea, R[r1] & DMASK8, VW); /* store byte */
WriteB (ea, R[r1], VW); /* store byte */
break;
case 0x34: /* EXHR - NO */
@@ -1291,7 +1291,7 @@ case 0xE3: /* SCP - RX */
else WriteB ((bufa + sr) & VAMASK, R[r1], VW); /* read, R1 to mem */
sr = sr + 1; /* inc count */
CC_GL_32 (sr & DMASK32); /* set cc's */
WriteH (t & VAMASK, sr & DMASK16, VW); /* rewrite */
WriteH (t & VAMASK, sr, VW); /* rewrite */
if ((sr > 0) && !(opnd & CCW32_FST)) /* buf switch? */
WriteH (ea, opnd ^ CCW32_B1, VW); /* flip CCW bit */
} /* end if */
@@ -1603,7 +1603,7 @@ slt = (t >> 16) & DMASK16; /* # slots */
usd = t & DMASK16; /* # used */
if (usd == 0) return CC_V; /* empty? */
usd = usd - 1; /* dec used */
WriteH (ea + Q32_USD, usd & DMASK16, VW); /* rewrite */
WriteH (ea + Q32_USD, usd, VW); /* rewrite */
if (flg) { /* RBL? */
rda = ReadH ((ea + Q32_BOT) & VAMASK, VR); /* get bottom */
if (rda == 0) rda = (slt - 1) & DMASK16; /* wrap if necc */
@@ -1673,7 +1673,7 @@ if (ccw & CCW32_FST) { /* fast mode? */
t = dev_tab[dev] (dev, IO_RD, 0); /* get byte */
WriteB (addr, t, VW); } /* write to mem */
bufc = bufc + 1; } /* adv buf cnt */
WriteH (ccwa + CCB32_B0C, bufc & DMASK16, VW);/* rewrite cnt */
WriteH (ccwa + CCB32_B0C, bufc, VW); /* rewrite cnt */
if (bufc > 0) {
PC = ReadH (ccwa + CCB32_SUB, VR); /* get subr */
return CC_G; } /* CC = G */
@@ -1709,7 +1709,7 @@ else { /* slow mode */
PC = t << 1; /* change PC */
R[3] = by; /* untrans char */
return 0; } /* CC = 0 */
WriteB (addr, t & DMASK8, VW); } /* wr trans */
WriteB (addr, t, VW); } /* wr trans */
else WriteB (addr, by, VW); } /* wr orig */
t = ReadH (ccwa + CCB32_CHK, VR); /* get check wd */
t = t ^ by; /* start LRC */
@@ -1719,7 +1719,7 @@ else { /* slow mode */
else t = t >> 1; } }
WriteH (ccwa + CCB32_CHK, t, VW); /* rewrite chk wd */
bufc = bufc + 1; /* adv buf cnt */
WriteH (ccwb, bufc & DMASK16, VW); /* rewrite cnt */
WriteH (ccwb, bufc, VW); /* rewrite cnt */
if (bufc > 0) { /* cnt pos? */
ccw = ccw ^ CCW32_B1; /* flip buf */
WriteH (ccwa, ccw, VW); /* rewrite */
@@ -1826,10 +1826,10 @@ uint32 val;
uint32 sc = (3 - (loc & 3)) << 3;
if ((PSW & PSW_REL) == 0) { /* reloc off? */
val = M[loc >> 2]; /* get mem word */
if ((loc & ~03) == MAC_STA) { /* MAC status? */
val = mac_sta; /* read it */
qevent = qevent & ~EV_MAC; } } /* clr MAC intr */
qevent = qevent & ~EV_MAC; } /* clr MAC intr */
else val = M[loc >> 2]; } /* get mem word */
else if (rel == 0) val = M[loc >> 2]; /* phys ref? */
else { uint32 pa = Reloc (loc, rel); /* relocate */
val = M[pa >> 2]; }
@@ -1841,10 +1841,10 @@ uint32 ReadH (uint32 loc, uint32 rel)
uint32 val;
if ((PSW & PSW_REL) == 0) { /* reloc off? */
val = M[loc >> 2]; /* get mem word */
if ((loc & ~03) == MAC_STA) { /* MAC status? */
val = mac_sta; /* read it */
qevent = qevent & ~EV_MAC; } } /* clr MAC intr */
qevent = qevent & ~EV_MAC; } /* clr MAC intr */
else val = M[loc >> 2]; } /* get mem word */
else if (rel == 0) val = M[loc >> 2]; /* phys ref? */
else { uint32 pa = Reloc (loc, rel); /* relocate */
val = M[pa >> 2]; }
@@ -1856,10 +1856,10 @@ uint32 ReadF (uint32 loc, uint32 rel)
uint32 val;
if ((PSW & PSW_REL) == 0) { /* reloc off? */
val = M[loc >> 2]; /* get mem word */
if ((loc & ~03) == MAC_STA) { /* MAC status? */
val = mac_sta; /* read it */
qevent = qevent & ~EV_MAC; } } /* clr MAC intr */
qevent = qevent & ~EV_MAC; } /* clr MAC intr */
else val = M[loc >> 2]; } /* get mem word */
else if (rel == 0) val = M[loc >> 2]; /* phys ref? */
else { uint32 pa = Reloc (loc, rel); /* relocate */
val = M[pa >> 2]; }
@@ -1894,9 +1894,9 @@ val = val & DMASK16;
if ((PSW & PSW_REL) == 0) { /* reloc off? */
uint32 idx = (pa - MAC_BASE) >> 2; /* check for MAC */
if (idx <= MAC_LNT) {
if (idx < MAC_LNT) mac_reg[idx] = ((loc & 2)?
((mac_reg[idx] & ~DMASK16) | val):
((mac_reg[idx] & DMASK16) | (val << 16))) & SR_MASK;
if (idx < MAC_LNT) mac_reg[idx] = ((loc & 2)?
((mac_reg[idx] & ~DMASK16) | val):
((mac_reg[idx] & DMASK16) | (val << 16))) & SR_MASK;
else {
mac_sta = 0;
qevent = qevent & ~EV_MAC; } } }
@@ -1911,6 +1911,7 @@ void WriteF (uint32 loc, uint32 val, uint32 rel)
{
uint32 pa = loc;
val = val & DMASK32;
if (loc & 2) {
WriteH (loc & VAMASK, (val >> 16) & DMASK16, rel);
WriteH ((loc + 2) & VAMASK, val & DMASK16, rel);
@@ -1918,7 +1919,7 @@ if (loc & 2) {
if ((PSW & PSW_REL) == 0) { /* reloc off? */
uint32 idx = (pa - MAC_BASE) >> 2; /* check for MAC */
if (idx <= MAC_LNT) {
if (idx < MAC_LNT) mac_reg[idx] = val & SR_MASK;
if (idx < MAC_LNT) mac_reg[idx] = val & SR_MASK;
else {
mac_sta = 0;
qevent = qevent & ~EV_MAC; } } }

37
Interdata/id32_dboot.c
View File

@@ -1,6 +1,6 @@
/* id32_dboot.c: Interdata 32b simulator disk bootstrap
Copyright (c) 2000-2002, Robert M. Supnik
Copyright (c) 2000-2003, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -22,6 +22,8 @@
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
17-Feb-03 RMS Fixed for UNIX bootstrap, upper platter bootstrap
*/
#include "id_defs.h"
@@ -140,7 +142,7 @@ static uint8 dboot_rom[] = {
0x11, 0xa5,
0x06, 0xba,
0x98, 0x49,
0xde, 0x4d, 0x03, 0x28,
0xde, 0x4d, 0x03, 0x2b,
0x9d, 0x3f,
0x22, 0x21,
0x9d, 0x4f,
@@ -265,23 +267,27 @@ static uint8 dboot_rom[] = {
struct dboot_id {
char *name;
uint32 sw;
uint32 cap;
uint32 dtype;
uint32 offset;
uint32 adder;
};
static struct dboot_id dboot_tab[] = {
{ "DP", 2, 0x31, o_DP0 },
{ "DP", 9, 0x33, o_DP0 },
{ "DM", 64, 0x35, o_ID0 },
{ "DM", 244, 0x36, o_ID0 },
{ "DP", 0, 2, 0x31, o_DP0, 0 },
{ "DP", SWMASK ('F'), 9, 0x32, o_DP0, o_DPF },
{ "DP", 0, 9, 0x33, o_DP0, 0 },
{ "DM", 0, 64, 0x35, o_ID0, 0 },
{ "DM", 0, 244, 0x36, o_ID0, 0 },
{ NULL } };
t_stat id_dboot (int32 u, DEVICE *dptr)
{
extern DIB pt_dib, sch_dib;
extern DIB ttp_dib, sch_dib;
extern uint32 PC;
uint32 i, typ, ctlno, off, cap, sch_dev;
extern int32 sim_switches;
uint32 i, typ, ctlno, off, add, cap, sch_dev;
UNIT *uptr;
DIB *ddib = (DIB *) dptr->ctxt; /* get disk DIB */
@@ -291,17 +297,20 @@ uptr = dptr->units + u; /* get capacity */
cap = uptr->capac >> 20;
for (i = typ = 0; dboot_tab[i].name != NULL; i++) {
if ((strcmp (dboot_tab[i].name, dptr->name) == 0) &&
((dboot_tab[i].sw == 0) || (dboot_tab[i].sw & sim_switches)) &&
(dboot_tab[i].cap == cap)) {
typ = dboot_tab[i].dtype;
off = dboot_tab[i].offset; } }
off = dboot_tab[i].offset;
add = dboot_tab[i].adder;
break; } }
if (typ == 0) return SCPE_NOFNC;
IOWriteBlk (DBOOT_BEG, DBOOT_LEN, dboot_rom); /* copy boot */
IOWriteB (AL_DEV, pt_dib.dno); /* bin input dev */
IOWriteB (AL_IOC, 0x99);
IOWriteB (AL_DSKU, ctlno + ((u + 1) * off)); /* disk param */
IOWriteB (AL_DSKT, typ);
IOWriteB (AL_DSKC, ctlno);
IOWriteB (AL_DEV, ttp_dib.dno); /* bin input dev */
IOWriteB (AL_IOC, 0xa3);
IOWriteB (AL_DSKU, ctlno + ((u + 1) * off) + add); /* disk dev addr */
IOWriteB (AL_DSKT, typ); /* disk type */
IOWriteB (AL_DSKC, ctlno); /* disk ctl addr */
IOWriteB (AL_SCH, sch_dev);
PC = DBOOT_START;
return SCPE_OK;

195
Interdata/id32_sys.c
View File

@@ -23,6 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
27-Feb-03 RMS Added relative addressing support
23-Dec-01 RMS Cloned from ID4 sources
*/
@@ -30,7 +31,7 @@
#include <ctype.h>
#define MSK_SBF 0x0100
#define SEXT15(x) (((x) & 0x4000)? ((x) | 0xFFFF8000): ((x) & 0x7FFF))
#define SEXT15(x) (((x) & 0x4000)? ((x) | ~0x3FFF): ((x) & 0x3FFF))
extern DEVICE cpu_dev;
extern DEVICE sch_dev;
@@ -45,8 +46,8 @@ extern UNIT cpu_unit;
extern REG cpu_reg[];
extern uint32 *M;
t_stat fprint_sym_m (FILE *of, t_addr addr, t_value *val);
t_stat parse_sym_m (char *cptr, t_addr addr, t_value *val);
t_stat fprint_sym_m (FILE *of, t_addr addr, t_value *val, t_bool cf);
t_stat parse_sym_m (char *cptr, t_addr addr, t_value *val, t_bool cf);
extern t_stat lp_load (FILE *fileref, char *cptr, char *fnam);
extern pt_dump (FILE *of, char *cptr, char *fnam);
@@ -286,7 +287,8 @@ static const uint32 opc_val[] = {
/* Print an RX specifier */
t_stat fprint_addr (FILE *of, t_addr addr, uint32 rx, uint32 ea1, uint32 ea2)
t_stat fprint_addr (FILE *of, t_addr addr, uint32 rx, uint32 ea1,
uint32 ea2, t_bool cf)
{
uint32 rx2;
@@ -295,8 +297,13 @@ if ((ea1 & 0xC000) == 0) { /* RX1 */
if (rx) fprintf (of, "(R%d)", rx);
return -3; }
if (ea1 & 0x8000) { /* RX2 */
ea1 = addr + 4 + SEXT15 (ea1);
fprintf (of, "%-X", ea1 & VAMASK32);
if (cf) { /* for CPU? */
ea1 = addr + 4 + SEXT15 (ea1);
fprintf (of, "%-X", ea1 & VAMASK32); }
else { /* for dev */
int32 disp = SEXT15 (ea1); /* get disp */
if (disp >= -4) fprintf (of, ".+%-X", disp + 4);
else fprintf (of, ".-%-X", -4 - disp); }
if (rx) fprintf (of, "(R%d)", rx);
return -3; }
rx2 = (ea1 >> 8) & 0xF;
@@ -351,7 +358,7 @@ if ((sw & SWMASK ('A')) || (sw & SWMASK ('C'))) { /* char format? */
return -(vp - 1); } /* return # chars */
if (sw & SWMASK ('M')) { /* inst format? */
r = fprint_sym_m (of, addr, val); /* decode inst */
r = fprint_sym_m (of, addr, val, uptr == &cpu_unit); /* decode inst */
if (r <= 0) return r; /* success? */
lnt = 2; } /* no, skip 16b */
@@ -366,14 +373,15 @@ return -(vp - 1);
of = output stream
addr = current PC
*val = values to decode
cf = true if parsing for CPU
Outputs:
return = if >= 0, error code
if < 0, number of extra bytes retired
*/
t_stat fprint_sym_m (FILE *of, t_addr addr, t_value *val)
t_stat fprint_sym_m (FILE *of, t_addr addr, t_value *val, t_bool cf)
{
uint32 i, j, k, inst, r1, r2, ea1, ea2, tgt, vp;
uint32 i, j, k, inst, r1, r2, ea1, ea2, vp;
vp = 0;
GETNUM (inst,2); /* high 16b */
@@ -384,49 +392,45 @@ for (i = 0; opc_val[i] != 0xFFFF; i++) { /* loop thru ops */
if ((opc_val[i] & 0xFFFF) == (inst & masks[j])) { /* match? */
r1 = (inst >> 4) & 0xF;
r2 = inst & 0xF;
fprintf (of, "%s ", opcode[i]); /* print opcode */
switch (j) { /* case on class */
case I_V_MR: /* mask-register */
fprintf (of, "%s %-X,R%d", opcode[i], r1, r2);
return -1;
fprintf (of, "%-X,R%d", r1, r2);
return -1;
case I_V_RR: /* register-register */
case I_V_FF: /* floating-floating */
fprintf (of, "%s R%d,R%d", opcode[i], r1, r2);
return -1;
fprintf (of, "R%d,R%d", r1, r2);
return -1;
case I_V_SI: /* short immediate */
fprintf (of, "%s R%d,%-X", opcode[i], r1, r2);
return -1;
fprintf (of, "R%d,%-X", r1, r2);
return -1;
case I_V_SB: /* short branch */
if (inst & MSK_SBF) tgt = addr + r2 + r2;
else tgt = addr - r2 - r2;
fprintf (of, "%s %-X,%-X", opcode[i], r1, tgt);
return -1;
fprintf (of, "%-X,", r1);
case I_V_SX: /* ext short branch */
if (inst & MSK_SBF) tgt = addr + r2 + r2;
else tgt = addr - r2 - r2;
fprintf (of, "%s %-X", opcode[i], tgt);
return -1;
if (cf) fprintf (of, "%-X", ((inst & MSK_SBF)?
(addr + r2 + r2): (addr - r2 - r2)));
else fprintf (of, ((inst & MSK_SBF)?
".+%-X": ".-%X"), r2 + r2);
return -1;
case I_V_R: /* register */
fprintf (of, "%s R%d", opcode[i], r2);
return -1;
fprintf (of, "R%d", r2);
return -1;
case I_V_RI: /* reg-immed */
fprintf (of, "%s R%d,%-X", opcode[i], r1, ea1);
if (r2) fprintf (of, "(R%d)", r2);
return -3;
fprintf (of, "R%d,%-X", r1, ea1);
if (r2) fprintf (of, "(R%d)", r2);
return -3;
case I_V_RF: /* reg-full imm */
fprintf (of, "%s R%d,%-X", opcode[i], r1,
(ea1 << 16) | ea2);
if (r2) fprintf (of, "(R%d)", r2);
return -5;
fprintf (of, "R%d,%-X", r1, (ea1 << 16) | ea2);
if (r2) fprintf (of, "(R%d)", r2);
return -5;
case I_V_MX: /* mask-memory */
fprintf (of, "%s %-X,", opcode[i], r1);
return fprint_addr (of, addr, r2, ea1, ea2);
fprintf (of, "%-X,", r1);
return fprint_addr (of, addr, r2, ea1, ea2, cf);
case I_V_RX: /* register-memory */
case I_V_FX: /* floating-memory */
fprintf (of, "%s R%d,", opcode[i], r1);
return fprint_addr (of, addr, r2, ea1, ea2);
fprintf (of, "R%d,", r1);
case I_V_X: /* memory */
fprintf (of, "%s ", opcode[i]);
return fprint_addr (of, addr, r2, ea1, ea2); }
return fprint_addr (of, addr, r2, ea1, ea2, cf); }
return SCPE_IERR; } /* end if */
} /* end for */
return SCPE_ARG; /* no match */
@@ -490,6 +494,41 @@ if (*tptr == '(') { /* index? */
if (*tptr != 0) return SCPE_ARG;
return SCPE_OK;
}
/* Address
Inputs:
*cptr = pointer to input string
**tptr = pointer to moved pointer
*ea = effective address
*rel = relative flag
addr = base address
cf = true if parsing for CPU
Outputs:
status = SCPE_OK if ok, else error code
*/
t_stat get_addr (char *cptr, char **tptr, t_addr *ea, t_bool *rel,
t_addr addr, t_bool cf)
{
int32 sign = 1;
*ea = 0;
if (*cptr == '.') { /* relative? */
*rel = TRUE;
cptr++;
if (cf) *ea = addr;
if (*cptr == '+') cptr++; /* .+? */
else if (*cptr == '-') { /* .-? */
sign = -1;
cptr++; }
else return SCPE_OK; }
else *rel = FALSE;
errno = 0;
*ea = *ea + (sign * ((int32) strtoul (cptr, tptr, 16)));
if (errno || (cptr == *tptr)) return SCPE_ARG;
return SCPE_OK;
}
#define PUTNUM(d,n) for (k = n; k > 0; k--) \
val[vp++] = (d >> ((k - 1) * 8)) & 0xFF
@@ -523,9 +562,8 @@ if ((sw & SWMASK ('A')) || (sw & SWMASK ('C'))) { /* char format? */
val[vp++] = *cptr++; }
return -(vp - 1); } /* return # chars */
if (uptr == &cpu_unit) { /* cpu only */
r = parse_sym_m (cptr, addr, val); /* try to parse inst */
if (r <= 0) return r; }
r = parse_sym_m (cptr, addr, val, uptr == &cpu_unit); /* try to parse */
if (r <= 0) return r;
num = (int32) get_uint (cptr, rdx, maxv[lnt], &r); /* get number */
if (r != SCPE_OK) return r;
@@ -539,16 +577,18 @@ return -(lnt - 1);
*cptr = pointer to input string
addr = current PC
*val = pointer to output values
cf = true if parsing for CPU
Outputs:
status = > 0 error code
<= 0 -number of extra words
*/
t_stat parse_sym_m (char *cptr, t_addr addr, t_value *val)
t_stat parse_sym_m (char *cptr, t_addr addr, t_value *val, t_bool cf)
{
uint32 i, j, k, t, df, db, inst, ea, vp;
uint32 i, j, k, df, db, t, inst, vp;
int32 st, r1, r2, rx2;
t_stat r;
t_bool rel;
char *tptr, gbuf[CBUFSIZE];
vp = 0;
@@ -580,9 +620,8 @@ case I_V_R: /* register */
case I_V_FX: /* float-memory */
case I_V_MX: case I_V_RX: /* mask/reg-memory */
case I_V_X: /* memory */
errno = 0;
ea = strtoul (gbuf, &tptr, 16); /* get address */
if (errno || (gbuf == tptr)) return SCPE_ARG; /* error? */
r = get_addr (gbuf, &tptr, &t, &rel, addr, cf); /* get addr */
if (r != SCPE_OK) return SCPE_ARG; /* error? */
rx2 = 0; /* assume no 2nd */
if (*tptr == '(') { /* index? */
if ((r2 = get_reg (tptr + 1, &tptr, R_R)) < 0)
@@ -594,47 +633,65 @@ case I_V_X: /* memory */
if (*tptr++ != ')') return SCPE_ARG; } /* all done? */
if (*tptr != 0) return SCPE_ARG;
PUTNUM (inst, 2); /* store inst */
if (!cf && rel) { /* periph, rel */
st = t - 4; /* displ */
if (rx2 || (st > 0x3FFF) || (st < -0x4000)) /* rx2 or too big? */
return SCPE_ARG;
t = (st & 0x7FFF) | 0x8000;
PUTNUM (t, 2); /* store displ */
return -3; }
if (rx2 == 0) { /* no 2nd? */
if (ea < 0x4000) { /* RX1? */
PUTNUM (ea, 2); /* store ea */
if (t < 0x4000) { /* RX1? */
PUTNUM (t, 2); /* store ea */
return -3; }
st = (ea - (addr + 4)); /* displ */
if ((st <= 0x3FFF) && (st >= -0x4000)) { /* RX2? */
st = (t - (addr + 4)); /* displ */
if (cf && (st <= 0x3FFF) && (st >= -0x4000)) { /* RX2? CPU only */
t = (st & 0x7FFF) | 0x8000;
PUTNUM (t, 2); /* store displ */
return -3; } }
ea = (ea & VAMASK32) | 0x40000000 | (rx2 << 24);
PUTNUM (ea, 4); /* RX3 */
t = (t & VAMASK32) | 0x40000000 | (rx2 << 24);
PUTNUM (t, 4); /* RX3 */
return -5;
case I_V_RI: /* 16b immediate */
r = get_imm (gbuf, &ea, &inst, DMASK16); /* process imm */
r = get_imm (gbuf, &t, &inst, DMASK16); /* process imm */
if (r != SCPE_OK) return r;
PUTNUM (inst, 2); /* store inst */
PUTNUM (ea, 2); /* store 16b imm */
PUTNUM (t, 2); /* store 16b imm */
return -3;
case I_V_RF:
r = get_imm (gbuf, &ea, &inst, DMASK32); /* process imm */
r = get_imm (gbuf, &t, &inst, DMASK32); /* process imm */
if (r != SCPE_OK) return r;
PUTNUM (inst, 2); /* store inst */
PUTNUM (ea, 4); /* store 32b imm */
PUTNUM (t, 4); /* store 32b imm */
return -5;
case I_V_SB: case I_V_SX: /* short branches */
t = get_uint (gbuf, 16, DMASK16, &r); /* get addr */
if ((r != SCPE_OK) || (t & 1)) return r; /* error if odd */
db = (addr - t) & 0x1F; /* back displ */
df = (t - addr) & 0x1F; /* fwd displ */
if ((t == ((addr - db) & VAMASK16)) && /* back work and */
((j == I_V_SX) || !(inst & MSK_SBF))) { /* ext or back br? */
inst = inst | (db >> 1); /* or in back displ */
break; }
if ((t == ((addr + df) & VAMASK16)) && /* fwd work and */
((j == I_V_SX) || (inst & MSK_SBF))) { /* ext or fwd br? */
inst = inst | (df >> 1) | MSK_SBF; /* or in fwd displ */
break; }
return SCPE_ARG; } /* end case */
r = get_addr (gbuf, &tptr, &t, &rel, addr, cf); /* get addr */
if ((r != SCPE_OK) || (t & 1) || *tptr) /* error if odd */
return SCPE_ARG;
st = t; /* signed version */
if (cf) { /* for CPU? */
db = (addr - t) & 0x1F; /* back displ */
df = (t - addr) & 0x1F; /* fwd displ */
if ((t == ((addr - db) & VAMASK16)) && /* back work and */
((j == I_V_SX) || !(inst & MSK_SBF))) /* ext or back br? */
inst = inst | (db >> 1); /* or in back displ */
else if ((t == ((addr + df) & VAMASK16)) && /* fwd work and */
((j == I_V_SX) || (inst & MSK_SBF))) /* ext or fwd br? */
inst = inst | (df >> 1) | MSK_SBF; /* or in fwd displ */
else return SCPE_ARG; }
else if (rel) { /* periph, must be rel */
if ((st <= 0) && (st >= -0x1F) && /* relative back? */
((j == I_V_SX) || !(inst & MSK_SBF)))
inst = inst | ((-st & 0x1F) >> 1);
else if ((st >= 0) && (st < 0x1F) && /* relative fwd? */
((j == I_V_SX) || (inst & MSK_SBF)))
inst = inst | ((t & 0x1F) >> 1);
else return SCPE_ARG; }
else return SCPE_ARG; /* periph & ~rel, err */
} /* end case */
PUTNUM (inst, 2);
return -1;

6
Interdata/id_defs.h
View File

@@ -25,6 +25,8 @@
The author gratefully acknowledges the help of Carl Friend and Al Kossow,
who provided key documents about the Interdata product line.
28-Feb-03 RMS Changed magtape device default to 0x85
*/
#include "sim_defs.h" /* simulator defns */
@@ -260,12 +262,12 @@ typedef struct interdib DIB;
#define d_LPT 0x62 /* line printer */
#define d_PIC 0x6C /* interval timer */
#define d_LFC 0x6D /* line freq clk */
#define d_MT 0x85 /* magtape */
#define o_MT0 0x10
#define d_DPC 0xB6 /* disk controller */
#define o_DP0 0x10
#define o_DPF 0x01 /* offset to fixed */
#define d_FD 0xC1 /* floppy disk */
#define d_MT 0xC5 /* magtape */
#define o_MT0 0x10
#define d_SCH 0xF0 /* selector chan */
#define d_IDC 0xFB /* MSM disk ctrl */
#define o_ID0 0x01

9
Interdata/id_diag.txt
View File

@@ -561,8 +561,8 @@ END OF TEST
---
Common magtape diagnostic
sim> set mt dev=85 ; 800 bpi default
sim> att -e pt0 diag.bin
sim> att mt foo.tap
sim> br c4
sim> boot pt0
@@ -577,9 +577,6 @@ COMMON MAGNETIC TAPE TEST PROGRAM 06-172R02
*MODE 0 ; prog i/o and selch
*RUN
*MODE 0
*RUN
TEST 00
NO ERROR
TEST 01
@@ -880,7 +877,7 @@ Bugs found
65. PIC, LFC: ric reloaded from output buffer on count overflow
66. PIC, LFC: added diagnostic mode, revised use of count vs timer
67. DP: track increment algorithm incorrect
68. DP,IDC: incorrectly setting overrun for less than full sector reads
68. DP, IDC: incorrectly setting overrun for less than full sector reads
69. DP: should interrupt on detach (offline)
70. FD: high water mark not updated on write
71. FD: deleted data not implemented, required for diagnostic
@@ -905,4 +902,6 @@ Bugs found
90. IDC: drive command 0x30 is an instant NOP
91. IDC: set cylinder with invalid cylinder sets SKI
92. IDC: read with invalid head sets ACF, not DTE
93. DP, IDC: write with cylinder overflow advanced selch pointer
94. MT: read error must stop selector channel (if active)

40
Interdata/id_doc.txt
View File

@@ -1,13 +1,13 @@
To: Users
From: Bob Supnik
Subj: Interdata 16b/32b Simulator Usage
Date: 15-Jan-2003
Date: 15-Mar-2003
COPYRIGHT NOTICE
The following copyright notice applies to both the SIMH source and binary:
Original code published in 1993-2002, written by Robert M Supnik
Original code published in 1993-2003, written by Robert M Supnik
Copyright (c) 1993-2003, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
@@ -91,7 +91,7 @@ DP 2.5MB/10MB cartridge disk
DM mass storage module (MSM)/intelligent (IDC) disk controller
MT magnetic tape
PAS programmable asynchronous line controller
PASL programmable asyhchronous lines, up to 32
PASL programmable asynchronous lines, up to 32
The Interdata simulator implements two unique stop conditions:
@@ -268,6 +268,10 @@ channels can be changed with the command:
SET SELCH CHANNELS=num
All the state for a selector channel can be displayed with the command:
SHOW SELCH num
The selector channels implement these registers:
name size comments
@@ -398,7 +402,7 @@ UC, 7B, or 8B. In UC mode, lower case input and output characters
are automatically converted to upper case. In 7B mode, input and
output characters are masked to 7 bits. In 8B mode, characters
are not modified. Changing the mode of either unit changes both.
The default mode is UC.
The default mode is 7B.
To simulate pressing the break key, stop the simulator and use
the command:
@@ -412,6 +416,8 @@ The PASLA console interface implements these registers:
name size comments
CMD 16 command register
STA 8 status register
KBUF 8 input buffer
KPOS 32 number of characters input
KTIME 24 input polling interval
@@ -480,7 +486,14 @@ Error handling is as follows:
2.4.5 Line Frequency Clock (LFC)
The line frequency clock (LFC) implements these registers:
The line frequency clock (LFC) frequency can be adjusted as follows:
SET LFC 60HZ set frequency to 60Hz
SET LFC 50HZ set frequency to 50Hz
The default is 60Hz.
The line frequency clock implements these registers:
name size comments
@@ -488,10 +501,9 @@ The line frequency clock (LFC) implements these registers:
IENB 1 clock interrupt enable
IARM 1 clock interrupt armed
TIME 24 clock frequency
TPS 8 ticks per second (120 or 100)
The real-time clock autocalibrates; the clock interval is adjusted up or
down so that the clock tracks actual elapsed time.
The line frequency clock autocalibrates; the clock interval is adjusted
up or down so that the clock tracks actual elapsed time.
2.4.6 Programmable Interval Clock (PIC)
@@ -509,8 +521,9 @@ The programmable interval clock (PIC) implements these registers:
IENB 1 clock interrupt enable
IARM 1 clock interrupt armed
If the interval requested is longer than 1 msec, the programmable clock
auto-calibrates; if not, it simply counts instructions.
If the interval requested is longer than 1 msec, and a multiple of
1 msec, the programmable clock auto-calibrates; if not, it simply
counts instructions.
2.4.7 Floppy Disk Controller (FD)
@@ -634,7 +647,8 @@ block 0, and uses that to locate the volume directory. It then searches
the directory for a filename of the form OS16xxxx.hhh or OS32xxxx.hhh,
where the xxxx is ignored and hhh is the ASCII form of the extension from
locations 7E:7F. The 32b bootstrap can also boot Wollongong UNIX; locations
7E:7F must be 0.
7E:7F must be 0. The bootstrap normally boots from the first (removable)
platter in a 5440; to boot from the second (fixed) platter, use BOOT -F.
All drives have 256 8b bytes per sector. The other disk parameters are:
@@ -877,7 +891,9 @@ number, optionally preceded by R, between 1 and F (15).
Instruction input uses standard Interdata assembler syntax. There are
nine instruction classes: short branch, extended short branch, short
immediate, 16b immediate, 32b immediate, register, register-register,
memory, and register-memory.
memory, and register-memory. Addresses, where required, can be
specified as either absolute numbers or relative to the current
location (.+n or .-n).
Short branch instructions have the format

23
Interdata/id_dp.c
View File

@@ -1,6 +1,6 @@
/* id_dp.c: Interdata 2.5MB/10MB cartridge disk simulator
Copyright (c) 2001-2002, Robert M. Supnik
Copyright (c) 2001-2003, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,8 @@
in this Software without prior written authorization from Robert M Supnik.
dp M46-421 2.5MB/10MB cartridge disk
16-Feb-03 RMS Fixed read to test transfer ok before selch operation
*/
#include "id_defs.h"
@@ -133,6 +135,7 @@ static struct drvtyp drv_tab[] = {
{ 0 } };
extern uint32 int_req[INTSZ], int_enb[INTSZ];
extern FILE *sim_log;
uint8 dpxb[DP_NUMBY]; /* xfer buffer */
uint32 dp_bptr = 0; /* buffer ptr */
@@ -148,6 +151,7 @@ uint32 dpd_arm[DP_NUMDR] = { 0 }; /* drives armed */
int32 dp_stime = 100; /* seek latency */
int32 dp_rtime = 100; /* rotate latency */
int32 dp_wtime = 1; /* word time */
int32 dp_log = 0; /* debug log */
uint8 dp_tplte[(2 * DP_NUMDR) + 2]; /* fix/rmv + ctrl + end */
DEVICE dp_dev;
@@ -208,6 +212,7 @@ REG dp_reg[] = {
DP_NUMDR, REG_RO) },
{ URDATA (CAPAC, dp_unit[0].capac, 10, 31, 0,
DP_NUMDR, PV_LEFT | REG_HRO) },
{ FLDATA (LOG, dp_log, 0), REG_HIDDEN },
{ HRDATA (DEVNO, dp_dib.dno, 8), REG_HRO },
{ HRDATA (SELCH, dp_dib.sch, 2), REG_HRO },
{ NULL } };
@@ -260,6 +265,8 @@ case IO_RD: /* read data */
else dp_sta = dp_sta | STA_BSY; /* xfr? set busy */
return dp_db; /* return data */
case IO_WD: /* write data */
if (sim_log && dp_log) fprintf (sim_log,
">>DPC WD = %02X, STA = %02X\n", dat, dp_sta);
if (dp_sta & STC_IDL) dp_hdsc = dat & HS_MASK; /* idle? hdsc */
else { /* data xfer */
dp_sta = dp_sta | STA_BSY; /* set busy */
@@ -270,6 +277,8 @@ case IO_SS: /* status */
if (t & SETC_EX) t = t | STA_EX; /* test for EX */
return t;
case IO_OC: /* command */
if (sim_log && dp_log) fprintf (sim_log,
">>DPC OC = %02X, STA = %02X\n", dat, dp_sta);
f = dat & CMC_MASK; /* get cmd */
if (f & CMC_CLR) { /* clear? */
dp_reset (&dp_dev); /* reset world */
@@ -305,6 +314,8 @@ case IO_ADR: /* select */
if (dp_sta & STC_IDL) dp_svun = dev; /* idle? save unit */
return BY; /* byte only */
case IO_WD: /* write data */
if (sim_log && dp_log) fprintf (sim_log,
">>DP%d WD = %02X, STA = %02X\n", u, dat, dp_sta);
if (GET_DTYPE (uptr->flags) == TYPE_2315) /* 2.5MB drive? */
dp_cyl = dat & 0xFF; /* cyl is 8b */
else dp_cyl = ((dp_cyl << 8) | dat) & DMASK16; /* insert byte */
@@ -318,6 +329,8 @@ case IO_SS: /* status */
if (t & SETD_EX) t = t | STA_EX; /* test for ex */
return t;
case IO_OC: /* command */
if (sim_log && dp_log) fprintf (sim_log,
">>DP%d OC = %02X, STA = %02X\n", u, dat, dp_sta);
dpd_arm[u] = int_chg (v_DPC + u + 1, dat, dpd_arm[u]);
if (dat & CMD_SK) t = dp_cyl; /* seek? get cyl */
else if (dat & CMD_RST) t = 0; /* rest? cyl 0 */
@@ -378,9 +391,9 @@ case CMC_RD: /* read */
case CMC_WR: /* write */
if (sch_actv (dp_dib.sch, dp_dib.dno)) { /* sch transfer? */
if (dp_dter (uptr, dp_1st)) return SCPE_OK; /* check xfr err */
dp_bptr = sch_rdmem (dp_dib.sch, dpxb, DP_NUMBY); /* read from mem */
dp_db = dpxb[dp_bptr - 1]; /* last byte */
if (dp_dter (uptr, dp_1st)) return SCPE_OK; /* check xfr err */
if (r = dp_wds (uptr)) return r; /* write sec, err? */
dp_1st = 0;
if (sch_actv (dp_dib.sch, dp_dib.dno)) { /* more to do? */
@@ -440,8 +453,10 @@ if (((uptr->flags & UNIT_ATT) == 0) || /* not attached? */
hd = GET_SRF (dp_hdsc); /* get head */
sc = GET_SEC (dp_hdsc); /* get sector */
if (dp_cyl != (uint32) uptr->CYL) { /* wrong cylinder? */
dp_done (STC_ACF); /* error, done */
return TRUE; }
if (dp_cyl == 0) uptr->CYL = 0;
else {
dp_done (STC_ACF); /* error, done */
return TRUE; } }
if (sc >= DP_NUMSC) { /* bad sector? */
dp_done (STC_OVR); /* error, done */
return TRUE; }

9
Interdata/id_idc.c
View File

@@ -1,6 +1,6 @@
/* id_idc.c: Interdata MSM/IDC disk controller simulator
Copyright (c) 2001-2002, Robert M. Supnik
Copyright (c) 2001-2003, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,8 @@
idc MSM/IDC disk controller
16-Feb-03 RMS Fixed read to test transfer ok before selch operation
Note: define flag ID_IDC to enable the extra functions of the intelligent
disk controller
*/
@@ -490,8 +492,7 @@ case CMC_RUNC: /* read uncorr */
#endif
case CMC_RD: /* read */
if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* sch transfer? */
if (idc_dter (uptr, idc_1st)) return SCPE_OK; /* dte? done */
/* fseek done */
if (idc_dter (uptr, idc_1st)) return SCPE_OK; /* dte? done */
if (r = idc_rds (uptr)) return r; /* read sec, err? */
idc_1st = 0;
t = sch_wrmem (idc_dib.sch, idcxb, IDC_NUMBY); /* write mem */
@@ -504,9 +505,9 @@ case CMC_RD: /* read */
case CMC_WR: /* write */
if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* sch transfer? */
if (idc_dter (uptr, idc_1st)) return SCPE_OK; /* dte? done */
idc_bptr = sch_rdmem (idc_dib.sch, idcxb, IDC_NUMBY); /* read mem */
idc_db = idcxb[idc_bptr - 1]; /* last byte */
if (idc_dter (uptr, idc_1st)) return SCPE_OK; /* dte? done */
if (r = idc_wds (uptr)) return r; /* write sec, err? */
idc_1st = 0;
if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* more to do? */

33
Interdata/id_io.c
View File

@@ -35,8 +35,7 @@
Interdata I/O uses the following interconnected tables:
dev_tab[dev] Indexed by device number, points to the I/O instruction
processing routine for the device. Initialized in the
device reset routine.
processing routine for the device.
sch_tab[dev] Indexed by device number, if non-zero, the number + 1
of the selector channel used by the device.
@@ -81,7 +80,8 @@ uint8 sch_tplte[SCH_NUMCH + 1]; /* dnum template */
uint32 sch (uint32 dev, uint32 op, uint32 dat);
void sch_ini (t_bool dtpl);
t_stat sch_reset (DEVICE *dptr);
t_stat sch_vchan (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat sch_set_nchan (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat sch_show_reg (FILE *st, UNIT *uptr, int32 val, void *desc);
/* Selector channel data structures
@@ -110,7 +110,15 @@ REG sch_reg[] = {
MTAB sch_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_VAL, 0, "channels", "CHANNELS",
&sch_vchan, NULL, &sch_reg[0] },
&sch_set_nchan, NULL, &sch_reg[0] },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "0", NULL,
NULL, &sch_show_reg, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "1", NULL,
NULL, &sch_show_reg, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 2, "2", NULL,
NULL, &sch_show_reg, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 3, "3", NULL,
NULL, &sch_show_reg, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
&set_dev, &show_dev, &sch_dib },
{ 0 } };
@@ -298,7 +306,7 @@ return SCPE_OK;
/* Set number of channels */
t_stat sch_vchan (UNIT *uptr, int32 val, char *cptr, void *desc)
t_stat sch_set_nchan (UNIT *uptr, int32 val, char *cptr, void *desc)
{
DEVICE *dptr;
DIB *dibp;
@@ -323,6 +331,21 @@ sch_reset_ch (sch_max); /* reset chan */
return SCPE_OK;
}
/* Show channel registers */
t_stat sch_show_reg (FILE *st, UNIT *uptr, int32 val, void *desc)
{
if (val < 0) return SCPE_IERR;
if (val >= (int32) sch_max) fprintf (st, "Channel %d disabled\n", val);
else { fprintf (st, "SA: %05X\n", sch_sa[val]);
fprintf (st, "EA: %05X\n", sch_ea[val]);
fprintf (st, "CMD: %02X\n", sch_cmd[val]);
fprintf (st, "DEV: %02X\n", sch_sdv[val]);
fprintf (st, "RDP: %X\n", sch_rdp[val]);
fprintf (st, "WDC: %X\n", sch_wdc[val]); }
return SCPE_OK;
}
/* Initialize template */
void sch_ini (t_bool dtpl)

183
Interdata/id_mt.c
View File

@@ -1,6 +1,6 @@
/* id_mt.c: Interdata magnetic tape simulator
Copyright (c) 2001-2002, Robert M Supnik
Copyright (c) 2001-2003, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,9 @@
mt M46-494 dual density 9-track magtape controller
28-Feb-03 RMS Revised for magtape library
20-Feb-03 RMS Fixed read to stop selch on error
Magnetic tapes are represented as a series of variable 8b records
of the form:
@@ -42,15 +45,11 @@
*/
#include "id_defs.h"
#include "sim_tape.h"
#define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */
#define UNIT_V_PNU (UNIT_V_UF + 1) /* pos not updated */
#define UNIT_WLK (1 << UNIT_V_WLK)
#define UNIT_PNU (1 << UNIT_V_PNU)
#define UST u3 /* unit status */
#define UCMD u4 /* unit command */
#define MT_MAXFR (1 << 16) /* max transfer */
#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */
/* Command - in UCMD */
@@ -98,15 +97,12 @@ static const uint8 bad_cmd[64] = {
DEVICE mt_dev;
uint32 mt (uint32 dev, uint32 op, uint32 dat);
t_bool mt_rdlntf (UNIT *uptr, t_mtrlnt *tbc, int32 *err);
t_bool mt_rdlntr (UNIT *uptr, t_mtrlnt *tbc, int32 *err);
t_bool mt_forwsp (UNIT *uptr, int32 *err);
t_bool mt_backsp (UNIT *uptr, int32 *err);
t_stat mt_svc (UNIT *uptr);
t_stat mt_reset (DEVICE *dptr);
t_stat mt_attach (UNIT *uptr, char *cptr);
t_stat mt_detach (UNIT *uptr);
t_stat mt_boot (int32 unitno, DEVICE *dptr);
t_stat mt_map_err (UNIT *uptr, t_stat st);
/* MT data structures
@@ -146,8 +142,8 @@ REG mt_reg[] = {
{ NULL } };
MTAB mt_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
&set_dev, &show_dev, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "SELCH", "SELCH",
@@ -200,7 +196,7 @@ case IO_OC: /* command */
if (((uptr->flags & UNIT_ATT) == 0) || /* ignore if unatt */
bad_cmd[f] || /* or bad cmd */
(((f == MTC_WR) || (f == MTC_WEOF)) && /* or write */
(uptr->flags & UNIT_WPRT))) break; /* and protected */
sim_tape_wrp (uptr))) break; /* and protected */
for (i = 0; i < MT_NUMDR; i++) { /* check other drvs */
if (sim_is_active (&mt_unit[i]) && /* active? */
(mt_unit[i].UCMD != MTC_REW)) { /* not rewind? */
@@ -238,16 +234,11 @@ return 0;
t_stat mt_svc (UNIT *uptr)
{
uint32 i, pnu;
int32 err;
uint32 i;
int32 u = uptr - mt_dev.units;
uint32 dev = mt_dib.dno + (u * o_MT0);
t_mtrlnt tbc;
static t_mtrlnt bceof = { 0 };
err = 0;
pnu = MT_TST_PNU (uptr); /* get pos not upd */
MT_CLR_PNU (uptr); /* and clear */
t_stat st, r = SCPE_OK;
if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
uptr->UCMD = 0; /* clr cmd */
@@ -274,8 +265,8 @@ if (uptr->UCMD & MTC_STOP1) { /* stop, gen EOM? */
switch (uptr->UCMD) { /* case on function */
case MTC_REW: /* rewind */
sim_tape_rewind (uptr); /* reposition */
uptr->UCMD = 0; /* clr cmd */
uptr->pos = 0; /* update position */
uptr->UST = STA_NMTN | STA_EOT; /* update status */
mt_sta = mt_sta & ~STA_BSY; /* don't set EOM */
if (mt_arm[u]) SET_INT (v_MT + u); /* interrupt */
@@ -293,16 +284,15 @@ case MTC_REW: /* rewind */
case MTC_RD: /* read */
if (mt_blnt == 0) { /* first time? */
if (mt_rdlntf (uptr, &tbc, &err)) break; /* read rec lnt, err? */
mt_blnt = tbc; /* set buf lnt */
if (tbc > MT_MAXFR) return SCPE_MTRLNT; /* record too long? */
i = fxread (mtxb, sizeof (uint8), mt_blnt, uptr->fileref);
if (err = ferror (uptr->fileref)) { /* error? */
MT_SET_PNU (uptr); /* pos not upd */
st = sim_tape_rdrecf (uptr, mtxb, &tbc, MT_MAXFR); /* read rec */
if (st == MTSE_RECE) mt_sta = mt_sta | STA_ERR; /* rec in err? */
else if (st != SCPE_OK) { /* other error? */
r = mt_map_err (uptr, st); /* map error */
if (sch_actv (mt_dib.sch, dev)) /* if sch, stop */
sch_stop (mt_dib.sch);
break; }
for ( ; i < mt_blnt; i++) mtxb[i] = 0; /* fill with 0's */
uptr->pos = uptr->pos + ((tbc + 1) & ~1) /* upd pos */
+ (2 * sizeof (t_mtrlnt)); }
mt_blnt = tbc; /* set buf lnt */
}
if (sch_actv (mt_dib.sch, dev)) { /* sch active? */
i = sch_wrmem (mt_dib.sch, mtxb, mt_blnt); /* store rec in mem */
@@ -334,114 +324,77 @@ case MTC_WR: /* write */
return SCPE_OK; }
if (mt_bptr) { /* any chars? */
int32 ebc = (mt_bptr + 1) & ~1; /* force even */
fseek (uptr->fileref, uptr->pos, SEEK_SET);
fxwrite (&mt_bptr, sizeof (t_mtrlnt), 1, uptr->fileref);
fxwrite (mtxb, sizeof (uint8), ebc, uptr->fileref);
fxwrite (&mt_bptr, sizeof (t_mtrlnt), 1, uptr->fileref);
if (err = ferror (uptr->fileref)) MT_SET_PNU (uptr);
else uptr->pos = uptr->pos + ebc + (2 * sizeof (t_mtrlnt)); }
if (st = sim_tape_wrrecf (uptr, mtxb, mt_bptr)) /* write, err? */
r = mt_map_err (uptr, st); } /* map error */
break; /* record done */
/* Unit service, continued */
case MTC_WEOF: /* write eof */
fseek (uptr->fileref, uptr->pos, SEEK_SET); /* set pos */
fxwrite (&bceof, sizeof (t_mtrlnt), 1, uptr->fileref);
if (err = ferror (uptr->fileref)) MT_SET_PNU (uptr);
else uptr->pos = uptr->pos + sizeof (t_mtrlnt); /* update pos */
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
r = mt_map_err (uptr, st); /* map error */
mt_sta = mt_sta | STA_EOF; /* set eof */
if (mt_arm[u]) SET_INT (v_MT + u); /* interrupt */
break;
case MTC_SKFF: /* skip file fwd */
while (mt_forwsp (uptr, &err)) ; /* spc until EOF/EOT */
while ((st = sim_tape_sprecf (uptr, &tbc)) == MTSE_OK) ;
if (st == MTSE_TMK) { /* stopped by tmk? */
mt_sta = mt_sta | STA_EOF; /* set eof */
if (mt_arm[u]) SET_INT (v_MT + u); } /* set intr */
else r = mt_map_err (uptr, st); /* map error */
break;
case MTC_SKFR: /* skip file rev */
while (mt_backsp (uptr, &err)) ; /* spc until EOF/BOT */
while ((st = sim_tape_sprecr (uptr, &tbc)) == MTSE_OK) ;
if (st == MTSE_TMK) { /* stopped by tmk? */
mt_sta = mt_sta | STA_EOF; /* set eof */
if (mt_arm[u]) SET_INT (v_MT + u); } /* set intr */
else r = mt_map_err (uptr, st); /* map error */
break;
case MTC_SPCR: /* backspace */
if (!pnu) mt_backsp (uptr, &err); /* if pos not upd */
if (st = sim_tape_sprecr (uptr, &tbc)) /* skip rec rev, err? */
r = mt_map_err (uptr, st); /* map error */
break; } /* end case */
if (err != 0) { /* I/O error */
mt_sta = mt_sta | STA_ERR;
perror ("MT I/O error");
clearerr (uptr->fileref);
if (mt_stopioe) return SCPE_IOERR; }
uptr->UCMD = uptr->UCMD | MTC_STOP1; /* set stop stage 1 */
sim_activate (uptr, mt_rtime); /* schedule */
return SCPE_OK;
return r;
}
/* Tape motion routines */
/* Map tape error status */
t_bool mt_rdlntf (UNIT *uptr, t_mtrlnt *tbc, int32 *err)
t_stat mt_map_err (UNIT *uptr, t_stat st)
{
int32 u = uptr - mt_dev.units;
fseek (uptr->fileref, uptr->pos, SEEK_SET); /* position */
fxread (tbc, sizeof (t_mtrlnt), 1, uptr->fileref); /* get bc */
if ((*err = ferror (uptr->fileref)) || /* err or eom? */
feof (uptr->fileref) || (*tbc == MTR_EOM)) {
mt_sta = mt_sta | STA_ERR; /* set err */
MT_SET_PNU (uptr); /* pos not upd */
return TRUE; }
if (*tbc == MTR_TMK) { /* tape mark? */
switch (st) {
case MTSE_FMT: /* illegal fmt */
case MTSE_UNATT: /* not attached */
mt_sta = mt_sta | STA_ERR;
case MTSE_OK: /* no error */
return SCPE_IERR;
case MTSE_TMK: /* end of file */
mt_sta = mt_sta | STA_EOF; /* set eof */
if (mt_arm[u]) SET_INT (v_MT + u); /* set intr */
uptr->pos = uptr->pos + sizeof (t_mtrlnt); /* update pos */
return TRUE; }
*tbc = MTRL (*tbc);
return FALSE;
}
t_bool mt_rdlntr (UNIT *uptr, t_mtrlnt *tbc, int32 *err)
{
int32 u = uptr - mt_dev.units;
if (uptr->pos < sizeof (t_mtrlnt)) { /* at bot? */
break;
case MTSE_IOERR: /* IO error */
mt_sta = mt_sta | STA_ERR; /* set err */
if (mt_stopioe) return SCPE_IOERR;
break;
case MTSE_INVRL: /* invalid rec lnt */
mt_sta = mt_sta | STA_ERR;
return SCPE_MTRLNT;
case MTSE_WRP: /* write protect */
case MTSE_RECE: /* record in error */
case MTSE_EOM: /* end of medium */
mt_sta = mt_sta | STA_ERR; /* set err */
break;
case MTSE_BOT: /* reverse into BOT */
uptr->UST = uptr->UST | STA_EOT; /* set err */
return TRUE; }
fseek (uptr->fileref, uptr->pos - sizeof (t_mtrlnt), SEEK_SET);
fxread (tbc, sizeof (t_mtrlnt), 1, uptr->fileref); /* get bc */
if ((*err = ferror (uptr->fileref)) || /* err or eof? */
feof (uptr->fileref)) {
mt_sta = mt_sta | STA_ERR; /* set err */
return TRUE; }
if (*tbc == MTR_EOM) { /* eom? */
mt_sta = mt_sta | STA_ERR; /* set err */
uptr->pos = uptr->pos - sizeof (t_mtrlnt); /* update pos */
return TRUE; }
if (*tbc == MTR_TMK) { /* tape mark? */
mt_sta = mt_sta | STA_EOF; /* set eof */
if (mt_arm[u]) SET_INT (v_MT + u); /* set intr */
uptr->pos = uptr->pos - sizeof (t_mtrlnt); /* update pos */
return TRUE; }
*tbc = MTRL (*tbc);
return FALSE;
}
t_bool mt_forwsp (UNIT *uptr, int32 *err)
{
t_mtrlnt tbc;
if (mt_rdlntf (uptr, &tbc, err)) return FALSE; /* read rec lnt, err? */
uptr->pos = uptr->pos + ((tbc + 1) & ~1) + /* space to next rec */
(2 * sizeof (t_mtrlnt));
return TRUE;
}
t_bool mt_backsp (UNIT *uptr, int32 *err)
{
t_mtrlnt tbc;
if (mt_rdlntr (uptr, &tbc, err)) return FALSE; /* read rec lnt, err? */
uptr->pos = uptr->pos - ((tbc + 1) & ~1) - /* space to prv rec */
(2 * sizeof (t_mtrlnt));
return TRUE;
break; } /* end switch */
return SCPE_OK;
}
/* Reset routine */
@@ -459,7 +412,7 @@ for (u = 0; u < MT_NUMDR; u++) { /* loop thru units */
CLR_ENB (v_MT + u); /* disable int */
mt_arm[u] = 0; /* disarm int */
uptr = mt_dev.units + u;
MT_CLR_PNU (uptr); /* clear pos flag */
sim_tape_reset (uptr); /* clear pos flag */
sim_cancel (uptr); /* cancel activity */
uptr->UST = (uptr->UST & STA_UFLGS) | STA_NMTN; /* init status */
uptr->UCMD = 0; } /* init cmd */
@@ -473,10 +426,8 @@ t_stat mt_attach (UNIT *uptr, char *cptr)
int32 u = uptr - mt_dev.units;
t_stat r;
r = attach_unit (uptr, cptr);
r = sim_tape_attach (uptr, cptr);
if (r != SCPE_OK) return r;
uptr->pos = 0;
MT_CLR_PNU (uptr);
uptr->UST = STA_EOT;
if (mt_arm[u]) SET_INT (v_MT + u);
return r;
@@ -489,11 +440,9 @@ t_stat mt_detach (UNIT* uptr)
int32 u = uptr - mt_dev.units;
t_stat r;
if ((uptr->flags & UNIT_ATT) == 0) return SCPE_OK;
r = detach_unit (uptr);
r = sim_tape_detach (uptr);
if (r != SCPE_OK) return r;
if (mt_arm[u]) SET_INT (v_MT + u);
MT_CLR_PNU (uptr);
uptr->UST = 0;
return SCPE_OK;
}
@@ -518,7 +467,7 @@ extern DIB sch_dib;
uint32 sch_dev;
if (decrom[0xD5] & dec_flgs) return SCPE_NOFNC; /* AL defined? */
mt_unit[unitno].pos = 0; /* rewind */
sim_tape_rewind (&mt_unit[unitno]); /* rewind */
sch_dev = sch_dib.dno + mt_dib.sch; /* sch dev # */
IOWriteBlk (BOOT_START, BOOT_LEN, boot_rom); /* copy boot */
IOWriteB (AL_DEV, mt_dib.dno + (unitno * o_MT0)); /* set dev no for unit */

2
Interdata/id_pt.c
View File

@@ -23,7 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
pt paper tape reader and punch
pt paper tape reader and punch
*/
#include "id_defs.h"

2
Interdata/id_tt.c
View File

@@ -23,7 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
tt console
tt console
11-Jan-03 RMS Added TTP support
22-Dec-02 RMS Added break support

6
Interdata/id_ttp.c
View File

@@ -23,7 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
ttp console (on PAS)
ttp console (on PAS)
*/
#include "id_defs.h"
@@ -76,8 +76,8 @@ extern int32 pas_par (int32 cmd, int32 c);
DIB ttp_dib = { d_TTP, -1, v_TTP, ttp_tplte, &ttp, NULL };
UNIT ttp_unit[] = {
{ UDATA (&ttpi_svc, UNIT_UC, 0), KBD_POLL_WAIT },
{ UDATA (&ttpo_svc, UNIT_UC, 0), SERIAL_OUT_WAIT }
{ UDATA (&ttpi_svc, 0, 0), KBD_POLL_WAIT },
{ UDATA (&ttpo_svc, 0, 0), SERIAL_OUT_WAIT }
};
REG ttp_reg[] = {

67
Interdata/id_uvc.c
View File

@@ -23,8 +23,11 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
pic precision incremental clock
lfc line frequency clock
pic precision incremental clock
lfc line frequency clock
01-Mar-03 RMS Added SET/SHOW LFC FREQ support
Changed precision clock algorithm for V7 UNIX
*/
#include "id_defs.h"
@@ -56,7 +59,9 @@ uint32 pic_rdp = 0;
uint32 pic_wdp = 0;
uint32 pic_cnti = 0; /* instr/timer */
uint32 pic_arm = 0; /* int arm */
uint32 pic_decr = 1; /* decrement */
uint16 pic_time[4] = { 1, 10, 100, 1000 }; /* delays */
uint16 pic_usec[4] = { 1, 10, 100, 1000 }; /* usec per tick */
static int32 pic_map[16] = { /* map rate to delay */
0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0 };
@@ -74,6 +79,8 @@ DEVICE lfc_dev;
uint32 lfc (uint32 dev, uint32 op, uint32 dat);
t_stat lfc_svc (UNIT *uptr);
t_stat lfc_reset (DEVICE *dptr);
t_stat lfc_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat lfc_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);
/* PIC data structures
@@ -90,7 +97,6 @@ REG pic_reg[] = {
{ HRDATA (BUF, pic_db, 16) },
{ HRDATA (RIC, pic_ric, 16) },
{ HRDATA (CIC, pic_cic, 12) },
{ DRDATA (SAVE, pic_save, 32), REG_HRO + PV_LEFT },
{ FLDATA (RDP, pic_rdp, 0) },
{ FLDATA (WDP, pic_wdp, 0) },
{ FLDATA (OVF, pic_ovf, 0) },
@@ -98,6 +104,9 @@ REG pic_reg[] = {
{ FLDATA (IENB, int_enb[l_PIC], i_PIC) },
{ FLDATA (IARM, pic_arm, 0) },
{ BRDATA (TIME, pic_time, 10, 16, 4), REG_NZ + PV_LEFT },
{ DRDATA (SAVE, pic_save, 32), REG_HRO + PV_LEFT },
{ DRDATA (DECR, pic_decr, 16), REG_HRO + PV_LEFT },
{ FLDATA (MODE, pic_cnti, 0), REG_HRO },
{ HRDATA (DEVNO, pic_dib.dno, 8), REG_HRO },
{ NULL } };
@@ -131,11 +140,17 @@ REG lfc_reg[] = {
{ FLDATA (IENB, int_enb[l_LFC], i_LFC) },
{ FLDATA (IARM, lfc_arm, 0) },
{ DRDATA (TIME, lfc_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS, lfc_tps, 8), REG_NZ + PV_LEFT },
{ DRDATA (TPS, lfc_tps, 8), PV_LEFT + REG_HRO },
{ HRDATA (DEVNO, lfc_dib.dno, 8), REG_HRO },
{ NULL } };
MTAB lfc_mod[] = {
{ MTAB_XTD|MTAB_VDV, 100, NULL, "50HZ",
&lfc_set_freq, NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 120, NULL, "60HZ",
&lfc_set_freq, NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "FREQUENCY", NULL,
NULL, &lfc_show_freq, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
&set_dev, &show_dev, NULL },
{ 0 } };
@@ -200,9 +215,9 @@ t_stat pic_svc (UNIT *uptr)
{
t_bool rate_chg = FALSE;
if (pic_cnti) pic_cic = -1; /* one shot? */
pic_cic = pic_cic - 1; /* decrement */
if (pic_cic < 0) { /* overflow? */
if (pic_cnti) pic_cic = 0; /* one shot? */
pic_cic = pic_cic - pic_decr; /* decrement */
if (pic_cic <= 0) { /* overflow? */
if (pic_wdp) pic_ovf = 1; /* broken wr? set flag */
if (pic_arm) SET_INT (v_PIC); /* if armed, intr */
if (GET_RATE (pic_ric) != GET_RATE (pic_db)) /* rate change? */
@@ -216,23 +231,27 @@ return SCPE_OK;
/* Schedule next interval
If rate < 1ms, or diagnostic mode, count instructions
If rate = 1ms, and not diagnostic mode, use timer
If eff rate < 1ms, or diagnostic mode, count instructions
If eff rate = 1ms, and not diagnostic mode, use timer
*/
void pic_sched (t_bool strt)
{
int32 r, t;
int32 r, t, intv, intv_usec;
pic_save = sim_grtime (); /* save start */
r = pic_map[GET_RATE (pic_ric)]; /* get mapped rate */
t = pic_time[r]; /* get delay */
if ((r == 3) && !(pic_unit.flags & UNIT_DIAG)) { /* timer? */
intv = pic_cic? pic_cic: 1; /* get cntr */
intv_usec = intv * pic_usec[r]; /* cvt to usec */
if (!(pic_unit.flags & UNIT_DIAG) && /* not diag? */
((intv_usec % 1000) == 0)) { /* 1ms multiple? */
pic_cnti = 0; /* clr mode */
if (strt) t = sim_rtcn_init (t, TMR_PIC); /* init or */
pic_decr = pic_usec[3 - r]; /* set decrement */
if (strt) t = sim_rtcn_init (pic_time[3], TMR_PIC); /* init or */
else t = sim_rtcn_calb (PIC_TPS, TMR_PIC); } /* calibrate */
else { pic_cnti = 1; /* set mode */
t = t * (pic_cic + 1); /* interval */
pic_decr = 1; /* decr = 1 */
t = pic_time[r] * intv; /* interval */
if (t == 1) t++; } /* for diagn */
sim_activate (&pic_unit, t); /* activate */
return;
@@ -260,6 +279,7 @@ pic_ric = pic_cic = 0;
pic_db = 0;
pic_ovf = 0; /* clear state */
pic_cnti = 0;
pic_decr = 1;
pic_rdp = pic_wdp = 0;
CLR_INT (v_PIC); /* clear int */
CLR_ENB (v_PIC); /* disable int */
@@ -309,3 +329,22 @@ CLR_ENB (v_LFC); /* disable int */
lfc_arm = 0; /* disarm int */
return SCPE_OK;
}
/* Set frequency */
t_stat lfc_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc)
{
if (cptr) return SCPE_ARG;
if ((val != 100) && (val != 120)) return SCPE_IERR;
lfc_tps = val;
return SCPE_OK;
}
/* Show frequency */
t_stat lfc_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc)
{
fprintf (st, (lfc_tps == 100)? "50Hz": "60Hz");
return SCPE_OK;
}