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SCP: Fix timer initialization logic when CAS intrinsic instructions aren't available for Lock Free queue insertion

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Mark Pizzolato
2015-01-19 16:36:19 -08:00
parent 433fa20c03
commit 4fbf8f36db
1 changed files with 3 additions and 1 deletions
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4
sim_defs.h
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@@ -1229,6 +1229,7 @@ extern int32 sim_asynch_inst_latency;
#define AIO_QUEUE_MODE "Lock based asynchronous event queue access" #define AIO_QUEUE_MODE "Lock based asynchronous event queue access"
#define AIO_INIT \ #define AIO_INIT \
if (1) { \ if (1) { \
int tmr; \
pthread_mutexattr_t attr; \ pthread_mutexattr_t attr; \
\ \
pthread_mutexattr_init (&attr); \ pthread_mutexattr_init (&attr); \
@@ -1242,7 +1243,8 @@ extern int32 sim_asynch_inst_latency;
sim_asynch_queue = QUEUE_LIST_END; \ sim_asynch_queue = QUEUE_LIST_END; \
sim_wallclock_queue = QUEUE_LIST_END; \ sim_wallclock_queue = QUEUE_LIST_END; \
sim_wallclock_entry = NULL; \ sim_wallclock_entry = NULL; \
sim_clock_cosched_queue = QUEUE_LIST_END; \ for (tmr=0; tmr<SIM_NTIMERS; tmr++) \
sim_clock_cosched_queue[tmr] = QUEUE_LIST_END; \
} \ } \
else \ else \
(void)0 (void)0