Notes For V3.0-0

Because some key files have changed, V3.0 should be unzipped to a
clean directory.

1. New Features in 3.0-0

1.1 SCP and Libraries

- Added ASSIGN/DEASSIGN (logical name) commands.
- Changed RESTORE to unconditionally detach files.
- Added E11 and TPC format support to magtape library.
- Fixed bug in SHOW CONNECTIONS.
- Added USE_ADDR64 support

1.2 All magtapes

- Magtapes support SIMH format, E11 format, and TPC format (read only).
- SET <tape_unit> FORMAT=format sets the specified tape unit's format.
- SHOW <tape_unit> FORMAT displays the specified tape unit's format.
- Tape format can also be set as part of the ATTACH command, using
  the -F switch.

1.3 VAX

- VAX can be compiled without USE_INT64.
- If compiled with USE_INT64 and USE_ADDR64, RQ and TQ controllers support
  files > 2GB.
- VAX ROM has speed control (SET ROM DELAY/NODELAY).

2. Bugs Fixed in 3.01-0

2.1 VAX

- Fixed CVTfi bug: integer overflow not set if exponent out of range
- Fixed EMODx bugs:
  o First and second operands reversed
  o Separated fraction received wrong exponent
  o Overflow calculation on separated integer incorrect
  o Fraction not set to zero if exponent out of range
- Fixed interval timer and ROM access to pass power-up self-test even on very
  fast host processors (fixes from Mark Pizzolato).

2.2 1401

- Fixed mnemonic, instruction lengths, and reverse scan length check bug for MCS.
- Fixed MCE bug, BS off by 1 if zero suppress.
- Fixed chaining bug, D lost if return to SCP.
- Fixed H branch, branch occurs after continue.
- Added check for invalid 8 character MCW, LCA.
- Fixed magtape load-mode end of record response.

2.3 Nova

- Fixed DSK variable size interaction with restore.

2.4 PDP-1

- Fixed DT variable size interaction with restore.

2.5 PDP-11

- Fixed DT variable size interaction with restore.
- Fixed bug in MMR1 update (found by Tim Stark).
- Added XQ features and fixed bugs:
  o Corrected XQ interrupts on IE state transition (code by Tom Evans).
  o Added XQ interrupt clear on soft reset.
  o Removed XQ interrupt when setting XL or RL (multiple people).
  o Added SET/SHOW XQ STATS.
  o Added SHOW XQ FILTERS.
  o Added ability to split received packet into multiple buffers.
  o Added explicit runt and giant packet processing.

2.6 PDP-18B

- Fixed DT, RF variable size interaction with restore.
- Fixed MT bug in MTTR.

2.7 PDP-8

- Fixed DT, DF, RF, RX variable size interaction with restore.
- Fixed MT bug in SKTR.

2.8 HP2100

- Fixed bug in DP (13210A controller only), DQ read status.
- Fixed bug in DP, DQ seek complete.

2.9 GRI

- Fixed bug in SC queue pointer management.

3. New Features in 3.0 vs prior releases

N/A

4. Bugs Fixed in 3.0 vs prior releases

N/A

5. General Notes

WARNING: The RESTORE command has changed.  RESTORE will now
detach an attached file on a unit, if that unit did not have
an attached file in the saved configuration.  This is required
to assure that the unit flags and the file state are consistent.

WARNING: The compilation scheme for the PDP-10, PDP-11, and VAX
has changed.  Use one of the supplied build files, or read the
documentation carefully, before compiling any of these simulators.

GRI/gri_cpu.c

@@ -1,6 +1,6 @@
 /* gri_cpu.c: GRI-909 CPU simulator
 
-   Copyright (c) 2001-2002, Robert M. Supnik
+   Copyright (c) 2001-2003, Robert M. Supnik
 
    Permission is hereby granted, free of charge, to any person obtaining a
    copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,10 @@
    be used in advertising or otherwise to promote the sale, use or other dealings
    in this Software without prior written authorization from Robert M Supnik.
 
+   cpu		GRI-909 CPU
+
+   14-Mar-03	RMS	Fixed bug in SC queue tracking
+
    The system state for the GRI-909 is:
 
    AX<0:15>		arithmetic input
@@ -167,6 +171,7 @@ uint32 stop_opr = 1;					/* stop ill operator */
 int16 scq[SCQ_SIZE] = { 0 };				/* PC queue */
 int32 scq_p = 0;					/* PC queue ptr */
 REG *scq_r = NULL;					/* PC queue reg ptr */
+
 extern int32 sim_interval;
 extern int32 sim_int_char;
 extern int32 sim_brk_types, sim_brk_dflt, sim_brk_summ;	/* breakpoint info */
@@ -340,7 +345,7 @@ REG cpu_reg[] = {
 	{ FLDATA (ION, dev_done, INT_V_ON) },
 	{ FLDATA (INODEF, dev_done, INT_V_NODEF) },
 	{ FLDATA (BKP, bkp, 0) },
-	{ BRDATA (SCQ, scq, 8, 15, SCQ_SIZE), REG_RO+REG_CIRC },
+	{ BRDATA (SCQ, scq, 8, 15, SCQ_SIZE), REG_RO + REG_CIRC },
 	{ ORDATA (SCQP, scq_p, 6), REG_HRO },
 	{ FLDATA (STOP_OPR, stop_opr, 0) },
 	{ ORDATA (WRU, sim_int_char, 8) },
@@ -475,7 +480,7 @@ else if ((src != U_MEM) && (dst != U_MEM)) {		/* reg-reg? */
 /* Memory reference.  The second SC increment occurs after the first
    execution cycle.  For direct, defer, and immediate defer, this is
    after the first memory read and before the bus transfer; but for
-   immediate, it is before the bus transfer.
+   immediate, it is after the bus transfer.
 */
 
 else {	SC = (SC + 1) & AMASK;				/* incr SC */
@@ -512,6 +517,7 @@ else {	SC = (SC + 1) & AMASK;				/* incr SC */
 /* Simulation halted */
 
 AO = ao_update ();					/* update AO */
+scq_r->qptr = scq_p;					/* update sc q ptr */
 return reason;
 }
 
@@ -871,7 +877,7 @@ return SCPE_OK;
 t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
 {
 int32 mc = 0;
-t_addr i;
+uint32 i;
 
 if ((val <= 0) || (val > MAXMEMSIZE) || ((val & 07777) != 0))
 	return SCPE_ARG;

GRI/gri_defs.h

@@ -1,6 +1,6 @@
 /* gri_defs.h: GRI-909 simulator definitions 
 
-   Copyright (c) 2001-2002, Robert M. Supnik
+   Copyright (c) 2001-2003, Robert M. Supnik
 
    Permission is hereby granted, free of charge, to any person obtaining a
    copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,7 @@
    be used in advertising or otherwise to promote the sale, use or other dealings
    in this Software without prior written authorization from Robert M Supnik.
 
+   25-Apr-03	RMS	Revised for extended file support
    19-Sep-02	RMS	Fixed declarations in gdev structure
 
    There are several discrepancies between the original GRI-909 Reference
@@ -65,7 +66,7 @@
 #define MAXMEMSIZE	32768				/* max memory size */
 #define AMASK		077777				/* logical addr mask */
 #define MEMSIZE		(cpu_unit.capac)		/* actual memory size */
-#define MEM_ADDR_OK(x)	(((t_addr) (x)) < MEMSIZE)
+#define MEM_ADDR_OK(x)	(((uint32) (x)) < MEMSIZE)
 
 /* Architectural constants */
 

GRI/gri_doc.txt

@@ -1,14 +1,14 @@
 To:	Users
 From:	Bob Supnik
 Subj:	GRI-909 Simulator Usage
-Date:	15-Nov-2002
+Date:	20-Apr-2003
 
 			COPYRIGHT NOTICE
 
 The following copyright notice applies to both the SIMH source and binary:
 
-   Original code published in 1993-2002, written by Robert M Supnik
-   Copyright (c) 1993-2002, Robert M Supnik
+   Original code published in 1993-2003, written by Robert M Supnik
+   Copyright (c) 1993-2003, Robert M Supnik
 
    Permission is hereby granted, free of charge, to any person obtaining a
    copy of this software and associated documentation files (the "Software"),
@@ -103,7 +103,7 @@ control registers for the interrupt system.
 
 	name		size	comments
 
-	SC		14	sequence counter
+	SC		15	sequence counter
 	AX		16	arithmetic operator input register 1
 	AY		16	arithmetic operator input register 2
 	AO		16	arithmetic operator output register
@@ -126,7 +126,7 @@ control registers for the interrupt system.
 	ION		1	interrupts enabled
 	INODEF		1	interrupts not deferred
 	BKP		1	breakpoint request
-	SCQ[0:63]	16	SC prior to last jump or interrupt;
+	SCQ[0:63]	15	SC prior to last jump or interrupt;
 				most recent SC change first
 	STOP_OPR	1	stop on undefined operator
 	WRU		8	interrupt character
@@ -136,8 +136,8 @@ control registers for the interrupt system.
 2.2.1 S42-004 High Speed Reader (HSR)
 
 The paper tape reader (HSR) reads data from or a disk file.  The POS
-register specifies the number of the next data item to be read.  Thus,
-by changing POS, the user can backspace or advance the reader.
+register specifies the number of the next data item to be read.
+Thus, by changing POS, the user can backspace or advance the reader.
 
 The paper tape reader implements these registers:
 

GRI/gri_stddev.c

@@ -1,6 +1,6 @@
 /* gri_stddev.c: GRI-909 standard devices
 
-   Copyright (c) 2001-2002, Robert M Supnik
+   Copyright (c) 2001-2003, Robert M Supnik
 
    Permission is hereby granted, free of charge, to any person obtaining a
    copy of this software and associated documentation files (the "Software"),
@@ -29,6 +29,7 @@
    hsp		S42-006 high speed punch
    rtc		real time clock
 
+   25-Apr-03	RMS	Revised for extended file support
    22-Dec-02	RMS	Added break support
    01-Nov-02	RMS	Added 7b/8B support to terminal
 */
@@ -73,7 +74,7 @@ REG tti_reg[] = {
 	{ ORDATA (BUF, tti_unit.buf, 8) },
 	{ FLDATA (IRDY, dev_done, INT_V_TTI) },
 	{ FLDATA (IENB, ISR, INT_V_TTI) },
-	{ DRDATA (POS, tti_unit.pos, 32), PV_LEFT },
+	{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
 	{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
 	{ FLDATA (UC, tti_unit.flags, UNIT_V_KSR), REG_HRO },
 	{ NULL }  };
@@ -103,7 +104,7 @@ REG tto_reg[] = {
 	{ ORDATA (BUF, tto_unit.buf, 8) },
 	{ FLDATA (ORDY, dev_done, INT_V_TTO) },
 	{ FLDATA (IENB, ISR, INT_V_TTO) },
-	{ DRDATA (POS, tto_unit.pos, 32), PV_LEFT },
+	{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
 	{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
 	{ NULL }  };
 
@@ -134,7 +135,7 @@ REG hsr_reg[] = {
 	{ ORDATA (BUF, hsr_unit.buf, 8) },
 	{ FLDATA (IRDY, dev_done, INT_V_HSR) },
 	{ FLDATA (IENB, ISR, INT_V_HSR) },
-	{ DRDATA (POS, hsr_unit.pos, 32), PV_LEFT },
+	{ DRDATA (POS, hsr_unit.pos, T_ADDR_W), PV_LEFT },
 	{ DRDATA (TIME, hsr_unit.wait, 24), REG_NZ + PV_LEFT },
 	{ FLDATA (STOP_IOE, hsr_stopioe, 0) },
 	{ NULL }  };
@@ -159,7 +160,7 @@ REG hsp_reg[] = {
 	{ ORDATA (BUF, hsp_unit.buf, 8) },
 	{ FLDATA (ORDY, dev_done, INT_V_HSP) },
 	{ FLDATA (IENB, ISR, INT_V_HSP) },
-	{ DRDATA (POS, hsp_unit.pos, 32), PV_LEFT },
+	{ DRDATA (POS, hsp_unit.pos, T_ADDR_W), PV_LEFT },
 	{ DRDATA (TIME, hsp_unit.wait, 24), PV_LEFT },
 	{ FLDATA (STOP_IOE, hsp_stopioe, 0) },
 	{ NULL }  };
@@ -223,7 +224,7 @@ return 0;
 
 /* Service routines */
 
-t_stat tti_svc (UNIT *uhsr)
+t_stat tti_svc (UNIT *uptr)
 {
 int32 c;
 
@@ -240,7 +241,7 @@ tti_unit.pos = tti_unit.pos + 1;
 return SCPE_OK;
 }
 
-t_stat tto_svc (UNIT *uhsr)
+t_stat tto_svc (UNIT *uptr)
 {
 int32 c;
 t_stat r;
@@ -257,7 +258,7 @@ return SCPE_OK;
 
 /* Reset routines */
 
-t_stat tti_reset (DEVICE *dhsr)
+t_stat tti_reset (DEVICE *dptr)
 {
 tti_unit.buf = 0;					/* clear buffer */
 dev_done = dev_done & ~INT_TTI;				/* clear ready */
@@ -265,7 +266,7 @@ sim_activate (&tti_unit, tti_unit.wait);		/* activate unit */
 return SCPE_OK;
 }
 
-t_stat tto_reset (DEVICE *dhsr)
+t_stat tto_reset (DEVICE *dptr)
 {
 tto_unit.buf = 0;					/* clear buffer */
 dev_done = dev_done | INT_TTO;				/* set ready */
@@ -310,7 +311,7 @@ if (((op & PT_IRDY) && (dev_done & INT_HSR)) ||
 return 0;
 }
 
-t_stat hsr_svc (UNIT *uhsr)
+t_stat hsr_svc (UNIT *uptr)
 {
 int32 temp;
 
@@ -329,7 +330,7 @@ hsr_unit.pos = hsr_unit.pos + 1;
 return SCPE_OK;
 }
 
-t_stat hsp_svc (UNIT *uhsr)
+t_stat hsp_svc (UNIT *uptr)
 {
 dev_done = dev_done | INT_HSP;				/* set ready */
 if ((hsp_unit.flags & UNIT_ATT) == 0)			/* attached? */
@@ -344,7 +345,7 @@ return SCPE_OK;
 
 /* Reset routines */
 
-t_stat hsr_reset (DEVICE *dhsr)
+t_stat hsr_reset (DEVICE *dptr)
 {
 hsr_unit.buf = 0;					/* clear buffer */
 dev_done = dev_done & ~INT_HSR;				/* clear ready */
@@ -352,7 +353,7 @@ sim_cancel (&hsr_unit);					/* deactivate unit */
 return SCPE_OK;
 }
 
-t_stat hsp_reset (DEVICE *dhsr)
+t_stat hsp_reset (DEVICE *dptr)
 {
 hsp_unit.buf = 0;					/* clear buffer */
 dev_done = dev_done | INT_HSP;				/* set ready */
@@ -377,7 +378,7 @@ if ((op & RTC_OV) && (dev_done & INT_RTC)) return 1;
 return 0;
 }
 
-t_stat rtc_svc (UNIT *uhsr)
+t_stat rtc_svc (UNIT *uptr)
 {
 M[RTC_CTR] = (M[RTC_CTR] + 1) & DMASK;			/* incr counter */
 if (M[RTC_CTR] == 0) dev_done = dev_done | INT_RTC;	/* ovflo? set ready */
@@ -385,7 +386,7 @@ sim_activate (&rtc_unit, sim_rtc_calb (rtc_tps));	/* reactivate */
 return SCPE_OK;
 }
 
-t_stat rtc_reset (DEVICE *dhsr)
+t_stat rtc_reset (DEVICE *dptr)
 {
 dev_done = dev_done & ~INT_RTC;				/* clear ready */
 sim_cancel (&rtc_unit);					/* stop clock */

GRI/gri_sys.c

@@ -1,6 +1,6 @@
 /* gri_sys.c: GRI-909 simulator interface
 
-   Copyright (c) 2001-2002, Robert M Supnik
+   Copyright (c) 2001-2003, Robert M Supnik
 
    Permission is hereby granted, free of charge, to any person obtaining a
    copy of this software and associated documentation files (the "Software"),
@@ -80,7 +80,8 @@ const char *sim_stop_messages[] = {
 
 t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
 {
-int32 c, org;
+int32 c;
+uint32 org;
 t_stat r;
 char gbuf[CBUFSIZE];
 
@@ -114,7 +115,7 @@ return SCPE_OK;
 
 /* Symbol tables */
 
-#define F_V_FL	16
+#define F_V_FL	16					/* class flag */
 #define F_M_FL	017
 #define F_V_FO	000					/* function out */
 #define F_V_FOI	001					/* FO, impl reg */