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Notes For V3.0-0
Because some key files have changed, V3.0 should be unzipped to a clean directory. 1. New Features in 3.0-0 1.1 SCP and Libraries - Added ASSIGN/DEASSIGN (logical name) commands. - Changed RESTORE to unconditionally detach files. - Added E11 and TPC format support to magtape library. - Fixed bug in SHOW CONNECTIONS. - Added USE_ADDR64 support 1.2 All magtapes - Magtapes support SIMH format, E11 format, and TPC format (read only). - SET <tape_unit> FORMAT=format sets the specified tape unit's format. - SHOW <tape_unit> FORMAT displays the specified tape unit's format. - Tape format can also be set as part of the ATTACH command, using the -F switch. 1.3 VAX - VAX can be compiled without USE_INT64. - If compiled with USE_INT64 and USE_ADDR64, RQ and TQ controllers support files > 2GB. - VAX ROM has speed control (SET ROM DELAY/NODELAY). 2. Bugs Fixed in 3.01-0 2.1 VAX - Fixed CVTfi bug: integer overflow not set if exponent out of range - Fixed EMODx bugs: o First and second operands reversed o Separated fraction received wrong exponent o Overflow calculation on separated integer incorrect o Fraction not set to zero if exponent out of range - Fixed interval timer and ROM access to pass power-up self-test even on very fast host processors (fixes from Mark Pizzolato). 2.2 1401 - Fixed mnemonic, instruction lengths, and reverse scan length check bug for MCS. - Fixed MCE bug, BS off by 1 if zero suppress. - Fixed chaining bug, D lost if return to SCP. - Fixed H branch, branch occurs after continue. - Added check for invalid 8 character MCW, LCA. - Fixed magtape load-mode end of record response. 2.3 Nova - Fixed DSK variable size interaction with restore. 2.4 PDP-1 - Fixed DT variable size interaction with restore. 2.5 PDP-11 - Fixed DT variable size interaction with restore. - Fixed bug in MMR1 update (found by Tim Stark). - Added XQ features and fixed bugs: o Corrected XQ interrupts on IE state transition (code by Tom Evans). o Added XQ interrupt clear on soft reset. o Removed XQ interrupt when setting XL or RL (multiple people). o Added SET/SHOW XQ STATS. o Added SHOW XQ FILTERS. o Added ability to split received packet into multiple buffers. o Added explicit runt and giant packet processing. 2.6 PDP-18B - Fixed DT, RF variable size interaction with restore. - Fixed MT bug in MTTR. 2.7 PDP-8 - Fixed DT, DF, RF, RX variable size interaction with restore. - Fixed MT bug in SKTR. 2.8 HP2100 - Fixed bug in DP (13210A controller only), DQ read status. - Fixed bug in DP, DQ seek complete. 2.9 GRI - Fixed bug in SC queue pointer management. 3. New Features in 3.0 vs prior releases N/A 4. Bugs Fixed in 3.0 vs prior releases N/A 5. General Notes WARNING: The RESTORE command has changed. RESTORE will now detach an attached file on a unit, if that unit did not have an attached file in the saved configuration. This is required to assure that the unit flags and the file state are consistent. WARNING: The compilation scheme for the PDP-10, PDP-11, and VAX has changed. Use one of the supplied build files, or read the documentation carefully, before compiling any of these simulators.
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
43385c9616
commit
4ffd3be790
@@ -1,6 +1,6 @@
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/* h316_cpu.c: Honeywell 316/516 CPU simulator
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Copyright (c) 1999-2002, Robert M. Supnik
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Copyright (c) 1999-2003, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -195,7 +195,7 @@
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#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = PC
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#define PCQ_TOP pcq[pcq_p]
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#define UNIT_V_MSIZE (UNIT_V_UF) /* dummy mask */
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#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
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#define UNIT_MSIZE (1u << UNIT_V_MSIZE)
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#define m7 0001000 /* for generics */
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#define m8 0000400
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#define m9 0000200
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@@ -229,17 +229,20 @@ int32 pcq_p = 0; /* PC queue ptr */
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REG *pcq_r = NULL; /* PC queue reg ptr */
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int32 dlog = 0; /* debug log */
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int32 turnoff = 0;
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extern int32 sim_int_char;
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extern int32 sim_interval;
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extern int32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
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extern FILE *sim_log;
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extern t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
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UNIT *uptr, int32 sw);
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t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_reset (DEVICE *dptr);
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t_stat cpu_set_noext (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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extern t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
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UNIT *uptr, int32 sw);
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/* CPU data structures
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@@ -276,7 +279,7 @@ REG cpu_reg[] = {
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{ FLDATA (STOP_INST, stop_inst, 0) },
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{ FLDATA (STOP_DEV, stop_dev, 1) },
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{ DRDATA (INDMAX, ind_max, 8), REG_NZ + PV_LEFT },
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{ BRDATA (PCQ, pcq, 8, 15, PCQ_SIZE), REG_RO+REG_CIRC },
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{ BRDATA (PCQ, pcq, 8, 15, PCQ_SIZE), REG_RO + REG_CIRC },
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{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
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{ ORDATA (WRU, sim_int_char, 8) },
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{ FLDATA (DLOG, dlog, 0), REG_HIDDEN },
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@@ -323,10 +326,9 @@ int32 (*iotab[64])() = {
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t_stat sim_instr (void)
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{
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extern int32 sim_interval;
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extern UNIT clk_unit;
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int32 AR, BR, MB, Y, t1, t2, t3, skip;
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unsigned int32 ut;
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uint32 ut;
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t_stat reason;
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t_stat Ea (int32 inst, int32 *addr);
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void Write (int32 val, int32 addr);
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@@ -377,6 +379,7 @@ else { if (sim_brk_summ &&
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MB = Read (Y); /* fetch instr */
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PC = NEWA (Y, Y + 1); /* incr PC */
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dev_ready = dev_ready | INT_NODEF; }
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sim_interval = sim_interval - 1;
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if (dlog && sim_log && !turnoff) { /* cycle log? */
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int32 op = I_GETOP (MB) & 017; /* core opcode */
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@@ -389,6 +392,7 @@ if (dlog && sim_log && !turnoff) { /* cycle log? */
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/* Memory reference instructions */
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switch (I_GETOP (MB)) { /* case on <1:6> */
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case 001: case 021: case 041: case 061: /* JMP */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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PCQ_ENTRY; /* save PC */
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@@ -401,6 +405,7 @@ case 001: case 021: case 041: case 061: /* JMP */
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else turnoff = 0; } /* no, log */
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if (extoff_pending) ext = extoff_pending = 0; /* cond ext off */
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break;
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case 002: case 022: case 042: case 062: /* LDA */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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if (dp) { /* double prec? */
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@@ -409,10 +414,12 @@ case 002: case 022: case 042: case 062: /* LDA */
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sc = 0; }
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else AR = Read (Y); /* no, get word */
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break;
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case 003: case 023: case 043: case 063: /* ANA */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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AR = AR & Read (Y);
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break;
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case 004: case 024: case 044: case 064: /* STA */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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if (dp) { /* double prec? */
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@@ -421,10 +428,12 @@ case 004: case 024: case 044: case 064: /* STA */
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sc = 0; }
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else Write (AR, Y); /* no, store word */
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break;
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case 005: case 025: case 045: case 065: /* ERA */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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AR = AR ^ Read (Y);
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break;
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case 006: case 026: case 046: case 066: /* ADD */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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if (dp) { /* double prec? */
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@@ -435,6 +444,7 @@ case 006: case 026: case 046: case 066: /* ADD */
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sc = 0; }
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else AR = Add16 (AR, Read (Y)); /* no, 16b add */
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break;
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case 007: case 027: case 047: case 067: /* SUB */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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if (dp) { /* double prec? */
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@@ -455,32 +465,38 @@ case 010: case 030: case 050: case 070: /* JST */
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PCQ_ENTRY;
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PC = NEWA (PC, Y + 1); /* set new PC */
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break;
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case 011: case 031: case 051: case 071: /* CAS */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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MB = Read (Y);
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if (AR == MB) PC = NEWA (PC, PC + 1);
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else if (SEXT (AR) < SEXT (MB)) PC = NEWA (PC, PC + 2);
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break;
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case 012: case 032: case 052: case 072: /* IRS */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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MB = (Read (Y) + 1) & DMASK; /* incr, rewrite */
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Write (MB, Y);
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if (MB == 0) PC = NEWA (PC, PC + 1); /* skip if zero */
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break;
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case 013: case 033: case 053: case 073: /* IMA */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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MB = Read (Y);
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Write (AR, Y); /* A to mem */
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AR = MB; /* mem to A */
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break;
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case 015: case 055: /* STX */
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if (reason = Ea (MB & ~IDX, &Y)) break; /* eff addr */
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Write (XR, Y); /* store XR */
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break;
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case 035: case 075: /* LDX */
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if (reason = Ea (MB & ~IDX, &Y)) break; /* eff addr */
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XR = Read (Y); /* load XR */
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break;
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case 016: case 036: case 056: case 076: /* MPY */
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if (cpu_unit.flags & UNIT_HSA) { /* installed? */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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@@ -489,6 +505,7 @@ case 016: case 036: case 056: case 076: /* MPY */
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sc = 0; }
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else reason = stop_inst;
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break;
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case 017: case 037: case 057: case 077: /* DIV */
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if (cpu_unit.flags & UNIT_HSA) { /* installed? */
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if (reason = Ea (MB, &Y)) break; /* eff addr */
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@@ -512,6 +529,7 @@ case 014: /* OCP */
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reason = t2 >> IOT_V_REASON;
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turnoff = 0;
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break;
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case 034: /* SKS */
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t2 = iotab[MB & DEVMASK] (ioSKS, I_GETFNC (MB), AR);
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reason = t2 >> IOT_V_REASON;
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@@ -519,6 +537,7 @@ case 034: /* SKS */
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PC = NEWA (PC, PC + 1);
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turnoff = 0; }
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break;
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case 054: /* INA */
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if (MB & INCLRA) AR = 0;
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t2 = iotab[MB & DEVMASK] (ioINA, I_GETFNC (MB), AR);
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@@ -528,6 +547,7 @@ case 054: /* INA */
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turnoff = 0; }
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AR = t2 & DMASK; /* data */
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break;
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case 074: /* OTA */
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t2 = iotab[MB & DEVMASK] (ioOTA, I_GETFNC (MB), AR);
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reason = t2 >> IOT_V_REASON;
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@@ -606,6 +626,7 @@ case 020:
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sc = 0; /* clear sc */
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if ((t1 = (-MB) & SHFMASK) == 0) break; /* shift count */
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switch (I_GETFNC (MB)) { /* case shift fnc */
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case 000: /* LRL */
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if (t1 > 32) ut = 0; /* >32? all 0 */
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else {
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@@ -614,6 +635,7 @@ case 020:
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ut = ut >> t1; } /* log right */
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PUTDBL_U (ut); /* store A,B */
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break;
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case 001: /* LRS */
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if (t1 > 31) t1 = 31; /* limit to 31 */
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t2 = GETDBL_S (SEXT (AR), BR); /* get A'B signed */
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@@ -621,6 +643,7 @@ case 020:
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t2 = t2 >> t1; /* arith right */
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PUTDBL_S (t2); /* store A,B */
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break;
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case 002: /* LRR */
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t2 = t1 % 32; /* mod 32 */
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ut = GETDBL_U (AR, BR); /* get A'B */
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@@ -628,6 +651,7 @@ case 020:
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C = (ut >> 31) & 1; /* C = A<1> */
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PUTDBL_U (ut); /* store A,B */
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break;
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case 003: /* "long right arot" */
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if (reason = stop_inst) break; /* stop on undef? */
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for (t2 = 0; t2 < t1; t2++) { /* bit by bit */
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@@ -636,22 +660,26 @@ case 020:
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((BR & MMASK) >> 1);
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AR = ((AR & SIGN) | (C << 15)) | (AR >> 1); }
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break;
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case 004: /* LGR */
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if (t1 > 16) AR = 0; /* > 16? all 0 */
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else {
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C = (AR >> (t1 - 1)) & 1; /* C = last out */
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AR = (AR >> t1) & DMASK; } /* log right */
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break;
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case 005: /* ARS */
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if (t1 > 16) t1 = 16; /* limit to 16 */
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C = ((SEXT (AR)) >> (t1 - 1)) & 1; /* C = last out */
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AR = ((SEXT (AR)) >> t1) & DMASK; /* arith right */
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break;
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case 006: /* ARR */
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t2 = t1 % 16; /* mod 16 */
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AR = ((AR >> t2) | (AR << (16 - t2))) & DMASK;
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C = (AR >> 15) & 1; /* C = A<1> */
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break;
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case 007: /* "short right arot" */
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if (reason = stop_inst) break; /* stop on undef? */
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for (t2 = 0; t2 < t1; t2++) { /* bit by bit */
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@@ -669,6 +697,7 @@ case 020:
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ut = ut << t1; } /* log left */
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PUTDBL_U (ut); /* store A,B */
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break;
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case 011: /* LLS */
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if (t1 > 31) t1 = 31; /* limit to 31 */
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t2 = GETDBL_S (SEXT (AR), BR); /* get A'B */
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@@ -677,6 +706,7 @@ case 020:
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if ((t2 >> (31 - t1)) != /* shf out = sgn? */
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((AR & SIGN)? -1: 0)) C = 1;
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break;
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case 012: /* LLR */
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t2 = t1 % 32; /* mod 32 */
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ut = GETDBL_U (AR, BR); /* get A'B */
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@@ -684,6 +714,7 @@ case 020:
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C = ut & 1; /* C = B<16> */
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PUTDBL_U (ut); /* store A,B */
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break;
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case 013: /* "long left arot" */
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if (reason = stop_inst) break; /* stop on undef? */
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for (t2 = 0; t2 < t1; t2++) { /* bit by bit */
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@@ -693,12 +724,14 @@ case 020:
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if ((AR & SIGN) != ((AR >> 1) & SIGN)) C = 1;
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AR = AR & DMASK; }
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break;
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case 014: /* LGL */
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if (t1 > 16) AR = 0; /* > 16? all 0 */
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else {
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C = (AR >> (16 - t1)) & 1; /* C = last out */
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AR = (AR << t1) & DMASK; } /* log left */
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break;
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case 015: /* ALS */
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if (t1 > 16) t1 = 16; /* limit to 16 */
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t2 = SEXT (AR); /* save AR */
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@@ -706,11 +739,13 @@ case 020:
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if ((t2 >> (16 - t1)) != /* shf out + sgn */
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((AR & SIGN)? -1: 0)) C = 1;
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break;
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case 016: /* ALR */
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t2 = t1 % 16; /* mod 16 */
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AR = ((AR << t2) | (AR >> (16 - t2))) & DMASK;
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C = AR & 1; /* C = A<16> */
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break;
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case 017: /* "short left arot" */
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if (reason = stop_inst) break; /* stop on undef? */
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for (t2 = 0; t2 < t1; t2++) { /* bit by bit */
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@@ -826,6 +861,7 @@ return;
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int32 Add16 (int32 v1, int32 v2)
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{
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int32 r = v1 + v2;
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C = 0;
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if (((v1 ^ ~v2) & (v1 ^ r)) & SIGN) C = 1;
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return (r & DMASK);
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@@ -834,6 +870,7 @@ return (r & DMASK);
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int32 Add31 (int32 v1, int32 v2)
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{
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int32 r = v1 + v2;
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C = 0;
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if (((v1 ^ ~v2) & (v1 ^ r)) & (1u << 30)) C = 1;
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return r;
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@@ -1037,7 +1074,7 @@ return SCPE_OK;
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t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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int32 mc = 0;
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t_addr i;
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uint32 i;
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if ((val <= 0) || (val > MAXMEMSIZE) || ((val & 07777) != 0) ||
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(((cpu_unit.flags & UNIT_EXT) == 0) && (val > (NX_AMASK + 1))))
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@@ -1,6 +1,6 @@
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/* h316_defs.h: Honeywell 316/516 simulator definitions
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Copyright (c) 1999-2002, Robert M. Supnik
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Copyright (c) 1999-2003, Robert M. Supnik
|
||||
|
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Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -22,6 +22,8 @@
|
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
|
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in this Software without prior written authorization from Robert M Supnik.
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25-Apr-03 RMS Revised for extended file support
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*/
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#include "sim_defs.h" /* simulator defns */
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@@ -40,7 +42,7 @@
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#define MEMSIZE (cpu_unit.capac) /* actual memory size */
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#define X_AMASK (MAXMEMSIZE - 1) /* ext address mask */
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#define NX_AMASK ((MAXMEMSIZE / 2) - 1) /* nx address mask */
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#define MEM_ADDR_OK(x) (((t_addr) (x)) < MEMSIZE)
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#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
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/* Architectural constants */
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@@ -56,8 +58,8 @@
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#define UNIT_V_EXT (UNIT_V_UF + 1) /* extended mem */
|
||||
#define UNIT_V_HSA (UNIT_V_UF + 2) /* high speed arith */
|
||||
#define UNIT_EXT (1 << UNIT_V_EXT)
|
||||
#define UNIT_HSA (1 << UNIT_V_HSA)
|
||||
#define UNIT_EXT (1u << UNIT_V_EXT)
|
||||
#define UNIT_HSA (1u << UNIT_V_HSA)
|
||||
|
||||
/* Instruction format */
|
||||
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
To: Users
|
||||
From: Bob Supnik
|
||||
Subj: H316 Simulator Usage
|
||||
Date: 15-Mar-2003
|
||||
Date: 20-Apr-2003
|
||||
|
||||
COPYRIGHT NOTICE
|
||||
|
||||
@@ -152,7 +152,7 @@ Error handling is as follows:
|
||||
0 out of tape
|
||||
|
||||
end of file 1 report error and stop
|
||||
0 out of tape or paper
|
||||
0 out of tape or paper
|
||||
|
||||
OS I/O error x report error and stop
|
||||
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* h316_lp.c: Honeywell 316/516 line printer
|
||||
|
||||
Copyright (c) 1999-2002, Robert M. Supnik
|
||||
Copyright (c) 1999-2003, Robert M. Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -25,34 +25,10 @@
|
||||
|
||||
lpt line printer
|
||||
|
||||
25-Apr-03 RMS Revised for extended file support
|
||||
30-May-02 RMS Widened POS to 32b
|
||||
*/
|
||||
|
||||
#include "h316_defs.h"
|
||||
#define LPT_WIDTH 120 /* width */
|
||||
#define LPT_SCAN (LPT_WIDTH / 2) /* words/scan */
|
||||
#define LPT_DRUM 64 /* drum rows */
|
||||
#define LPT_SVCSH 01 /* shuttle */
|
||||
#define LPT_SVCPA 02 /* paper advance */
|
||||
|
||||
extern int32 dev_ready, dev_enable;
|
||||
extern int32 stop_inst;
|
||||
int32 lpt_wdpos = 0; /* word position */
|
||||
int32 lpt_drpos = 0; /* drum position */
|
||||
int32 lpt_crpos = 0; /* carriage position */
|
||||
int32 lpt_svcst = 0; /* service state */
|
||||
int32 lpt_svcch = 0; /* service channel */
|
||||
int32 lpt_xfer = 0; /* transfer flag */
|
||||
int32 lpt_prdn = 1; /* printing done */
|
||||
char lpt_buf[LPT_WIDTH + 1] = { 0 }; /* line buffer */
|
||||
int32 lpt_xtime = 5; /* transfer time */
|
||||
int32 lpt_etime = 50; /* end of scan time */
|
||||
int32 lpt_ptime = 5000; /* paper adv time */
|
||||
int32 lpt_stopioe = 0; /* stop on error */
|
||||
t_stat lpt_svc (UNIT *uptr);
|
||||
t_stat lpt_reset (DEVICE *dptr);
|
||||
|
||||
/* The Series 16 line printer is an unbuffered Analex shuttle printer.
|
||||
The Series 16 line printer is an unbuffered Analex shuttle printer.
|
||||
Because it was unbuffered, the CPU had to scan out an entire line's
|
||||
worth of characters (60 words) for every character on the print drum
|
||||
(64 characters). Because it was a shuttle printer, the entire
|
||||
@@ -81,8 +57,36 @@ t_stat lpt_reset (DEVICE *dptr);
|
||||
lpt_svcch channel for paper advance (0 = no adv)
|
||||
lpt_xfer transfer ready flag
|
||||
lpt_prdn printing done flag
|
||||
*/
|
||||
|
||||
LPT data structures
|
||||
#include "h316_defs.h"
|
||||
|
||||
#define LPT_WIDTH 120 /* width */
|
||||
#define LPT_SCAN (LPT_WIDTH / 2) /* words/scan */
|
||||
#define LPT_DRUM 64 /* drum rows */
|
||||
#define LPT_SVCSH 01 /* shuttle */
|
||||
#define LPT_SVCPA 02 /* paper advance */
|
||||
|
||||
extern int32 dev_ready, dev_enable;
|
||||
extern int32 stop_inst;
|
||||
|
||||
int32 lpt_wdpos = 0; /* word position */
|
||||
int32 lpt_drpos = 0; /* drum position */
|
||||
int32 lpt_crpos = 0; /* carriage position */
|
||||
int32 lpt_svcst = 0; /* service state */
|
||||
int32 lpt_svcch = 0; /* service channel */
|
||||
int32 lpt_xfer = 0; /* transfer flag */
|
||||
int32 lpt_prdn = 1; /* printing done */
|
||||
char lpt_buf[LPT_WIDTH + 1] = { 0 }; /* line buffer */
|
||||
int32 lpt_xtime = 5; /* transfer time */
|
||||
int32 lpt_etime = 50; /* end of scan time */
|
||||
int32 lpt_ptime = 5000; /* paper adv time */
|
||||
int32 lpt_stopioe = 0; /* stop on error */
|
||||
|
||||
t_stat lpt_svc (UNIT *uptr);
|
||||
t_stat lpt_reset (DEVICE *dptr);
|
||||
|
||||
/* LPT data structures
|
||||
|
||||
lpt_dev LPT device descriptor
|
||||
lpt_unit LPT unit descriptor
|
||||
@@ -103,7 +107,7 @@ REG lpt_reg[] = {
|
||||
{ ORDATA (SVCST, lpt_svcst, 2) },
|
||||
{ ORDATA (SVCCH, lpt_svcch, 2) },
|
||||
{ BRDATA (BUF, lpt_buf, 8, 8, 120) },
|
||||
{ DRDATA (POS, lpt_unit.pos, 32), PV_LEFT },
|
||||
{ DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
|
||||
{ DRDATA (XTIME, lpt_xtime, 24), PV_LEFT },
|
||||
{ DRDATA (ETIME, lpt_etime, 24), PV_LEFT },
|
||||
{ DRDATA (PTIME, lpt_ptime, 24), PV_LEFT },
|
||||
@@ -115,7 +119,6 @@ DEVICE lpt_dev = {
|
||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &lpt_reset,
|
||||
NULL, NULL, NULL };
|
||||
|
||||
|
||||
/* IO routine */
|
||||
|
||||
@@ -127,7 +130,7 @@ switch (inst) { /* case on opcode */
|
||||
case ioOCP: /* OCP */
|
||||
switch (fnc) { /* case on fnc */
|
||||
case 000: case 002: case 004: /* paper adv */
|
||||
lpt_svcst = lpt_svcst | LPT_SVCPA; /* set state */
|
||||
lpt_svcst = lpt_svcst | LPT_SVCPA; /* set state */
|
||||
lpt_svcch = fnc >> 1; /* save channel */
|
||||
sim_activate (&lpt_unit, lpt_ptime);
|
||||
CLR_READY (INT_LPT); /* clear int */
|
||||
@@ -141,6 +144,7 @@ case ioOCP: /* OCP */
|
||||
default:
|
||||
return IOBADFNC (dat); }
|
||||
break;
|
||||
|
||||
case ioSKS: /* SKS */
|
||||
switch (fnc) { /* case on fnc */
|
||||
case 000: /* if xfer rdy */
|
||||
@@ -180,6 +184,7 @@ case ioSKS: /* SKS */
|
||||
default:
|
||||
return IOBADFNC (dat); }
|
||||
break;
|
||||
|
||||
case ioOTA: /* OTA */
|
||||
if (fnc) return IOBADFNC (dat); /* only fnc 0 */
|
||||
if (lpt_xfer) { /* xfer ready? */
|
||||
|
||||
@@ -28,6 +28,7 @@
|
||||
tty 316/516-33 teleprinter
|
||||
clk/options 316/516-12 real time clocks/internal options
|
||||
|
||||
25-Apr-03 RMS Revised for extended file support
|
||||
01-Mar-03 RMS Added SET/SHOW CLK FREQ support
|
||||
22-Dec-02 RMS Added break support
|
||||
01-Nov-02 RMS Added 7b/8b support to terminal
|
||||
@@ -87,7 +88,7 @@ REG ptr_reg[] = {
|
||||
{ ORDATA (BUF, ptr_unit.buf, 8) },
|
||||
{ FLDATA (READY, dev_ready, INT_V_PTR) },
|
||||
{ FLDATA (ENABLE, dev_enable, INT_V_PTR) },
|
||||
{ DRDATA (POS, ptr_unit.pos, 32), PV_LEFT },
|
||||
{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },
|
||||
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
|
||||
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
|
||||
{ NULL } };
|
||||
@@ -114,7 +115,7 @@ REG ptp_reg[] = {
|
||||
{ FLDATA (READY, dev_ready, INT_V_PTP) },
|
||||
{ FLDATA (ENABLE, dev_enable, INT_V_PTP) },
|
||||
{ FLDATA (POWER, ptp_power, 0) },
|
||||
{ DRDATA (POS, ptp_unit.pos, 32), PV_LEFT },
|
||||
{ DRDATA (POS, ptp_unit.pos, T_ADDR_W), PV_LEFT },
|
||||
{ DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT },
|
||||
{ DRDATA (PWRTIME, ptp_ptime, 24), PV_LEFT },
|
||||
{ FLDATA (STOP_IOE, ptp_stopioe, 0) },
|
||||
@@ -147,9 +148,9 @@ REG tty_reg[] = {
|
||||
{ FLDATA (MODE, tty_mode, 0) },
|
||||
{ FLDATA (READY, dev_ready, INT_V_TTY) },
|
||||
{ FLDATA (ENABLE, dev_enable, INT_V_TTY) },
|
||||
{ DRDATA (KPOS, tty_unit[TTI].pos, 32), PV_LEFT },
|
||||
{ DRDATA (KPOS, tty_unit[TTI].pos, T_ADDR_W), PV_LEFT },
|
||||
{ DRDATA (KTIME, tty_unit[TTI].wait, 24), REG_NZ + PV_LEFT },
|
||||
{ DRDATA (TPOS, tty_unit[TTO].pos, 32), PV_LEFT },
|
||||
{ DRDATA (TPOS, tty_unit[TTO].pos, T_ADDR_W), PV_LEFT },
|
||||
{ DRDATA (TTIME, tty_unit[TTO].wait, 24), REG_NZ + PV_LEFT },
|
||||
{ NULL } };
|
||||
|
||||
@@ -164,7 +165,7 @@ DEVICE tty_dev = {
|
||||
2, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &tty_reset,
|
||||
NULL, NULL, NULL };
|
||||
|
||||
|
||||
/* CLK data structures
|
||||
|
||||
clk_dev CLK device descriptor
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* h316_sys.c: Honeywell 316/516 simulator interface
|
||||
|
||||
Copyright (c) 1999-2002, Robert M Supnik
|
||||
Copyright (c) 1999-2003, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
|
||||
Reference in New Issue
Block a user