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Notes For V3.0-0
Because some key files have changed, V3.0 should be unzipped to a clean directory. 1. New Features in 3.0-0 1.1 SCP and Libraries - Added ASSIGN/DEASSIGN (logical name) commands. - Changed RESTORE to unconditionally detach files. - Added E11 and TPC format support to magtape library. - Fixed bug in SHOW CONNECTIONS. - Added USE_ADDR64 support 1.2 All magtapes - Magtapes support SIMH format, E11 format, and TPC format (read only). - SET <tape_unit> FORMAT=format sets the specified tape unit's format. - SHOW <tape_unit> FORMAT displays the specified tape unit's format. - Tape format can also be set as part of the ATTACH command, using the -F switch. 1.3 VAX - VAX can be compiled without USE_INT64. - If compiled with USE_INT64 and USE_ADDR64, RQ and TQ controllers support files > 2GB. - VAX ROM has speed control (SET ROM DELAY/NODELAY). 2. Bugs Fixed in 3.01-0 2.1 VAX - Fixed CVTfi bug: integer overflow not set if exponent out of range - Fixed EMODx bugs: o First and second operands reversed o Separated fraction received wrong exponent o Overflow calculation on separated integer incorrect o Fraction not set to zero if exponent out of range - Fixed interval timer and ROM access to pass power-up self-test even on very fast host processors (fixes from Mark Pizzolato). 2.2 1401 - Fixed mnemonic, instruction lengths, and reverse scan length check bug for MCS. - Fixed MCE bug, BS off by 1 if zero suppress. - Fixed chaining bug, D lost if return to SCP. - Fixed H branch, branch occurs after continue. - Added check for invalid 8 character MCW, LCA. - Fixed magtape load-mode end of record response. 2.3 Nova - Fixed DSK variable size interaction with restore. 2.4 PDP-1 - Fixed DT variable size interaction with restore. 2.5 PDP-11 - Fixed DT variable size interaction with restore. - Fixed bug in MMR1 update (found by Tim Stark). - Added XQ features and fixed bugs: o Corrected XQ interrupts on IE state transition (code by Tom Evans). o Added XQ interrupt clear on soft reset. o Removed XQ interrupt when setting XL or RL (multiple people). o Added SET/SHOW XQ STATS. o Added SHOW XQ FILTERS. o Added ability to split received packet into multiple buffers. o Added explicit runt and giant packet processing. 2.6 PDP-18B - Fixed DT, RF variable size interaction with restore. - Fixed MT bug in MTTR. 2.7 PDP-8 - Fixed DT, DF, RF, RX variable size interaction with restore. - Fixed MT bug in SKTR. 2.8 HP2100 - Fixed bug in DP (13210A controller only), DQ read status. - Fixed bug in DP, DQ seek complete. 2.9 GRI - Fixed bug in SC queue pointer management. 3. New Features in 3.0 vs prior releases N/A 4. Bugs Fixed in 3.0 vs prior releases N/A 5. General Notes WARNING: The RESTORE command has changed. RESTORE will now detach an attached file on a unit, if that unit did not have an attached file in the saved configuration. This is required to assure that the unit flags and the file state are consistent. WARNING: The compilation scheme for the PDP-10, PDP-11, and VAX has changed. Use one of the supplied build files, or read the documentation carefully, before compiling any of these simulators.
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
43385c9616
commit
4ffd3be790
150
VAX/vax_sysdev.c
150
VAX/vax_sysdev.c
@@ -1,6 +1,6 @@
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/* vax_sysreg.c: VAX system registers simulator
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Copyright (c) 1998-2002, Robert M Supnik
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Copyright (c) 1998-2003, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -33,6 +33,10 @@
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cso console storage output
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sysd system devices (SSC miscellany)
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7-Jun-03 MP Added calibrated delay to ROM reads (from Mark Pizzolato)
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Fixed calibration problems interval timer (from Mark Pizzolato)
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12-May-03 RMS Fixed compilation warnings from VC.Net
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23-Apr-03 RMS Revised for 32b/64b t_addr
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19-Aug-02 RMS Removed unused variables (found by David Hittner)
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Allowed NVR to be attached to file
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30-May-02 RMS Widened POS to 32b
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@@ -41,6 +45,9 @@
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#include "vax_defs.h"
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#define UNIT_V_NODELAY (UNIT_V_UF + 0) /* ROM access equal to RAM access */
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#define UNIT_NODELAY (1u << UNIT_V_NODELAY)
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/* Console storage control/status */
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#define CSICSR_IMP (CSR_DONE + CSR_IE) /* console input */
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@@ -156,6 +163,7 @@
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extern int32 int_req[IPL_HLVL];
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extern UNIT cpu_unit;
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extern UNIT clk_unit;
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extern jmp_buf save_env;
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extern int32 p1;
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extern int32 sim_switches;
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@@ -182,12 +190,13 @@ uint32 tmr_sav[2] = { 0 }; /* saved inst cnt */
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int32 ssc_adsm[2] = { 0 }; /* addr strobes */
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int32 ssc_adsk[2] = { 0 };
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int32 cdg_dat[CDASIZE >> 2]; /* cache data */
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static uint32 rom_delay = 0;
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t_stat rom_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat rom_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
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t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
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t_stat rom_reset (DEVICE *dptr);
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t_stat nvr_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat nvr_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
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t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
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t_stat nvr_reset (DEVICE *dptr);
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t_stat nvr_attach (UNIT *uptr, char *cptr);
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t_stat nvr_detach (UNIT *uptr);
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@@ -241,6 +250,7 @@ extern void rxcs_wr (int32 dat);
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extern void txcs_wr (int32 dat);
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extern void txdb_wr (int32 dat);
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extern void ioreset_wr (int32 dat);
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extern uint32 sim_os_msec();
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/* ROM data structures
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@@ -254,8 +264,13 @@ UNIT rom_unit = { UDATA (NULL, UNIT_FIX+UNIT_BINK, ROMSIZE) };
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REG rom_reg[] = {
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{ NULL } };
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MTAB rom_mod[] = {
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{ UNIT_NODELAY, UNIT_NODELAY, "fast access", "NODELAY", NULL },
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{ UNIT_NODELAY, 0, "1usec calibrated access", "DELAY", NULL },
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{ 0 } };
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DEVICE rom_dev = {
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"ROM", &rom_unit, rom_reg, NULL,
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"ROM", &rom_unit, rom_reg, rom_mod,
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1, 16, ROMAWIDTH, 4, 16, 32,
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&rom_ex, &rom_dep, &rom_reset,
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NULL, NULL, NULL,
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@@ -395,13 +410,70 @@ DEVICE sysd_dev = {
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/* ROM: read only memory - stored in a buffered file
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Register space access routines see ROM twice
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ROM access has been 'regulated' to about 1Mhz to avoid issues
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with testing the interval timers in self-test. Specifically,
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the VAX boot ROM (ka655.bin) contains code which presumes that
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the VAX runs at a particular slower speed when code is running
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from ROM (which is not cached). These assumptions are built
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into instruction based timing loops. As the host platform gets
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much faster than the original VAX, the assumptions embedded in
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these code loops are no longer valid.
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Code has been added to the ROM implementation to limit CPU speed
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to about 500K instructions per second. This heads off any future
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issues with the embedded timing loops.
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*/
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int32 rom_swapb(int32 val)
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{
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return ((val << 24) & 0xff000000) | (( val << 8) & 0xff0000) |
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((val >> 8) & 0xff00) | ((val >> 24) & 0xff);
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}
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int32 rom_read_delay (int32 val)
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{
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uint32 i, l = rom_delay;
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int32 loopval = 0;
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if (rom_unit.flags & UNIT_NODELAY) return val;
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/* Calibrate the loop delay factor when first used.
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Do this 4 times to and use the largest value computed. */
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if (rom_delay == 0) {
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uint32 ts, te, c = 10000, samples = 0;
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while (1) {
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c = c * 2;
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te = sim_os_msec();
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while (te == (ts = sim_os_msec ())); /* align on ms tick */
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/* This is merely a busy wait with some "work" that won't get optimized
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away by a good compiler. loopval always is zero. To avoid smart compilers,
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the loopval variable is referenced in the function arguments so that the
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function expression is not loop invariant. It also must be referenced
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by subsequent code or to avoid the whole computation being eliminated. */
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for (i = 0; i < c; i++)
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loopval |= (loopval + ts) ^ rom_swapb (rom_swapb (loopval + ts));
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te = sim_os_msec ();
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if ((te - ts) < 50) continue; /* sample big enough? */
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if (rom_delay < (loopval + (c / (te - ts) / 1000) + 1))
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rom_delay = loopval + (c / (te - ts) / 1000) + 1;
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if (++samples >= 4) break;
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c = c / 2; }
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if (rom_delay < 5) rom_delay = 5; }
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for (i = 0; i < l; i++)
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loopval |= (loopval + val) ^ rom_swapb (rom_swapb (loopval + val));
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return val + loopval;
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}
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int32 rom_rd (int32 pa)
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{
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int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2;
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return rom[rg];
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return rom_read_delay (rom[rg]);
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}
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void rom_wr (int32 pa, int32 val, int32 lnt)
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@@ -418,8 +490,10 @@ return;
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/* ROM examine */
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t_stat rom_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
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t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if ((vptr == NULL) || (addr & 03)) return SCPE_ARG;
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if (addr >= ROMSIZE) return SCPE_NXM;
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*vptr = rom[addr >> 2];
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@@ -428,8 +502,10 @@ return SCPE_OK;
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/* ROM deposit */
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t_stat rom_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
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t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if (addr & 03) return SCPE_ARG;
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if (addr >= ROMSIZE) return SCPE_NXM;
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rom[addr >> 2] = (uint32) val;
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@@ -468,8 +544,10 @@ return;
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/* NVR examine */
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t_stat nvr_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
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t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if ((vptr == NULL) || (addr & 03)) return SCPE_ARG;
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if (addr >= NVRSIZE) return SCPE_NXM;
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*vptr = nvr[addr >> 2];
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@@ -478,8 +556,10 @@ return SCPE_OK;
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/* NVR deposit */
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t_stat nvr_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
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t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
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{
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uint32 addr = (uint32) exta;
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if (addr & 03) return SCPE_ARG;
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if (addr >= NVRSIZE) return SCPE_NXM;
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nvr[addr >> 2] = (uint32) val;
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@@ -711,8 +791,8 @@ return;
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struct reglink { /* register linkage */
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int32 low; /* low addr */
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int32 high; /* high addr */
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t_stat (*read)(); /* read routine */
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void (*write)(); }; /* write routine */
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t_stat (*read)(int32 pa); /* read routine */
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void (*write)(int32 pa, int32 val, int32 lnt); }; /* write routine */
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struct reglink regtable[] = {
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{ CQMAPBASE, CQMAPBASE+CQMAPSIZE, &cqmap_rd, &cqmap_wr },
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@@ -1031,13 +1111,31 @@ return;
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clock events per second. Instead, a gross hack is used. When
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a timer is started, the clock interval is inspected.
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if (int < 0 and small) then testing timer, count instructions
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if (int < 0 and small) then testing timer, count instructions.
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Small is determined by when the requested interval is less
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than the size of a 100hz system clock tick.
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if (int >= 0 or large) then counting a real interval, schedule
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clock events at 100Hz using calibrated line clock delay
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and when the remaining time value gets small enough, behave
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like the small case above.
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If the interval register is read, then its value between events
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is interpolated using the current instruction count versus the
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count when the most recent event started.
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count when the most recent event started, the result is scaled
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to the calibrated system clock, unless the interval being timed
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is less than a calibrated system clock tick (or the calibrated
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clock is running very slowly) at which time the result will be
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the elapsed instruction count.
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The powerup TOY Test sometimes fails its tolerance test. This was
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due to varying system load causing varying calibration values to be
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used at different times while referencing the TIR. While timing long
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intervals, we now synchronize the stepping (and calibration) of the
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system tick with the opportunity to reference the value. This gives
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precise tolerance measurement values (when interval timers are used
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to measure the system clock), regardless of other load issues on the
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host system which might cause varying values of the system clock's
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calibration factor.
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*/
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int32 tmr_tir_rd (int32 tmr, t_bool interp)
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@@ -1046,6 +1144,9 @@ uint32 delta;
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if (interp || (tmr_csr[tmr] & TMR_CSR_RUN)) { /* interp, running? */
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delta = sim_grtime () - tmr_sav[tmr]; /* delta inst */
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if ((tmr_inc[tmr] == TMR_INC) && /* scale large int */
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(tmr_poll > TMR_INC))
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delta = (uint32) ((((double) delta) * TMR_INC) / tmr_poll);
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if (delta >= tmr_inc[tmr]) delta = tmr_inc[tmr] - 1;
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return tmr_tir[tmr] + delta; }
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return tmr_tir[tmr];
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@@ -1117,12 +1218,27 @@ return;
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void tmr_sched (int32 tmr)
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{
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int32 clk_time = sim_is_active (&clk_unit) - 1;
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int32 tmr_time;
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tmr_sav[tmr] = sim_grtime (); /* save intvl base */
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if (tmr_tir[tmr] > (0xFFFFFFFFu - TMR_INC)) { /* short interval? */
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tmr_inc[tmr] = (~tmr_tir[tmr] + 1); /* inc = interval */
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sim_activate (&sysd_unit[tmr], tmr_inc[tmr]); }
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tmr_time = tmr_inc[tmr]; }
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else { tmr_inc[tmr] = TMR_INC; /* usec/interval */
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sim_activate (&sysd_unit[tmr], tmr_poll); } /* use calib clock */
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tmr_time = tmr_poll; }
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if (tmr_time == 0) tmr_time = 1;
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if ((tmr_inc[tmr] = TMR_INC) && (tmr_time > clk_time)) {
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/* Align scheduled event to be identical to the event for the next clock
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tick. This lets us always see a consistent calibrated value, both for
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this scheduling, AND for any query of the current timer register that
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may happen in tmr_tir_rd (). This presumes that sim_activate will
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queue the interval timer behind the event for the clock tick. */
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tmr_inc[tmr] = (uint32) (((double) clk_time * TMR_INC) / tmr_poll);
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tmr_time = clk_time; }
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sim_activate (&sysd_unit[tmr], tmr_time);
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return;
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}
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