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Merge branch 'SerialMux' and compiler suggested cleanup

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This commit is contained in:
Mark Pizzolato 2012-12-18 09:52:14 -08:00
commit 50cf91d441
149 changed files with 11789 additions and 1437 deletions
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4
0readme_ethernet.txt
View File

@ -156,9 +156,9 @@ Note 2: Root access will likely be needed to configure or start the vde
Note 3: Simulators running using VDE networking can run without root
privilege.
Linux (Ubuntu 10.04):
Linux (Ubuntu 11.10):
apt-get install make
apt-get install libvdeplug-dev
apt-get install libvdeplug2-dev
apt-get install vde2
vde_switch -s /tmp/switch1 -tap tap0 -m 666

2
ALTAIR/altair_cpu.c
View File

@ -366,7 +366,7 @@ int32 sim_instr (void)
if ((OP & 0xCF) == 0x01) { /* LXI */
DAR = M[PC] & 0x00ff;
PC++;
DAR = DAR | (M[PC] <<8) & 0xFF00;;
DAR = DAR | ((M[PC] <<8) & 0xFF00);
putpair((OP >> 4) & 0x03, DAR);
PC++;
continue;

23
AltairZ80/altairz80_net.c
View File

@ -150,36 +150,33 @@ static t_stat net_reset(DEVICE *dptr) {
}
static t_stat net_attach(UNIT *uptr, char *cptr) {
uint32 i, ipa, ipp;
t_stat r = get_ipaddr(cptr, &ipa, &ipp);
uint32 i;
char host[CBUFSIZE], port[CBUFSIZE];
t_stat r;
r = sim_parse_addr (cptr, host, sizeof(host), "localhost", port, sizeof(port), "3000", NULL);
if (r != SCPE_OK)
return SCPE_ARG;
if (ipa == 0)
ipa = 0x7F000001; /* localhost = 127.0.0.1 */
if (ipp == 0)
ipp = 3000;
net_unit.u3 = ipp;
net_unit.u4 = ipa;
net_reset(&net_dev);
for (i = 0; i <= MAX_CONNECTIONS; i++)
serviceDescriptor[i].ioSocket = 0;
if (net_unit.flags & UNIT_SERVER) {
net_unit.wait = NET_INIT_POLL_SERVER;
serviceDescriptor[1].masterSocket = sim_master_sock(ipp);
serviceDescriptor[1].masterSocket = sim_master_sock(cptr, NULL);
if (serviceDescriptor[1].masterSocket == INVALID_SOCKET)
return SCPE_IOERR;
}
else {
net_unit.wait = NET_INIT_POLL_CLIENT;
serviceDescriptor[0].ioSocket = sim_connect_sock(ipa, ipp);
serviceDescriptor[0].ioSocket = sim_connect_sock(cptr, "localhost", "3000");
if (serviceDescriptor[0].ioSocket == INVALID_SOCKET)
return SCPE_IOERR;
}
net_unit.flags |= UNIT_ATT;
net_unit.filename = (char *) calloc(CBUFSIZE, sizeof (char)); /* alloc name buf */
net_unit.filename = (char *) calloc(1, strlen(cptr)+1); /* alloc name buf */
if (net_unit.filename == NULL)
return SCPE_MEM;
strncpy(net_unit.filename, cptr, CBUFSIZE); /* save name */
strcpy(net_unit.filename, cptr); /* save name */
return SCPE_OK;
}
@ -216,7 +213,7 @@ static t_stat net_svc(UNIT *uptr) {
}
}
else if (serviceDescriptor[0].ioSocket == 0) {
serviceDescriptor[0].ioSocket = sim_connect_sock(net_unit.u4, net_unit.u3);
serviceDescriptor[0].ioSocket = sim_connect_sock(net_unit.filename, "localhost", "3000");
if (serviceDescriptor[0].ioSocket == INVALID_SOCKET)
return SCPE_IOERR;
printf("\rWaiting for server ... Type g<return> (possibly twice) when ready" NLP);

1
HP2100/hp2100_baci.c
View File

@ -26,6 +26,7 @@
BACI 12966A BACI card
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Removed DEV_NET to allow restoration of listening port
28-Mar-11 JDB Tidied up signal handling
26-Oct-10 JDB Changed I/O signal handler for revised signal model
25-Nov-08 JDB Revised for new multiplexer library SHOW routines

1
HP2100/hp2100_defs.h
View File

@ -81,6 +81,7 @@
#pragma GCC diagnostic ignored "-Wunknown-pragmas"
#pragma GCC diagnostic ignored "-Wpragmas"
#pragma GCC diagnostic ignored "-Wlogical-op-parentheses"
#pragma GCC diagnostic ignored "-Wbitwise-op-parentheses"
#endif

9
HP2100/hp2100_di_da.c
View File

@ -25,6 +25,7 @@
DA 12821A Disc Interface with Amigo disc drives
24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash
07-May-12 JDB Cancel the intersector delay if an untalk is received
29-Mar-12 JDB First release
04-Nov-11 JDB Created DA device
@ -757,7 +758,7 @@ switch (if_state [unit]) { /* dispatch the inte
case disc_command: /* execute a disc command */
result = dl_service_drive (cvptr, uptr); /* service the disc unit */
if (cvptr->opcode == clear) /* is this a Clear command? */
if (cvptr->opcode == Clear) /* is this a Clear command? */
if_dsj [unit] = 2; /* indicate that the self test is complete */
if (cvptr->state != cntlr_busy) { /* has the controller stopped? */
@ -857,7 +858,7 @@ switch (if_state [unit]) { /* dispatch the inte
if (cvptr->length == 0 || cvptr->eod == SET) { /* is the data phase complete? */
uptr->PHASE = end_phase; /* set the end phase */
if (cvptr->opcode == request_status) /* is it a Request Status command? */
if (cvptr->opcode == Request_Status) /* is it a Request Status command? */
if_dsj [unit] = 0; /* clear the DSJ value */
if_state [unit] = command_exec; /* set to execute the command */
@ -981,7 +982,7 @@ if (result == SCPE_IERR && DEBUG_PRI (da_dev, DEB_RWSC)) { /* did an internal e
if (if_state [unit] == idle) { /* is the command now complete? */
if (if_command [unit] == disc_command) { /* did a disc command complete? */
if (cvptr->opcode != end) /* yes; if the command was not End, */
if (cvptr->opcode != End) /* yes; if the command was not End, */
di_poll_response (da, unit, SET); /* then enable PPR */
if (DEBUG_PRI (da_dev, DEB_RWSC))
@ -1267,7 +1268,7 @@ result = dl_load_unload (&icd_cntlr [unit], uptr, load); /* load or unload th
if (result == SCPE_OK && ! load) { /* was the unload successful? */
icd_cntlr [unit].status = drive_attention; /* set Drive Attention status */
if (uptr->OP == end) /* is the controller in idle state 2? */
if (uptr->OP == End) /* is the controller in idle state 2? */
di_poll_response (da, unit, SET); /* enable PPR */
}

57
HP2100/hp2100_ds.c
View File

@ -26,6 +26,7 @@
DS 13037D/13175D disc controller/interface
24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash
29-Mar-12 JDB Rewritten to use the MAC/ICD disc controller library
ioIOO now notifies controller service of parameter output
14-Feb-12 JDB Corrected SRQ generation and FIFO under/overrun detection
@ -705,10 +706,10 @@ result = dl_service_drive (&mac_cntlr, uptr); /* service the drive */
if ((CNTLR_PHASE) uptr->PHASE == data_phase) /* is the drive in the data phase? */
switch ((CNTLR_OPCODE) uptr->OP) { /* dispatch the current operation */
case read: /* read operations */
case read_full_sector:
case read_with_offset:
case read_without_verify:
case Read: /* read operations */
case Read_Full_Sector:
case Read_With_Offset:
case Read_Without_Verify:
if (mac_cntlr.length == 0 || ds.edt == SET) { /* is the data phase complete? */
mac_cntlr.eod = ds.edt; /* set EOD if DCPC is done */
uptr->PHASE = end_phase; /* set the end phase */
@ -729,9 +730,9 @@ if ((CNTLR_PHASE) uptr->PHASE == data_phase) /* is the drive in the d
break;
case write: /* write operations */
case write_full_sector:
case initialize:
case Write: /* write operations */
case Write_Full_Sector:
case Initialize:
if (entry_phase == start_phase) { /* is this the phase transition? */
ds.srq = SET; /* start the DCPC transfer */
ds_io (&ds_dib, ioSIR, 0); /* and recalculate the interrupts */
@ -850,19 +851,19 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current
case end_phase: /* start and end on the same phase */
switch (opcode) { /* dispatch the current operation */
case request_status:
case request_sector_address:
case address_record:
case request_syndrome:
case load_tio_register:
case request_disc_address:
case end:
case Request_Status:
case Request_Sector_Address:
case Address_Record:
case Request_Syndrome:
case Load_TIO_Register:
case Request_Disc_Address:
case End:
break; /* complete the operation without setting the flag */
case clear:
case set_file_mask:
case wakeup:
case Clear:
case Set_File_Mask:
case Wakeup:
ds_io (&ds_dib, ioENF, 0); /* complete the operation and set the flag */
break;
@ -877,11 +878,11 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current
case data_phase:
switch (opcode) { /* dispatch the current operation */
case seek: /* operations that accept parameters */
case verify:
case address_record:
case read_with_offset:
case load_tio_register:
case Seek: /* operations that accept parameters */
case Verify:
case Address_Record:
case Read_With_Offset:
case Load_TIO_Register:
buffer [mac_cntlr.index++] = fifo_unload (); /* unload the next word from the FIFO */
mac_cntlr.length--; /* count it */
@ -891,7 +892,7 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current
else { /* all parameters have been received */
uptr->PHASE = end_phase; /* set the end phase */
if (opcode == read_with_offset) /* a Read With Offset command sets the flag */
if (opcode == Read_With_Offset) /* a Read With Offset command sets the flag */
ds_io (&ds_dib, ioENF, 0); /* to indicate that offsetting is complete */
start_command (); /* the command is now ready to execute */
@ -899,10 +900,10 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the current
break;
case request_status: /* operations that supply parameters */
case request_sector_address:
case request_syndrome:
case request_disc_address:
case Request_Status: /* operations that supply parameters */
case Request_Sector_Address:
case Request_Syndrome:
case Request_Disc_Address:
if (mac_cntlr.length) { /* are there more words to return? */
fifo_load (buffer [mac_cntlr.index++]); /* load the next word into the FIFO */
mac_cntlr.length--; /* count it */
@ -1258,7 +1259,7 @@ unit = GET_S1UNIT (mac_cntlr.spd_unit); /* get the (prepared) un
if (unit <= DL_MAXDRIVE) /* is the unit number valid? */
drive_command = (CNTLR_OPCODE) ds_unit [unit].OP; /* get the opcode from the unit that will be used */
else /* the unit is invalid, so the command will not start */
drive_command = end; /* but the compiler doesn't know this! */
drive_command = End; /* but the compiler doesn't know this! */
uptr = dl_start_command (&mac_cntlr, ds_unit, DL_MAXDRIVE); /* ask the controller to start the command */

45
HP2100/hp2100_ipl.c
View File

@ -25,6 +25,7 @@
IPLI, IPLO 12875A interprocessor link
25-Oct-12 JDB Removed DEV_NET to allow restoration of listening ports
09-May-12 JDB Separated assignments from conditional expressions
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Added CARD_INDEX casts to dib.card_index
@ -188,7 +189,7 @@ DEVICE ipli_dev = {
1, 10, 31, 1, 16, 16,
&tmxr_ex, &tmxr_dep, &ipl_reset,
&ipl_boot, &ipl_attach, &ipl_detach,
&ipli_dib, DEV_NET | DEV_DISABLE | DEV_DIS | DEV_DEBUG,
&ipli_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG,
0, ipl_deb, NULL, NULL
};
@ -217,7 +218,7 @@ DEVICE iplo_dev = {
1, 10, 31, 1, 16, 16,
&tmxr_ex, &tmxr_dep, &ipl_reset,
&ipl_boot, &ipl_attach, &ipl_detach,
&iplo_dib, DEV_NET | DEV_DISABLE | DEV_DIS | DEV_DEBUG,
&iplo_dib, DEV_DISABLE | DEV_DIS | DEV_DEBUG,
0, ipl_deb, NULL, NULL
};
@ -570,56 +571,56 @@ return SCPE_OK;
t_stat ipl_attach (UNIT *uptr, char *cptr)
{
SOCKET newsock;
uint32 i, t, ipa, ipp, oldf;
char *tptr;
uint32 i, t, oldf;
char host[CBUFSIZE], port[CBUFSIZE], hostport[2*CBUFSIZE+3];
char *tptr = NULL;
t_stat r;
r = get_ipaddr (cptr, &ipa, &ipp);
if ((r != SCPE_OK) || (ipp == 0))
return SCPE_ARG;
oldf = uptr->flags;
if (oldf & UNIT_ATT)
ipl_detach (uptr);
if ((sim_switches & SWMASK ('C')) ||
((sim_switches & SIM_SW_REST) && (oldf & UNIT_ACTV))) {
if (ipa == 0)
ipa = 0x7F000001;
newsock = sim_connect_sock (ipa, ipp);
r = sim_parse_addr (cptr, host, sizeof(host), "localhost", port, sizeof(port), NULL, NULL);
if ((r != SCPE_OK) || (port[0] == '\0'))
return SCPE_ARG;
sprintf(hostport, "%s%s%s%s%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", host[0] ? ":" : "", port);
newsock = sim_connect_sock (hostport, NULL, NULL);
if (newsock == INVALID_SOCKET)
return SCPE_IOERR;
printf ("Connecting to IP address %d.%d.%d.%d, port %d\n",
(ipa >> 24) & 0xff, (ipa >> 16) & 0xff,
(ipa >> 8) & 0xff, ipa & 0xff, ipp);
printf ("Connecting to %s\n", hostport);
if (sim_log)
fprintf (sim_log,
"Connecting to IP address %d.%d.%d.%d, port %d\n",
(ipa >> 24) & 0xff, (ipa >> 16) & 0xff,
(ipa >> 8) & 0xff, ipa & 0xff, ipp);
"Connecting to %s\n", hostport);
uptr->flags = uptr->flags | UNIT_ACTV;
uptr->LSOCKET = 0;
uptr->DSOCKET = newsock;
}
else {
if (ipa != 0)
r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), NULL, NULL);
if (r != SCPE_OK)
return SCPE_ARG;
newsock = sim_master_sock (ipp);
sprintf(hostport, "%s%s%s%s%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", host[0] ? ":" : "", port);
newsock = sim_master_sock (hostport, &r);
if (r != SCPE_OK)
return r;
if (newsock == INVALID_SOCKET)
return SCPE_IOERR;
printf ("Listening on port %d\n", ipp);
printf ("Listening on port %s\n", hostport);
if (sim_log)
fprintf (sim_log, "Listening on port %d\n", ipp);
fprintf (sim_log, "Listening on port %s\n", hostport);
uptr->flags = uptr->flags & ~UNIT_ACTV;
uptr->LSOCKET = newsock;
uptr->DSOCKET = 0;
}
uptr->IBUF = uptr->OBUF = 0;
uptr->flags = (uptr->flags | UNIT_ATT) & ~(UNIT_ESTB | UNIT_HOLD);
tptr = (char *) malloc (strlen (cptr) + 1); /* get string buf */
tptr = (char *) malloc (strlen (hostport) + 1); /* get string buf */
if (tptr == NULL) { /* no memory? */
ipl_detach (uptr); /* close sockets */
return SCPE_MEM;
}
strcpy (tptr, cptr); /* copy ipaddr:port */
strcpy (tptr, hostport); /* copy ipaddr:port */
uptr->filename = tptr; /* save */
sim_activate (uptr, POLL_FIRST); /* activate first poll "immediately" */
if (sim_switches & SWMASK ('W')) { /* wait? */

1
HP2100/hp2100_mpx.c
View File

@ -26,6 +26,7 @@
MPX 12792C 8-channel multiplexer card
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Removed DEV_NET to allow restoration of listening port
28-Mar-11 JDB Tidied up signal handling
26-Oct-10 JDB Changed I/O signal handler for revised signal model
25-Nov-08 JDB Revised for new multiplexer library SHOW routines

1
HP2100/hp2100_mux.c
View File

@ -26,6 +26,7 @@
MUX,MUXL,MUXM 12920A terminal multiplexor
10-Feb-12 JDB Deprecated DEVNO in favor of SC
Removed DEV_NET to allow restoration of listening port
28-Mar-11 JDB Tidied up signal handling
26-Oct-10 JDB Changed I/O signal handler for revised signal model
25-Nov-08 JDB Revised for new multiplexer library SHOW routines

169
HP2100/hp_disclib.c
View File

@ -24,6 +24,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the authors.
24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash
07-May-12 JDB Corrected end-of-track delay time logic
02-May-12 JDB First release
09-Nov-11 JDB Created disc controller common library from DS simulator
@ -594,8 +595,8 @@ set_timer (cvptr, CLEAR); /* stop the command wait
opcode = GET_OPCODE (cvptr->buffer [0]); /* get the opcode from the command */
if (opcode > last_opcode) /* is the opcode invalid? */
props = &cmd_props [invalid_opcode]; /* undefined commands clear prior status */
if (opcode > Last_Opcode) /* is the opcode invalid? */
props = &cmd_props [Invalid_Opcode]; /* undefined commands clear prior status */
else /* the opcode is potentially valid */
props = &cmd_props [opcode]; /* get the command properties */
@ -794,7 +795,7 @@ cvptr->eod = CLEAR; /* clear the end of data
switch (cvptr->opcode) { /* dispatch the command */
case cold_load_read:
case Cold_Load_Read:
cvptr->cylinder = 0; /* set the cylinder address to 0 */
cvptr->head = GET_CHEAD (cvptr->buffer [0]); /* set the head */
cvptr->sector = GET_CSECT (cvptr->buffer [0]); /* and sector from the command */
@ -802,7 +803,7 @@ switch (cvptr->opcode) { /* dispatch the command
if (is_seeking) { /* if a seek is in progress, */
uptr->STAT |= DL_S2SC; /* a Seek Check occurs */
cvptr->file_mask = DL_FSPEN; /* enable sparing */
uptr->OP = read; /* start the read on the seek completion */
uptr->OP = Read; /* start the read on the seek completion */
uptr->PHASE = start_phase; /* and reset the command phase */
return uptr; /* to allow the seek to complete normally */
}
@ -813,7 +814,7 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case seek:
case Seek:
cvptr->cylinder = cvptr->buffer [1]; /* get the supplied cylinder */
cvptr->head = GET_HEAD (cvptr->buffer [2]); /* and head */
cvptr->sector = GET_SECTOR (cvptr->buffer [2]); /* and sector addresses */
@ -827,7 +828,7 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case request_status:
case Request_Status:
cvptr->buffer [0] = /* set the Status-1 value */
cvptr->spd_unit | SET_S1STAT (cvptr->status); /* into the buffer */
@ -854,12 +855,12 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case request_disc_address:
case Request_Disc_Address:
set_address (cvptr, 0); /* return the CHS values in buffer 0-1 */
break;
case request_sector_address:
case Request_Sector_Address:
if (unit > unit_limit) /* if the unit number is invalid */
rptr = NULL; /* it does not correspond to a unit */
else /* otherwise, the unit is valid */
@ -872,7 +873,7 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case request_syndrome:
case Request_Syndrome:
cvptr->buffer [0] = /* return the Status-1 value in buffer 0 */
cvptr->spd_unit | SET_S1STAT (cvptr->status);
@ -885,7 +886,7 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case address_record:
case Address_Record:
cvptr->cylinder = cvptr->buffer [1]; /* get the supplied cylinder */
cvptr->head = GET_HEAD (cvptr->buffer [2]); /* and head */
cvptr->sector = GET_SECTOR (cvptr->buffer [2]); /* and sector addresses */
@ -893,7 +894,7 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case set_file_mask:
case Set_File_Mask:
cvptr->file_mask = GET_FMASK (cvptr->buffer [0]); /* get the supplied file mask */
if (cvptr->type == MAC) /* if this is a MAC controller, */
@ -901,14 +902,14 @@ switch (cvptr->opcode) { /* dispatch the command
break;
case initialize:
case Initialize:
if (uptr) /* if the unit is valid, */
cvptr->spd_unit |= /* merge the SPD flags */
SET_S1SPD (GET_SPD (cvptr->buffer [0])); /* from the command word */
break;
case verify:
case Verify:
cvptr->verify_count = cvptr->buffer [1]; /* get the supplied sector count */
break;
@ -1078,35 +1079,35 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
case start_phase:
switch (opcode) { /* dispatch the current operation */
case recalibrate:
case seek:
case Recalibrate:
case Seek:
if (start_seek (cvptr, uptr, opcode, end_phase) /* start the seek; if it succeeded, */
&& (cvptr->type == MAC)) /* and this a MAC controller, */
dl_idle_controller (cvptr); /* then go idle until it completes */
break;
case cold_load_read:
if (start_seek (cvptr, uptr, read, start_phase)) /* start the seek; did it succeed? */
case Cold_Load_Read:
if (start_seek (cvptr, uptr, Read, start_phase)) /* start the seek; did it succeed? */
cvptr->file_mask = DL_FSPEN; /* set sparing enabled now */
break;
case read:
case read_with_offset:
case read_without_verify:
case Read:
case Read_With_Offset:
case Read_Without_Verify:
cvptr->length = DL_WPSEC; /* transfer just the data */
result = start_read (cvptr, uptr); /* start the sector read */
break;
case read_full_sector:
case Read_Full_Sector:
cvptr->length = DL_WPFSEC; /* transfer the header/data/trailer */
result = start_read (cvptr, uptr); /* start the sector read */
break;
case verify:
case Verify:
cvptr->length = 0; /* no data transfer needed */
result = start_read (cvptr, uptr); /* start the sector read */
@ -1118,29 +1119,29 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
break;
case write:
case initialize:
case Write:
case Initialize:
cvptr->length = DL_WPSEC; /* transfer just the data */
start_write (cvptr, uptr); /* start the sector write */
break;
case write_full_sector:
case Write_Full_Sector:
cvptr->length = DL_WPFSEC; /* transfer the header/data/trailer */
start_write (cvptr, uptr); /* start the sector write */
break;
case request_status:
case request_sector_address:
case clear:
case address_record:
case request_syndrome:
case set_file_mask:
case load_tio_register:
case request_disc_address:
case end:
case wakeup:
case Request_Status:
case Request_Sector_Address:
case Clear:
case Address_Record:
case Request_Syndrome:
case Set_File_Mask:
case Load_TIO_Register:
case Request_Disc_Address:
case End:
case Wakeup:
dl_service_controller (cvptr, uptr); /* the controller service handles these */
break;
@ -1154,13 +1155,13 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
case data_phase:
switch (opcode) { /* dispatch the current operation */
case read:
case read_full_sector:
case read_with_offset:
case read_without_verify:
case write:
case write_full_sector:
case initialize:
case Read:
case Read_Full_Sector:
case Read_With_Offset:
case Read_Without_Verify:
case Write:
case Write_Full_Sector:
case Initialize:
break; /* data transfers are handled by the caller */
@ -1174,8 +1175,8 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
case end_phase:
switch (opcode) { /* dispatch the operation command */
case recalibrate:
case seek:
case Recalibrate:
case Seek:
if (cvptr->type == ICD) /* is this an ICD controller? */
dl_end_command (cvptr, drive_attention); /* seeks end with Drive Attention status */
else /* if not an ICD controller, */
@ -1183,22 +1184,22 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
break;
case read:
case read_full_sector:
case read_with_offset:
case Read:
case Read_Full_Sector:
case Read_With_Offset:
end_read (cvptr, uptr); /* end the sector read */
break;
case read_without_verify:
case Read_Without_Verify:
if (cvptr->sector == 0) /* have we reached the end of the track? */
uptr->OP = read; /* begin verifying the next time */
uptr->OP = Read; /* begin verifying the next time */
end_read (cvptr, uptr); /* end the sector read */
break;
case verify:
case Verify:
cvptr->verify_count = /* decrement the count */
(cvptr->verify_count - 1) & DMASK; /* modulo 65536 */
@ -1209,16 +1210,16 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
break;
case write:
case write_full_sector:
case initialize:
case Write:
case Write_Full_Sector:
case Initialize:
result = end_write (cvptr, uptr); /* end the sector write */
break;
case request_status:
case request_sector_address:
case request_disc_address:
case Request_Status:
case Request_Sector_Address:
case Request_Disc_Address:
dl_service_controller (cvptr, uptr); /* the controller service handles these */
break;
@ -1278,33 +1279,33 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
case start_phase:
case end_phase:
switch (opcode) { /* dispatch the current operation */
case request_status:
case Request_Status:
dl_end_command (cvptr, cvptr->status); /* the command completes with no status change */
break;
case clear:
case Clear:
dl_clear_controller (cvptr, uptr, soft_clear); /* clear the controller */
dl_end_command (cvptr, normal_completion); /* the command is complete */
break;
case request_sector_address:
case address_record:
case request_syndrome:
case set_file_mask:
case load_tio_register:
case request_disc_address:
case Request_Sector_Address:
case Address_Record:
case Request_Syndrome:
case Set_File_Mask:
case Load_TIO_Register:
case Request_Disc_Address:
dl_end_command (cvptr, normal_completion); /* the command is complete */
break;
case end:
case End:
dl_idle_controller (cvptr); /* the command completes with the controller idle */
break;
case wakeup:
case Wakeup:
dl_end_command (cvptr, unit_available); /* the command completes with Unit Available status */
break;
@ -1319,11 +1320,11 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
case data_phase:
switch (opcode) { /* dispatch the current operation */
case seek:
case verify:
case address_record:
case read_with_offset:
case load_tio_register:
case Seek:
case Verify:
case Address_Record:
case Read_With_Offset:
case Load_TIO_Register:
if (cvptr->length > 1) /* at least one more parameter to input? */
set_timer (cvptr, SET); /* restart the timer for the next parameter */
else /* this is the last one */
@ -1331,10 +1332,10 @@ switch ((CNTLR_PHASE) uptr->PHASE) { /* dispatch the phase */
break;
case request_status:
case request_sector_address:
case request_syndrome:
case request_disc_address:
case Request_Status:
case Request_Sector_Address:
case Request_Syndrome:
case Request_Disc_Address:
if (cvptr->length > 0) /* at least one more to parameter output? */
set_timer (cvptr, SET); /* restart the timer for the next parameter */
else /* this is the last one */
@ -1505,8 +1506,8 @@ for (unit = 0; unit < unit_count; unit++) { /* loop through the unit
if (!(uptr->flags & UNIT_DIS)) { /* is the unit enabled? */
if (clear_type == hard_clear /* a hard clear cancels */
&& uptr->OP != seek /* only if not seeking */
&& uptr->OP != recalibrate) /* or recalibrating */
&& uptr->OP != Seek /* only if not seeking */
&& uptr->OP != Recalibrate) /* or recalibrating */
sim_cancel (uptr); /* cancel the service */
uptr->STAT &= ~DL_S2CPS; /* do "Controller Preset" for the unit */
@ -1597,7 +1598,7 @@ return SCPE_OK;
CNTLR_CLASS dl_classify (CNTLR_VARS cntlr)
{
if (cntlr.type <= last_type /* if the controller type is legal */
&& cntlr.opcode <= last_opcode /* and the opcode is legal */
&& cntlr.opcode <= Last_Opcode /* and the opcode is legal */
&& cmd_props [cntlr.opcode].valid [cntlr.type]) /* and is defined for this controller, */
return cmd_props [cntlr.opcode].classification; /* then return the command classification */
else /* the type or opcode is illegal */
@ -1615,7 +1616,7 @@ else /* the type or opcode is
const char *dl_opcode_name (CNTLR_TYPE controller, CNTLR_OPCODE opcode)
{
if (controller <= last_type /* if the controller type is legal */
&& opcode <= last_opcode /* and the opcode is legal */
&& opcode <= Last_Opcode /* and the opcode is legal */
&& cmd_props [opcode].valid [controller]) /* and is defined for this controller, */
return opcode_name [opcode]; /* then return the opcode name */
else /* the type or opcode is illegal, */
@ -1776,7 +1777,7 @@ if (cvptr->eod == SET) { /* is the end of data in
return SCPE_OK;
}
if (opcode == read_full_sector) { /* are we starting a Read Full Sector command? */
if (opcode == Read_Full_Sector) { /* are we starting a Read Full Sector command? */
if (cvptr->type == ICD) /* is this an ICD controller? */
cvptr->buffer [0] = 0100377; /* ICD does not support ECC */
else
@ -1789,7 +1790,7 @@ if (opcode == read_full_sector) { /* are we starting a Rea
else { /* it's another read command */
offset = 0; /* data starts at the beginning */
verify = (opcode != read_without_verify); /* set for address verification unless it's a RWV */
verify = (opcode != Read_Without_Verify); /* set for address verification unless it's a RWV */
}
if (! position_sector (cvptr, uptr, verify)) /* position the sector */
@ -1911,7 +1912,7 @@ return;
static void start_write (CVPTR cvptr, UNIT *uptr)
{
const t_bool verify = (CNTLR_OPCODE) uptr->OP == write; /* only Write verifies the sector address */
const t_bool verify = (CNTLR_OPCODE) uptr->OP == Write; /* only Write verifies the sector address */
if ((uptr->flags & UNIT_WPROT) /* is the unit write protected, */
|| !verify && !(uptr->flags & UNIT_FMT)) /* or is formatting required but not enabled? */
@ -1959,7 +1960,7 @@ static t_stat end_write (CVPTR cvptr, UNIT *uptr)
uint32 count;
uint16 pad;
const CNTLR_OPCODE opcode = (CNTLR_OPCODE) uptr->OP;
const uint32 offset = (opcode == write_full_sector ? 3 : 0);
const uint32 offset = (opcode == Write_Full_Sector ? 3 : 0);
if (uptr->flags & UNIT_UNLOAD) { /* if the drive is not ready, */
dl_end_command (cvptr, access_not_ready); /* terminate the command with an error */
@ -2200,7 +2201,7 @@ if (uptr->flags & UNIT_UNLOAD) { /* are the heads unloade
return FALSE; /* as the drive was not ready */
}
if ((CNTLR_OPCODE) uptr->OP == recalibrate) /* is the unit recalibrating? */
if ((CNTLR_OPCODE) uptr->OP == Recalibrate) /* is the unit recalibrating? */
target_cylinder = 0; /* seek to cylinder 0 and don't reset the EOC flag */
else { /* it's a Seek command or an auto-seek request */

49
HP2100/hp_disclib.h
View File

@ -24,6 +24,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the authors.
24-Oct-12 JDB Changed CNTLR_OPCODE to title case to avoid name clash
07-May-12 JDB Added end-of-track delay time as a controller variable
02-May-12 JDB First release
09-Nov-11 JDB Created disc controller common library from DS simulator
@ -206,29 +207,29 @@ typedef enum {
/* Controller opcodes */
typedef enum {
cold_load_read = 000,
recalibrate = 001,
seek = 002,
request_status = 003,
request_sector_address = 004,
read = 005,
read_full_sector = 006,
verify = 007,
write = 010,
write_full_sector = 011,
clear = 012,
initialize = 013,
address_record = 014,
request_syndrome = 015,
read_with_offset = 016,
set_file_mask = 017,
invalid_opcode = 020,
read_without_verify = 022,
load_tio_register = 023,
request_disc_address = 024,
end = 025,
wakeup = 026,
last_opcode = wakeup /* last valid opcode */
Cold_Load_Read = 000,
Recalibrate = 001,
Seek = 002,
Request_Status = 003,
Request_Sector_Address = 004,
Read = 005,
Read_Full_Sector = 006,
Verify = 007,
Write = 010,
Write_Full_Sector = 011,
Clear = 012,
Initialize = 013,
Address_Record = 014,
Request_Syndrome = 015,
Read_With_Offset = 016,
Set_File_Mask = 017,
Invalid_Opcode = 020,
Read_Without_Verify = 022,
Load_TIO_Register = 023,
Request_Disc_Address = 024,
End = 025,
Wakeup = 026,
Last_Opcode = Wakeup /* last valid opcode */
} CNTLR_OPCODE;
#define DL_OPCODE_MASK 037
@ -353,7 +354,7 @@ typedef CNTLR_VARS *CVPTR; /* pointer to controller
*/
#define CNTLR_INIT(ctype,bufptr,auxptr) \
(ctype), cntlr_idle, end, normal_completion, \
(ctype), cntlr_idle, End, normal_completion, \
CLEAR, CLEAR, \
0, 0, 0, 0, 0, 0, 0, 0, \
(bufptr), 0, 0, (auxptr), \

2
I1401/i1401_cd.c
View File

@ -398,7 +398,7 @@ static const unsigned char boot_rom[] = {
t_stat cdr_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_IS;
for (i = 0; i < CDR_WIDTH; i++) /* clear buffer */

4
I1620/i1620_pt.c
View File

@ -348,7 +348,7 @@ return SCPE_OK;
/* Bootstrap routine */
const static uint8 boot_rom[] = {
static const uint8 boot_rom[] = {
4, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* NOP */
3, 6, 0, 0, 0, 3, 1, 0, 0, 3, 0, 0, /* RNPT 31 */
2, 5, 0, 0, 0, 7, 1, 0, 0, 0, 0, 0, /* TD 71,loc */
@ -363,7 +363,7 @@ const static uint8 boot_rom[] = {
t_stat ptr_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern uint32 saved_PC;
for (i = 0; i < BOOT_LEN; i++)

6
I7094/i7094_com.c
View File

@ -183,10 +183,10 @@ uint32 com_chob_v = 0; /* valid flag */
t_uint64 com_buf[COM_BUFSIZ]; /* channel buffer */
LISTHD com_free; /* free list */
uint32 com_not_ret[COM_TLINES] = { 0 }; /* chars not returned */
LISTHD com_inpq[COM_TLINES] = { 0 }; /* input queues */
LISTHD com_outq[COM_TLINES] = { 0 }; /* output queues */
LISTHD com_inpq[COM_TLINES] = { {0} }; /* input queues */
LISTHD com_outq[COM_TLINES] = { {0} }; /* output queues */
LISTENT com_pkt[COM_PKTSIZ]; /* character packets */
TMLN com_ldsc[COM_MLINES] = { 0 }; /* line descriptors */
TMLN com_ldsc[COM_MLINES] = { {0} }; /* line descriptors */
TMXR com_desc = { COM_MLINES, 0, 0, com_ldsc }; /* mux descriptor */
/* Even parity truth table */

10
Ibm1130/ibm1130_cpu.c
View File

@ -768,7 +768,7 @@ t_stat sim_instr (void)
CCC--;
}
C = (CCC != 0);
WriteIndex(TAG, ReadIndex(TAG) & 0xFF00 | CCC); /* put 6 bits back into low byte of index register */
WriteIndex(TAG, (ReadIndex(TAG) & 0xFF00) | CCC); /* put 6 bits back into low byte of index register */
break;
}
/* if TAG == 0, fall through and treat like normal shift SLT */
@ -814,8 +814,8 @@ t_stat sim_instr (void)
while (CCC > 0) {
xbit = (ACC & 0x0001) << 15;
abit = (ACC & 0x8000);
ACC = (ACC >> 1) & 0x7FFF | abit;
EXT = (EXT >> 1) & 0x7FFF | xbit;
ACC = ((ACC >> 1) & 0x7FFF) | abit;
EXT = ((EXT >> 1) & 0x7FFF) | xbit;
CCC--;
}
break;
@ -824,8 +824,8 @@ t_stat sim_instr (void)
while (CCC > 0) {
abit = (EXT & 0x0001) << 15;
xbit = (ACC & 0x0001) << 15;
ACC = (ACC >> 1) & 0x7FFF | abit;
EXT = (EXT >> 1) & 0x7FFF | xbit;
ACC = ((ACC >> 1) & 0x7FFF) | abit;
EXT = ((EXT >> 1) & 0x7FFF) | xbit;
CCC--;
}
break;

118
Ibm1130/ibm1130_sca.c
View File

@ -85,9 +85,6 @@
#include "ibm1130_defs.h"
#include "sim_sock.h" /* include path must include main simh directory */
#include <ctype.h>
#ifndef INADDR_NONE
#define INADDR_NONE ((unsigned long)-1)
#endif
#define DEBUG_SCA_FLUSH 0x0001 /* debugging options */
#define DEBUG_SCA_TRANSMIT 0x0002
@ -106,7 +103,7 @@
/* #define DEBUG_SCA (DEBUG_SCA_TIMERS|DEBUG_SCA_FLUSH|DEBUG_SCA_TRANSMIT|DEBUG_SCA_CHECK_INDATA|DEBUG_SCA_RECEIVE_SYNC|DEBUG_SCA_RECEIVE_DATA|DEBUG_SCA_XIO_INITR|DEBUG_SCA_XIO_INITW) */
#define DEBUG_SCA (DEBUG_SCA_TIMERS|DEBUG_SCA_FLUSH|DEBUG_SCA_CHECK_INDATA|DEBUG_SCA_XIO_INITR|DEBUG_SCA_XIO_INITW)
#define SCA_DEFAULT_PORT 2703 /* default socket, This is the number of the IBM 360's BSC device */
#define SCA_DEFAULT_PORT "2703" /* default socket, This is the number of the IBM 360's BSC device */
#define MAX_SYNS 100 /* number of consecutive syn's after which we stop buffering them */
@ -164,7 +161,7 @@ static uint32 sca_state = SCA_STATE_IDLE;
static uint8 sichar = 0; /* sync/idle character */
static uint8 rcvd_char = 0; /* most recently received character */
static uint8 sca_frame = 8;
static uint16 sca_port = SCA_DEFAULT_PORT; /* listening port number */
static char sca_port[CBUFSIZE]; /* listening port */
static int32 sca_keepalive = 0; /* keepalive SYN packet period in msec, default = 0 (disabled) */
static SCA_TIMER_STATE sca_timer_state[3]; /* current timer state */
static int sca_timer_endtime[3]; /* clocktime when timeout is to occur if state is RUNNING */
@ -221,7 +218,7 @@ REG sca_reg[] = { /* DEVICE STATE/SETTABLE PARAMETERS: */
{ DRDATA (SCASTATE, sca_state, 32), PV_LEFT }, /* current state */
{ DRDATA (CTIME, sca_cwait, 32), PV_LEFT }, /* inter-character wait */
{ DRDATA (ITIME, sca_iwait, 32), PV_LEFT }, /* idle wait (polling interval for socket connects) */
{ DRDATA (SCASOCKET, sca_port, 16), PV_LEFT }, /* listening port number */
{ BRDATA (SCASOCKET, sca_port, 8, 8, sizeof(sca_port)) }, /* listening port number */
{ DRDATA (KEEPALIVE, sca_keepalive, 32), PV_LEFT }, /* keepalive packet period in msec */
{ NULL } };
@ -317,7 +314,7 @@ static void sca_socket_error (void)
free(sca_unit.filename);
if (sca_unit.flags & UNIT_LISTEN) {
sprintf(name, "(Listening on port %d)", sca_port);
sprintf(name, "(Listening on port %s)", sca_port);
sca_unit.filename = mstring(name);
printf("%s\n", name);
}
@ -454,99 +451,75 @@ static t_stat sca_reset (DEVICE *dptr)
static t_stat sca_attach (UNIT *uptr, char *cptr)
{
char host[CBUFSIZE], port[CBUFSIZE];
t_bool do_listen;
char *colon;
uint32 ipaddr;
int32 port;
struct hostent *he;
char name[256];
static SOCKET sdummy = INVALID_SOCKET;
fd_set wr_set, err_set;
char name[CBUFSIZE];
t_stat r;
do_listen = sim_switches & SWMASK('L'); /* -l means listen mode */
if (sca_unit.flags & UNIT_ATT) /* if already attached, detach */
detach_unit(&sca_unit);
if (do_listen) { /* if listen mode, string specifies socket number (only; otherwise it's a dummy argument) */
if (isdigit(*cptr)) { /* if digits specified, extract port number */
port = atoi(cptr);
if (port <= 0 || port > 65535)
return SCPE_ARG;
else
sca_port = port;
}
if (do_listen) { /* if listen mode, string specifies port number (only; otherwise it's a dummy argument) */
r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), SCA_DEFAULT_PORT, NULL);
if (r != SCPE_OK)
return r;
if ((0 == strcmp(port, cptr)) && (0 == strcmp(port, "dummy")))
strcpy(port, SCA_DEFAULT_PORT);
sprintf(sca_port, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port);
/* else if nondigits specified, ignore... but the command has to have something there otherwise the core scp */
/* attach_cmd() routine complains "too few arguments". */
if ((sca_lsock = sim_master_sock(sca_port)) == INVALID_SOCKET)
sca_lsock = sim_master_sock(sca_port, &r);
if (r != SCPE_OK)
return r;
if (sca_lsock == INVALID_SOCKET)
return SCPE_OPENERR;
SETBIT(sca_unit.flags, UNIT_LISTEN); /* note that we are listening, not yet connected */
sprintf(name, "(Listening on port %d)", sca_port);
sca_unit.filename = mstring(name);
printf("%s\n", name);
sprintf(name, "(Listening on port %s)", sca_port);
sca_unit.filename = mstring(name);
printf("%s\n", sca_unit.filename);
}
else {
while (*cptr && *cptr <= ' ')
while (*cptr && *cptr <= ' ')
cptr++;
if (! *cptr)
return SCPE_2FARG;
if ((colon = strchr(cptr, ':')) != NULL) {
*colon++ = '\0'; /* clip hostname at colon */
r = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), SCA_DEFAULT_PORT, NULL);
if (r != SCPE_OK)
return r;
if ((0 == strcmp(cptr, port)) && (0 == strcmp(host, ""))) {
strcpy(host, port);
strcpy(port, SCA_DEFAULT_PORT);
}
port = atoi(colon); /* extract port number that follows it */
if (port <= 0 || port > 65535)
return SCPE_ARG;
else
sca_port = port;
}
sprintf(sca_port, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port);
if (sdummy == INVALID_SOCKET)
if ((sdummy = sim_create_sock()) == INVALID_SOCKET) /* create and keep a socket, to force initialization */
return SCPE_IERR; /* of socket library (e.g on Win32 call WSAStartup), else gethostbyname fails */
if (get_ipaddr(cptr, &ipaddr, NULL) != SCPE_OK) { /* try to parse hostname as dotted decimal nnn.nnn.nnn.nnn */
if ((he = gethostbyname(cptr)) == NULL) /* if not decimal, look up name through DNS */
return SCPE_OPENERR;
if ((ipaddr = * (unsigned long *) he->h_addr_list[0]) == INADDR_NONE)
return SCPE_OPENERR;
ipaddr = ntohl(ipaddr); /* convert to host byte order; gethostbyname() gives us network order */
}
if ((sca_sock = sim_connect_sock(ipaddr, sca_port)) == INVALID_SOCKET)
if ((sca_sock = sim_connect_sock(sca_port, NULL, NULL)) == INVALID_SOCKET)
return SCPE_OPENERR;
/* sim_connect_sock() sets socket to nonblocking before initiating the connect, so
* the connect is pending when it returns. For outgoing connections, the attach command should wait
* until the connection succeeds or fails. We use "accept" to wait and find out which way it goes...
* until the connection succeeds or fails. We use "sim_check_conn" to wait and find out which way it goes...
*/
FD_ZERO(&wr_set); /* we are only interested in info for sca_sock */
FD_ZERO(&err_set);
FD_SET(sca_sock, &wr_set);
FD_SET(sca_sock, &err_set);
while (0 == sim_check_conn(sca_sock, 0))/* wait for connection to complete or fail */
sim_os_ms_sleep(1000);
select(3, NULL, &wr_set, &err_set, NULL); /* wait for connection to complete or fail */
if (FD_ISSET(sca_sock, &wr_set)) { /* sca_sock appears in "writable" set -- connect completed */
sprintf(name, "%s:%d", cptr, sca_port);
if (1 == sim_check_conn(sca_sock, 0)) { /* sca_sock appears in "writable" set -- connect completed */
sprintf(name, "%s%s%s:%s", strchr(host, ':') ? "[" : "", host, strchr(host, ':') ? "]" : "", port);
sca_unit.filename = mstring(name);
SETBIT(sca_dsw, SCA_DSW_READY);
}
else if (FD_ISSET(sca_sock, &err_set)) { /* sca_sock appears in "error" set -- connect failed */
sim_close_sock(sca_sock, TRUE);
sca_sock = INVALID_SOCKET;
return SCPE_OPENERR;
}
else { /* if we get here my assumption about how select works is wrong */
printf("SCA_SOCK NOT FOUND IN WR_SET -OR- ERR_SET, CODING IN IBM1130_SCA IS WRONG\n");
else { /* sca_sock appears in "error" set -- connect failed */
sim_close_sock(sca_sock, TRUE);
sca_sock = INVALID_SOCKET;
return SCPE_OPENERR;
@ -610,22 +583,17 @@ static t_stat sca_detach (UNIT *uptr)
static void sca_check_connect (void)
{
uint32 ipaddr;
char name[100];
char *connectaddress;
if ((sca_sock = sim_accept_conn(sca_lsock, &ipaddr)) == INVALID_SOCKET)
if ((sca_sock = sim_accept_conn(sca_lsock, &connectaddress)) == INVALID_SOCKET)
return;
ipaddr = htonl(ipaddr); /* convert to network order so we can print it */
sprintf(name, "%d.%d.%d.%d", ipaddr & 0xFF, (ipaddr >> 8) & 0xFF, (ipaddr >> 16) & 0xFF, (ipaddr >> 24) & 0xFF);
printf("(SCA connection from %s)\n", name);
printf("(SCA connection from %s)\n", connectaddress);
if (sca_unit.filename != NULL)
free(sca_unit.filename);
sca_unit.filename = mstring(name);
sca_unit.filename = connectaddress;
SETBIT(sca_dsw, SCA_DSW_READY); /* indicate active connection */

2
Interdata/id32_cpu.c
View File

@ -222,7 +222,7 @@ uint32 GREG[16 * NRSETS] = { 0 }; /* general registers */
uint32 *M = NULL; /* memory */
uint32 *R = &GREG[0]; /* working reg set */
uint32 F[8] = { 0 }; /* sp fp registers */
dpr_t D[8] = { 0 }; /* dp fp registers */
dpr_t D[8] = { {0} }; /* dp fp registers */
uint32 PSW = 0; /* processor status word */
uint32 PC = 0; /* program counter */
uint32 oPC = 0; /* PC at inst start */

2
Interdata/id_fd.c
View File

@ -115,7 +115,7 @@ uint32 fd_cmd = 0; /* command */
uint32 fd_db = 0; /* data buffer */
uint32 fd_bptr = 0; /* buffer pointer */
uint8 fdxb[FD_NUMBY] = { 0 }; /* sector buffer */
uint8 fd_es[FD_NUMDR][ES_SIZE] = { 0 }; /* ext status */
uint8 fd_es[FD_NUMDR][ES_SIZE] = { {0} }; /* ext status */
uint32 fd_lrn = 0; /* log rec # */
uint32 fd_wdv = 0; /* wd valid */
uint32 fd_stopioe = 1; /* stop on error */

2
Interdata/id_pas.c
View File

@ -103,7 +103,7 @@ uint8 pas_xarm[PAS_LINES]; /* xmt int armed */
uint8 pas_rchp[PAS_LINES]; /* rcvr chr pend */
uint8 pas_tplte[PAS_LINES * 2 + 1]; /* template */
TMLN pas_ldsc[PAS_LINES] = { 0 }; /* line descriptors */
TMLN pas_ldsc[PAS_LINES] = { {0} }; /* line descriptors */
TMXR pas_desc = { 8, 0, 0, pas_ldsc }; /* mux descriptor */
#define PAS_ENAB pas_desc.lines

3
Interdata/id_ttp.c
View File

@ -130,7 +130,7 @@ DEVICE ttp_dev = {
uint32 ttp (uint32 dev, uint32 op, uint32 dat)
{
int32 xmt = dev & 1;
int32 t, old_cmd;
int32 t;
switch (op) { /* case IO op */
@ -160,7 +160,6 @@ switch (op) { /* case IO op */
return t;
case IO_OC: /* command */
old_cmd = ttp_cmd; /* old cmd */
if (dat & CMD_TYP) { /* type 1? */
ttp_cmd = (ttp_cmd & 0xFF) | (dat << 8);
if (ttp_cmd & CMD_WRT) /* write? */

2
NOVA/nova_qty.c
View File

@ -222,7 +222,7 @@ DEVICE qty_dev =
#define QTY_LINE_RX_CHAR( line ) (qty_status[ (line) ] & QTY_S_DMASK)
#define QTY_UNIT_ACTIVE( unitp ) ( (unitp)->conn )
#define QTY_LINE_BITS( line, bits ) qty_status[ (line) ] & bits
#define QTY_LINE_BITS( line, bits ) (qty_status[ (line) ] & bits)
#define QTY_LINE_SET_BIT( line, bit ) qty_status[ (line) ] |= (bit) ;
#define QTY_LINE_CLEAR_BIT( line, bit ) qty_status[ (line) ] &= ~(bit) ;

2
PDP1/pdp1_dcs.c
View File

@ -48,7 +48,7 @@ uint8 dcs_buf[DCS_LINES]; /* line bufffers */
extern int32 iosta, stop_inst;
extern int32 tmxr_poll;
TMLN dcs_ldsc[DCS_LINES] = { 0 }; /* line descriptors */
TMLN dcs_ldsc[DCS_LINES] = { {0} }; /* line descriptors */
TMXR dcs_desc = { DCS_LINES, 0, 0, dcs_ldsc }; /* mux descriptor */
t_stat dcsi_svc (UNIT *uptr);

2
PDP10/pdp10_rp.c
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@ -1286,7 +1286,7 @@ static const d10 boot_rom_its[] = {
t_stat rp_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern a10 saved_PC;
M[FE_UNIT] = unitno & CS2_M_UNIT;

2
PDP10/pdp10_tu.c
View File

@ -1273,7 +1273,7 @@ static const d10 boot_rom_its[] = {
t_stat tu_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern a10 saved_PC;
M[FE_UNIT] = 0;

14
PDP11/pdp11_cis.c
View File

@ -170,7 +170,7 @@ typedef struct {
uint32 val[DSTRLNT];
} DSTR;
static DSTR Dstr0 = { 0, 0, 0, 0, 0 };
static DSTR Dstr0 = { 0, {0, 0, 0, 0} };
extern int32 isenable, dsenable;
extern int32 N, Z, V, C, fpd, ipl;
@ -321,14 +321,12 @@ static int32 overbin[128] = {
/* Overpunch to ASCII table: indexed by sign and digit */
static int32 binover[2][16] = {
'{', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I',
'0', '0', '0', '0', '0', '0',
'}', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R',
'0', '0', '0', '0', '0', '0'
{'{', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I',
'0', '0', '0', '0', '0', '0'},
{'}', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R',
'0', '0', '0', '0', '0', '0'}
};
static unsigned char movbuf[65536];
/* CIS emulator */
t_stat cis11 (int32 IR)
@ -342,7 +340,7 @@ uint32 nc, digit, result;
t_stat st;
static DSTR accum, src1, src2, dst;
static DSTR mptable[10];
static DSTR Dstr1 = { 0, 0x10, 0, 0, 0 };
static DSTR Dstr1 = { 0, {0x10, 0, 0, 0} };
old_PC = (PC - 2) & 0177777; /* original PC */
op = IR & 0177; /* IR <6:0> */

6
PDP11/pdp11_cpu.c
View File

@ -256,7 +256,7 @@ typedef struct {
extern FILE *sim_log;
uint16 *M = NULL; /* memory */
int32 REGFILE[6][2] = { 0 }; /* R0-R5, two sets */
int32 REGFILE[6][2] = { {0} }; /* R0-R5, two sets */
int32 STACKFILE[4] = { 0 }; /* SP, four modes */
int32 saved_PC = 0; /* program counter */
int32 R[8] = { 0 }; /* working registers */
@ -273,7 +273,7 @@ int32 trap_req = 0; /* trap requests */
int32 int_req[IPL_HLVL] = { 0 }; /* interrupt requests */
int32 PIRQ = 0; /* programmed int req */
int32 STKLIM = 0; /* stack limit */
fpac_t FR[6] = { 0 }; /* fp accumulators */
fpac_t FR[6] = { {0} }; /* fp accumulators */
int32 FPS = 0; /* fp status */
int32 FEC = 0; /* fp exception code */
int32 FEA = 0; /* fp exception addr */
@ -1246,7 +1246,7 @@ while (reason == 0) {
else dst = R[dstspec];
}
else {
i = ((cm == pm) && (cm == MD_USR))? calc_ds (pm): calc_is (pm);
i = ((cm == pm) && (cm == MD_USR))? (int32)calc_ds (pm): (int32)calc_is (pm);
dst = ReadW ((GeteaW (dstspec) & 0177777) | i);
}
N = GET_SIGN_W (dst);

2
PDP11/pdp11_cpumod.c
View File

@ -1159,7 +1159,7 @@ if ((mc != 0) && !get_yn ("Really truncate memory [N]?", FALSE))
nM = (uint16 *) calloc (val >> 1, sizeof (uint16));
if (nM == NULL)
return SCPE_MEM;
clim = (((t_addr) val) < MEMSIZE)? val: MEMSIZE;
clim = (((t_addr) val) < MEMSIZE)? (uint32)val: MEMSIZE;
for (i = 0; i < clim; i = i + 2)
nM[i >> 1] = M[i >> 1];
free (M);

2
PDP11/pdp11_dc.c
View File

@ -86,7 +86,7 @@ uint32 dci_ireq = 0;
uint16 dco_csr[DCX_LINES] = { 0 }; /* control/status */
uint8 dco_buf[DCX_LINES] = { 0 };
uint32 dco_ireq = 0;
TMLN dcx_ldsc[DCX_LINES] = { 0 }; /* line descriptors */
TMLN dcx_ldsc[DCX_LINES] = { {0} }; /* line descriptors */
TMXR dcx_desc = { DCX_LINES, 0, 0, dcx_ldsc }; /* mux descriptor */
static const uint8 odd_par[] = {

6
PDP11/pdp11_defs.h
View File

@ -662,6 +662,8 @@ typedef struct pdp_dib DIB;
#define INT_V_TU 15
#define INT_V_RF 16
#define INT_V_RC 17
#define INT_V_DMCRX 18
#define INT_V_DMCTX 19
#define INT_V_PIR4 0 /* BR4 */
#define INT_V_TTI 1
@ -705,6 +707,8 @@ typedef struct pdp_dib DIB;
#define INT_TU (1u << INT_V_TU)
#define INT_RF (1u << INT_V_RF)
#define INT_RC (1u << INT_V_RC)
#define INT_DMCRX (1u << INT_V_DMCRX)
#define INT_DMCTX (1u << INT_V_DMCTX)
#define INT_PIR4 (1u << INT_V_PIR4)
#define INT_TTI (1u << INT_V_TTI)
#define INT_TTO (1u << INT_V_TTO)
@ -751,6 +755,8 @@ typedef struct pdp_dib DIB;
#define IPL_TU 5
#define IPL_RF 5
#define IPL_RC 5
#define IPL_DMCRX 5
#define IPL_DMCTX 5
#define IPL_PTR 4
#define IPL_PTP 4
#define IPL_TTI 4

2
PDP11/pdp11_dl.c
View File

@ -87,7 +87,7 @@ uint32 dli_ireq[2] = { 0, 0};
uint16 dlo_csr[DLX_LINES] = { 0 }; /* control/status */
uint8 dlo_buf[DLX_LINES] = { 0 };
uint32 dlo_ireq = 0;
TMLN dlx_ldsc[DLX_LINES] = { 0 }; /* line descriptors */
TMLN dlx_ldsc[DLX_LINES] = { {0} }; /* line descriptors */
TMXR dlx_desc = { DLX_LINES, 0, 0, dlx_ldsc }; /* mux descriptor */
t_stat dlx_rd (int32 *data, int32 PA, int32 access);

2267
PDP11/pdp11_dmc.c Normal file
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File diff suppressed because it is too large Load Diff

132
PDP11/pdp11_dmc.h Normal file
View File

@ -0,0 +1,132 @@
/* pdp11_dmc.h: DMC11 Emulation
------------------------------------------------------------------------------
Copyright (c) 2011, Robert M. A. Jarratt
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of the author shall not be
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from the author.
------------------------------------------------------------------------------*/
// Notes
// Base address needs to be 760060 according to DMC11 manual, but SYSGEN seems to think CSR is 0760100. However if I use
// 0760100 I get a conflict with the DZ because the first 13 bits are still 00100. If I use 760060 VMS sees the XM device, but
// if I remove the DZ to prevent the conflict VMS does not see an XM device, but I do get lots of reads and writes, possibly
// because it thinks it is a different device. What worries me more though is that there seems to be overlap in the 13-bit base
// addresses of the DZ and DMC.
#ifndef _PDP11_DMC_H
#define _PDP11_DMC_H
#if defined (VM_VAX) /* VAX version */
#include "vax_defs.h"
extern int32 int_req[IPL_HLVL];
#else /* PDP-11 version */
#include "pdp11_defs.h"
extern int32 int_req[IPL_HLVL];
#endif
#include "sim_sock.h"
#define DMC_NUMDEVICE 4 /* # DMC-11 devices */
#define DMC_UNITSPERDEVICE 1 /* # units per DMC-11 */
#define DMP_NUMDEVICE 1 /* # DMP-11 devices */
#define DMP_UNITSPERDEVICE 1 /* # units per DMP-11 */
#define DMC_RDX 8
/* debugging bitmaps */
#define DBG_TRC 0x0001 /* trace routine calls */
#define DBG_REG 0x0002 /* trace read/write registers */
#define DBG_WRN 0x0004 /* display warnings */
#define DBG_INF 0x0008 /* display informational messages (high level trace) */
#define DBG_DAT 0x0010 /* display data buffer contents */
#define DBG_DTS 0x0020 /* display data summary */
#define DBG_SOK 0x0040 /* display socket open/close */
#define DBG_CON 0x0080 /* display socket connection establishment */
#define TYPE_BACCI 0
#define TYPE_CNTLI 1
#define TYPE_BASEI 03
#define TYPE_BACCO 0
#define TYPE_CNTLO 1
#define TYPE_DMP_MODE 2
#define TYPE_DMP_CONTROL 1
#define TYPE_DMP_RECEIVE 0
#define TYPE_DMP_TRANSMIT 4
/* SEL0 */
#define DMC_TYPE_INPUT_MASK 0x0003
#define DMC_IN_IO_MASK 0x0004
#define DMP_IEO_MASK 0x0010
#define DMC_RQI_MASK 0x0020
#define DMP_RQI_MASK 0x0080
#define DMC_RDYI_MASK 0x0080
#define DMC_IEI_MASK 0x0040
#define DMP_IEI_MASK 0x0001
#define LU_LOOP_MASK 0x0800
#define MASTER_CLEAR_MASK 0x4000
#define RUN_MASK 0x8000
/* SEL2 */
#define DMP_IN_IO_MASK 0x0004
#define DMP_TYPE_INPUT_MASK 0x0007
#define TYPE_OUTPUT_MASK 0x0003
#define OUT_IO_MASK 0x0004
#define DMC_RDYO_MASK 0x0080
#define DMC_IEO_MASK 0x0040
#define DMP_RDYI_MASK 0x0010
/* BSEL6 */
#define LOST_DATA_MASK 0x0010
#define DISCONNECT_MASK 0x0040
#define SEL0_RUN_BIT 15
#define SEL0_MCLR_BIT 14
#define SEL0_LU_LOOP_BIT 11
#define SEL0_RDI_BIT 7
#define SEL0_DMC_IEI_BIT 6
#define SEL0_DMP_IEI_BIT 0
#define SEL0_DMP_IEO_BIT 4
#define SEL0_DMC_RQI_BIT 5
#define SEL0_DMP_RQI_BIT 7
#define SEL0_IN_IO_BIT 2
#define SEL0_TYPEI_BIT 0
#define SEL2_TYPEO_BIT 0
#define SEL2_RDO_BIT 7
#define SEL2_IEO_BIT 6
#define SEL2_OUT_IO_BIT 2
#define SEL2_LINE_BIT 8
#define SEL2_LINE_BIT_LENGTH 6
#define SEL2_PRIO_BIT 14
#define SEL2_PRIO_BIT_LENGTH 2
#define SEL6_LOST_DATA_BIT 4
#define SEL6_DISCONNECT_BIT 6
#define BUFFER_QUEUE_SIZE 7
#endif /* _VAX_DMC_H */

108
PDP11/pdp11_dz.c
View File

@ -124,9 +124,26 @@ extern int32 int_req[IPL_HLVL];
#define RBUF_VALID 0100000 /* rcv valid */
#define RBUF_MBZ 0004000
char *dz_charsizes[] = {"5", "6", "7", "8"};
char *dz_baudrates[] = {"50", "75", "110", "134.5", "150", "300", "600", "1200",
"1800", "2000", "2400", "3600", "4800", "7200", "9600", "19200"};
char *dz_parity[] = {"N", "E", "N", "O"};
char *dz_stopbits[] = {"1", "2", "1", "1.5"};
/* DZLPR - 160102 - line parameter register, write only, word access only */
#define LPR_V_LINE 0 /* line */
#define LPR_V_SPEED 8 /* speed code */
#define LPR_M_SPEED 0007400 /* speed code mask */
#define LPR_V_CHARSIZE 3 /* char size code */
#define LPR_M_CHARSIZE 0000030 /* char size code mask */
#define LPR_V_STOPBITS 5 /* stop bits code */
#define LPR_V_PARENB 6 /* parity enable */
#define LPR_V_PARODD 7 /* parity odd */
#define LPR_GETSPD(x) dz_baudrates[((x) & LPR_M_SPEED) >> LPR_V_SPEED]
#define LPR_GETCHARSIZE(x) dz_charsizes[((x) & LPR_M_CHARSIZE) >> LPR_V_CHARSIZE]
#define LPR_GETPARITY(x) dz_parity[(((x) >> LPR_V_PARENB) & 1) | (((x) >> (LPR_V_PARODD-1)) & 2)]
#define LPR_GETSTOPBITS(x) dz_stopbits[(((x) >> LPR_V_STOPBITS) & 1) + (((((x) & LPR_M_CHARSIZE) >> LPR_V_CHARSIZE) == 5) ? 2 : 0)]
#define LPR_LPAR 0007770 /* line pars - NI */
#define LPR_RCVE 0010000 /* receive enb */
#define LPR_GETLN(x) (((x) >> LPR_V_LINE) & DZ_LNOMASK)
@ -170,12 +187,16 @@ TMXR dz_desc = { DZ_MUXES * DZ_LINES, 0, 0, NULL }; /* mux descriptor */
#define DBG_INT 0x0002 /* display transfer requests */
#define DBG_XMT TMXR_DBG_XMT /* display Transmitted Data */
#define DBG_RCV TMXR_DBG_RCV /* display Received Data */
#define DBG_TRC TMXR_DBG_TRC /* display trace routine calls */
#define DBG_ASY TMXR_DBG_ASY /* display Asynchronous Activities */
DEBTAB dz_debug[] = {
{"REG", DBG_REG},
{"INT", DBG_INT},
{"XMT", DBG_XMT},
{"RCV", DBG_RCV},
{"TRC", DBG_TRC},
{"ASY", DBG_ASY},
{0}
};
@ -268,7 +289,7 @@ DEVICE dz_dev = {
1, DEV_RDX, 8, 1, DEV_RDX, 8,
&tmxr_ex, &tmxr_dep, &dz_reset,
NULL, &dz_attach, &dz_detach,
&dz_dib, DEV_FLTA | DEV_DISABLE | DEV_NET | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
&dz_dib, DEV_FLTA | DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG,
0, dz_debug
};
@ -282,6 +303,7 @@ static char *dz_wr_regs[] =
t_stat dz_rd (int32 *data, int32 PA, int32 access)
{
int i;
int32 dz = ((PA - dz_dib.ba) >> 3) & DZ_MNOMASK; /* get mux num */
switch ((PA >> 1) & 03) { /* case on PA<2:1> */
@ -311,6 +333,20 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
break;
case 03: /* MSR */
if (dz_mctl)
for (i=0; i<DZ_LINES; ++i) { /* Gather line status bits for each line */
int line;
int32 modem_bits;
TMLN *lp;
line = (dz * DZ_LINES) + i;
lp = &dz_ldsc[line]; /* get line desc */
tmxr_set_get_modem_bits (lp, 0, 0, &modem_bits);
dz_msr[dz] &= ~((1 << (MSR_V_RI + i)) | (1 << (MSR_V_CD + i)));
dz_msr[dz] |= ((modem_bits&TMXR_MDM_RNG) ? (1 << (MSR_V_RI + i)) : 0) |
((modem_bits&TMXR_MDM_DCD) ? (1 << (MSR_V_CD + i)) : 0);
}
*data = dz_msr[dz];
break;
}
@ -324,6 +360,7 @@ t_stat dz_wr (int32 data, int32 PA, int32 access)
{
int32 dz = ((PA - dz_dib.ba) >> 3) & DZ_MNOMASK; /* get mux num */
int32 i, c, line;
char lineconfig[16];
TMLN *lp;
sim_debug(DBG_REG, &dz_dev, "dz_wr(PA=0x%08X [%s], access=%d, data=0x%X)\n", PA, dz_wr_regs[(PA >> 1) & 03], access, data);
@ -359,6 +396,11 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
if (dz_lpr[dz] & LPR_RCVE) /* rcv enb? on */
lp->rcve = 1;
else lp->rcve = 0; /* else line off */
if (dz_mctl) {
sprintf(lineconfig, "%s-%s%s%s", LPR_GETSPD(data), LPR_GETCHARSIZE(data), LPR_GETPARITY(data), LPR_GETSTOPBITS(data));
if (!lp->serconfig || (0 != strcmp(lp->serconfig, lineconfig))) /* config changed? */
tmxr_set_config_line (lp, lineconfig); /* set it */
}
tmxr_poll_rx (&dz_desc); /* poll input */
dz_update_rcvi (); /* update rx intr */
break;
@ -368,23 +410,20 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
(dz_tcr[dz] & 0377) | (data << 8):
(dz_tcr[dz] & ~0377) | data;
if (dz_mctl) { /* modem ctl? */
dz_msr[dz] |= ((data & 0177400) & /* dcd |= dtr & ring */
((dz_msr[dz] & DZ_LMASK) << MSR_V_CD));
dz_msr[dz] &= ~(data >> TCR_V_DTR); /* ring &= ~dtr */
if (dz_auto) { /* auto disconnect? */
int32 drop;
drop = (dz_tcr[dz] & ~data) >> TCR_V_DTR; /* drop = dtr & ~data */
for (i = 0; i < DZ_LINES; i++) { /* drop hangups */
line = (dz * DZ_LINES) + i; /* get line num */
lp = &dz_ldsc[line]; /* get line desc */
if (lp->conn && (drop & (1 << i))) {
tmxr_linemsg (lp, "\r\nLine hangup\r\n");
tmxr_reset_ln (lp); /* reset line, cdet */
dz_msr[dz] &= ~(1 << (i + MSR_V_CD));
} /* end if drop */
} /* end for */
} /* end if auto */
} /* end if modem */
int32 changed = data ^ dz_tcr[dz];
for (i = 0; i < DZ_LINES; i++) {
if (0 == (changed & (1 << (TCR_V_DTR + i))))
continue; /* line unchanged skip */
line = (dz * DZ_LINES) + i; /* get line num */
lp = &dz_ldsc[line]; /* get line desc */
if (data & (1 << (TCR_V_DTR + i)))
tmxr_set_get_modem_bits (lp, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL);
else
if (dz_auto)
tmxr_set_get_modem_bits (lp, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL);
}
}
dz_tcr[dz] = data;
tmxr_poll_tx (&dz_desc); /* poll output */
dz_update_xmti (); /* update int */
@ -424,7 +463,7 @@ return SCPE_OK;
t_stat dz_svc (UNIT *uptr)
{
int32 dz, t, newln;
int32 dz, t, newln, muxln;
for (dz = t = 0; dz < dz_desc.lines/DZ_LINES; dz++) /* check enabled */
t = t | (dz_csr[dz] & CSR_MSE);
@ -432,9 +471,10 @@ if (t) { /* any enabled? */
newln = tmxr_poll_conn (&dz_desc); /* poll connect */
if ((newln >= 0) && dz_mctl) { /* got a live one? */
dz = newln / DZ_LINES; /* get mux num */
if (dz_tcr[dz] & (1 << (newln + TCR_V_DTR))) /* DTR set? */
dz_msr[dz] |= (1 << (newln + MSR_V_CD)); /* set cdet */
else dz_msr[dz] |= (1 << newln); /* set ring */
muxln = newln % DZ_LINES; /* get line in mux */
if (dz_tcr[dz] & (1 << (muxln + TCR_V_DTR))) /* DTR set? */
dz_msr[dz] |= (1 << (muxln + MSR_V_CD)); /* set cdet */
else dz_msr[dz] |= (1 << (muxln + MSR_V_RI)); /* set ring */
}
tmxr_poll_rx (&dz_desc); /* poll input */
dz_update_rcvi (); /* upd rcv intr */
@ -630,13 +670,17 @@ return auto_config (dptr->name, ndev); /* auto config */
t_stat dz_attach (UNIT *uptr, char *cptr)
{
int32 dz, muxln;
t_stat r;
extern int32 sim_switches;
dz_mctl = dz_auto = 0; /* modem ctl off */
if (sim_switches & SWMASK ('M')) /* modem control? */
tmxr_set_modem_control_passthru (&dz_desc);
r = tmxr_attach (&dz_desc, uptr, cptr); /* attach mux */
if (r != SCPE_OK) /* error? */
if (r != SCPE_OK) { /* error? */
tmxr_clear_modem_control_passthru (&dz_desc);
return r;
}
if (sim_switches & SWMASK ('M')) { /* modem control? */
dz_mctl = 1;
printf ("Modem control activated\n");
@ -649,6 +693,18 @@ if (sim_switches & SWMASK ('M')) { /* modem control? */
fprintf (sim_log, "Auto disconnect activated\n");
}
}
for (dz = 0; dz < DZ_MUXES; dz++) {
if (!dz_mctl || (0 == (dz_csr[dz] & CSR_MSE))) /* enabled? */
continue;
for (muxln = 0; muxln < DZ_LINES; muxln++) {
if (dz_tcr[dz] & (1 << (muxln + TCR_V_DTR))) {
TMLN *lp = &dz_ldsc[(dz * DZ_LINES) + muxln];
tmxr_set_get_modem_bits (lp, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL);
}
}
}
return SCPE_OK;
}
@ -656,6 +712,7 @@ return SCPE_OK;
t_stat dz_detach (UNIT *uptr)
{
dz_mctl = dz_auto = 0; /* modem ctl off */
return tmxr_detach (&dz_desc, uptr);
}
@ -663,7 +720,7 @@ return tmxr_detach (&dz_desc, uptr);
t_stat dz_setnl (UNIT *uptr, int32 val, char *cptr, void *desc)
{
int32 newln, i, t, ndev;
int32 newln, i, t;
t_stat r;
if (cptr == NULL)
@ -690,7 +747,6 @@ if (newln < dz_desc.lines) {
dz_dib.lnt = (newln / DZ_LINES) * IOLN_DZ; /* set length */
dz_desc.lines = newln;
dz_desc.ldsc = dz_ldsc = realloc(dz_ldsc, dz_desc.lines*sizeof(*dz_ldsc));
ndev = ((dz_dev.flags & DEV_DIS)? 0: (dz_desc.lines / DZ_LINES));
return dz_reset (&dz_dev); /* setup lines and auto config */
}

9
PDP11/pdp11_hk.c
View File

@ -772,11 +772,9 @@ return SCPE_OK;
t_stat hk_wr (int32 data, int32 PA, int32 access)
{
int32 drv, i, j, old_val, new_val;
UNIT *uptr;
int32 drv, i, j, old_val = 0, new_val = 0;
drv = GET_UNIT (hkcs2); /* get current unit */
uptr = hk_dev.units + drv; /* get unit */
j = (PA >> 1) & 017; /* get reg offset */
if ((hkcs1 & CS1_GO) && /* busy? */
!(((j == 0) && (data & CS1_CCLR)) || /* not cclr or sclr? */
@ -1245,9 +1243,10 @@ if (old_hkcs1 != hkcs1)
sim_debug_bits (HKDEB_OPS, &hk_dev, hk_cs1_bits, old_hkcs1, hkcs1, 1);
if (old_hkcs2 != hkcs2)
sim_debug_bits (HKDEB_OPS, &hk_dev, hk_cs2_bits, old_hkcs2, hkcs2, 1);
if (flag & CS1_DONE) /* set done */
if (flag & CS1_DONE) { /* set done */
sim_debug (HKDEB_OPS, &hk_dev, ">>HK%d done: fnc=%s, cs1=%o, cs2=%o, ds=%o, er=%o, cyl=%o, da=%o, ba=%o, wc=%o\n",
drv, hk_funcs[GET_FNC (hkcs1)], hkcs1, hkcs2, hkds[drv], hker[drv], hkdc, hkda, hkba, hkwc);
}
return;
}
@ -1552,7 +1551,7 @@ static const uint16 boot_rom[] = {
t_stat hk_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
for (i = 0; i < BOOT_LEN; i++)

4
PDP11/pdp11_io_lib.c
View File

@ -352,7 +352,7 @@ AUTO_CON auto_tab[] = {
{ { NULL }, 1, 2, 8, 8 }, /* DU11 */
{ { NULL }, 1, 2, 8, 8 }, /* DUP11 */
{ { NULL }, 10, 2, 8, 8 }, /* LK11A */
{ { NULL }, 1, 2, 8, 8 }, /* DMC11 */
{ { "DMA", "DMB", "DMC", "DMD" }, 1, 2, 8, 8 }, /* DMC11 */
{ { "DZ" }, DZ_MUXES, 2, 8, 8 }, /* DZ11 */
{ { NULL }, 1, 2, 8, 8 }, /* KMC11 */
{ { NULL }, 1, 2, 8, 8 }, /* LPP11 */
@ -369,7 +369,7 @@ AUTO_CON auto_tab[] = {
{ { "RX", "RY" }, 1, 1, 8, 4, {IOBA_RX} , {VEC_RX} }, /* RX11/RX211 */
{ { NULL }, 1, 1, 8, 4 }, /* DR11W */
{ { NULL }, 1, 1, 8, 4, { 0, 0 }, { 0 } }, /* DR11B - fx CSRs,vec */
{ { NULL }, 1, 2, 8, 8 }, /* DMP11 */
{ { "DMP" }, 1, 2, 8, 8 }, /* DMP11 */
{ { NULL }, 1, 2, 8, 8 }, /* DPV11 */
{ { NULL }, 1, 2, 8, 8 }, /* ISB11 */
{ { NULL }, 1, 2, 16, 8 }, /* DMV11 */

2
PDP11/pdp11_rc.c
View File

@ -437,7 +437,7 @@ static uint32 sectorCRC (const uint16 *data)
static t_stat rc_svc (UNIT *uptr)
{
uint32 ma, da, t, u_old, u_new, last_da;
uint32 ma, da, t, u_old, u_new, last_da = 0;
uint16 dat;
uint16 *fbuf = uptr->filebuf;

4
PDP11/pdp11_rf.c
View File

@ -144,7 +144,7 @@ uint32 update_rfcs (uint32 newcs, uint32 newdae);
DIB rf_dib = {
IOBA_RF, IOLN_RF, &rf_rd, &rf_wr,
1, IVCL (RF), VEC_RF, NULL
1, IVCL (RF), VEC_RF, {NULL}
};
@ -461,7 +461,7 @@ static const uint16 boot_rom[] = {
t_stat rf_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
for (i = 0; i < BOOT_LEN; i++)

2
PDP11/pdp11_rk.c
View File

@ -746,7 +746,7 @@ static const uint16 boot_rom[] = {
t_stat rk_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
for (i = 0; i < BOOT_LEN; i++)

2
PDP11/pdp11_rl.c
View File

@ -1187,7 +1187,7 @@ static const uint16 boot_rom[] = {
t_stat rl_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern uint16 *M;
extern int32 saved_PC;

2
PDP11/pdp11_rp.c
View File

@ -1459,7 +1459,7 @@ static const uint16 boot_rom[] = {
t_stat rp_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
extern uint16 *M;
UNIT *uptr = dptr->units + unitno;

2
PDP11/pdp11_rq.c
View File

@ -2917,7 +2917,7 @@ static const uint16 boot_rom[] = {
t_stat rq_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
extern uint16 *M;
DIB *dibp = (DIB *) dptr->ctxt;

2
PDP11/pdp11_rx.c
View File

@ -522,7 +522,7 @@ static const uint16 boot_rom[] = {
t_stat rx_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
extern uint16 *M;

2
PDP11/pdp11_ry.c
View File

@ -678,7 +678,7 @@ static const uint16 boot_rom[] = {
t_stat ry_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
extern uint16 *M;

5
PDP11/pdp11_sys.c
View File

@ -102,6 +102,7 @@ extern DEVICE xq_dev, xqb_dev;
extern DEVICE xu_dev, xub_dev;
extern DEVICE ke_dev;
extern DEVICE kg_dev;
extern DEVICE dmc_dev[];
extern UNIT cpu_unit;
extern REG cpu_reg[];
extern uint16 *M;
@ -166,6 +167,10 @@ DEVICE *sim_devices[] = {
&xub_dev,
&ke_dev,
&kg_dev,
&dmc_dev[0],
&dmc_dev[1],
&dmc_dev[2],
&dmc_dev[3],
NULL
};

4
PDP11/pdp11_tc.c
View File

@ -749,7 +749,7 @@ t_bool dt_setpos (UNIT *uptr)
{
uint32 new_time, ut, ulin, udelt;
int32 mot = DTS_GETMOT (uptr->STATE);
int32 unum, delta;
int32 unum, delta = 0;
new_time = sim_grtime (); /* current time */
ut = new_time - uptr->LASTT; /* elapsed time */
@ -1183,7 +1183,7 @@ static const uint16 boot_rom[] = {
t_stat dt_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
dt_unit[unitno].pos = DT_EZLIN;

2
PDP11/pdp11_tm.c
View File

@ -711,7 +711,7 @@ static const uint16 boot2_rom[] = {
t_stat tm_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
extern int32 sim_switches;

4
PDP11/pdp11_tq.c
View File

@ -1691,7 +1691,7 @@ return tq_putpkt (pkt, TRUE);
t_bool tq_plf (uint32 err)
{
int32 pkt;
int32 pkt = 0;
if (!tq_deqf (&pkt)) /* get log pkt */
return ERR;
@ -2202,7 +2202,7 @@ static const uint16 boot_rom[] = {
t_stat tq_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
extern uint16 *M;

2
PDP11/pdp11_ts.c
View File

@ -1150,7 +1150,7 @@ static const uint16 boot_rom[] = {
t_stat ts_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
extern uint16 *M;

4
PDP11/pdp11_tu.c
View File

@ -793,7 +793,7 @@ if (DEBUG_PRS (tu_dev)) {
fprintf (sim_deb, ">>TU%d DONE: fnc=%s, fc=%06o, fs=%06o, er=%06o, pos=",
drv, tu_fname[fnc], tufc, tufs, tuer);
fprint_val (sim_deb, uptr->pos, 10, T_ADDR_W, PV_LEFT);
fprintf (sim_deb, "\n");
fprintf (sim_deb, ", r=%d\n", r);
}
return SCPE_OK;
}
@ -1036,7 +1036,7 @@ static const uint16 boot_rom[] = {
t_stat tu_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
extern uint16 *M;

9
PDP11/pdp11_vh.c
View File

@ -34,6 +34,7 @@
of lines available to be 8, 16, 24, or 32.
Fixed performance issue avoiding redundant polling
03-Jan-10 JAD Eliminate gcc warnings
24-Nov-08 JDB Removed tmxr_send_buffered_data declaration (now in sim_tmxr.h)
19-Nov-08 RMS Revised for common TMXR show routines
18-Jun-07 RMS Added UNIT_IDLE flag
29-Oct-06 RMS Synced poll and clock
@ -304,12 +305,16 @@ static TMLX vh_parm[VH_MUXES * VH_LINES_ALLOC] = { { 0 } };
#define DBG_INT 0x0002 /* display transfer requests */
#define DBG_XMT TMXR_DBG_XMT /* display Transmitted Data */
#define DBG_RCV TMXR_DBG_RCV /* display Received Data */
#define DBG_TRC TMXR_DBG_TRC /* display trace routine calls */
#define DBG_ASY TMXR_DBG_ASY /* display Asynchronous Activities */
DEBTAB vh_debug[] = {
{"REG", DBG_REG},
{"INT", DBG_INT},
{"XMT", DBG_XMT},
{"RCV", DBG_RCV},
{"TRC", DBG_TRC},
{"ASY", DBG_ASY},
{0}
};
@ -335,8 +340,6 @@ static t_stat vh_set_log (UNIT *uptr, int32 val, char *cptr, void *desc);
static t_stat vh_set_nolog (UNIT *uptr, int32 val, char *cptr, void *desc);
static t_stat vh_show_log (FILE *st, UNIT *uptr, int32 val, void *desc);
int32 tmxr_send_buffered_data (TMLN *lp);
/* SIMH I/O Structures */
static DIB vh_dib = {
@ -421,7 +424,7 @@ DEVICE vh_dev = {
&vh_attach, /* attach routine */
&vh_detach, /* detach routine */
(void *)&vh_dib,/* context */
DEV_FLTA | DEV_DISABLE | DEV_DIS |DEV_NET | DEV_QBUS | DEV_UBUS | DEV_DEBUG, /* flags */
DEV_FLTA | DEV_DISABLE | DEV_DIS | DEV_QBUS | DEV_UBUS | DEV_DEBUG, /* flags */
0, vh_debug
};

14
PDP11/pdp11_xq.c
View File

@ -1101,7 +1101,6 @@ t_stat xq_process_rbdl(CTLR* xq)
t_stat xq_process_mop(CTLR* xq)
{
uint32 address;
uint16 size;
int32 wstatus;
struct xq_meb* meb = (struct xq_meb*) &xq->var->write_buffer.msg[0200];
const struct xq_meb* limit = (struct xq_meb*) &xq->var->write_buffer.msg[0400];
@ -1113,7 +1112,6 @@ t_stat xq_process_mop(CTLR* xq)
while ((meb->type != 0) && (meb < limit)) {
address = (meb->add_hi << 16) || (meb->add_mi << 8) || meb->add_lo;
size = (meb->siz_hi << 8) || meb->siz_lo;
/* MOP stuff here - NOT YET FULLY IMPLEMENTED */
sim_debug (DBG_WRN, xq->dev, "Processing MEB type: %d\n", meb->type);
@ -1634,8 +1632,9 @@ t_stat xq_process_turbo_rbdl(CTLR* xq)
ethq_remove(&xq->var->ReadQ);
} while (0 == (xq->var->rring[xq->var->rbindx].rmd3 & XQ_RMD3_OWN));
if (xq->var->rring[xq->var->rbindx].rmd3 & XQ_RMD3_OWN)
if (xq->var->rring[xq->var->rbindx].rmd3 & XQ_RMD3_OWN) {
sim_debug(DBG_WRN, xq->dev, "xq_process_turbo_rbdl() - receive ring full\n");
}
if (descriptors_consumed)
/* Interrupt for Packet Reception Completion */
@ -2019,7 +2018,8 @@ t_stat xq_process_bootrom (CTLR* xq)
uint16 b_length, w_length;
uint32 address;
uint8* bootrom = (uint8*) xq_bootrom;
int i, checksum;
size_t i;
int checksum;
sim_debug(DBG_TRC, xq->dev, "xq_process_bootrom()\n");
@ -2645,7 +2645,7 @@ t_stat xq_tmrsvc(UNIT* uptr)
/* has sanity timer expired? if so, reboot */
if (xq->var->sanity.enabled)
if (--xq->var->sanity.timer <= 0)
if (--xq->var->sanity.timer <= 0) {
if (xq->var->mode != XQ_T_DELQA_PLUS)
return xq_boot_host(xq);
else { /* DELQA-T Host Inactivity Timer expiration means switch out of DELQA-T mode */
@ -2654,6 +2654,7 @@ t_stat xq_tmrsvc(UNIT* uptr)
xq->var->iba = xq->var->srr = 0;
xq->var->var = XQ_VEC_MS | XQ_VEC_OS;
}
}
/* has system id timer expired? if so, do system id */
if (--xq->var->idtmr <= 0) {
@ -2895,8 +2896,9 @@ void xq_debug_setup(CTLR* xq)
if (!(sim_deb && (xq->dev->dctrl & DBG_SET)))
return;
if (xq->var->write_buffer.msg[0])
if (xq->var->write_buffer.msg[0]) {
sim_debug(DBG_SET, xq->dev, "%s: setup> MOP info present!\n", xq->dev->name);
}
for (i = 0; i < XQ_FILTER_MAX; i++) {
eth_mac_fmt(&xq->var->setup.macs[i], buffer);

22
PDP11/pdp11_xu.c
View File

@ -674,18 +674,16 @@ t_stat xu_sw_reset (CTLR* xu)
for (i=0; i<6; i++)
xu->var->setup.macs[1][i] = 0xff; /* Broadcast Address */
xu->var->setup.mac_count = 2;
if (xu->var->etherface)
if (xu->var->etherface) {
eth_filter (xu->var->etherface, xu->var->setup.mac_count,
xu->var->setup.macs, xu->var->setup.multicast,
xu->var->setup.promiscuous);
/* activate device if not disabled */
if ((xu->dev->flags & DEV_DIS) == 0) {
/* activate device */
sim_activate_abs(&xu->unit[0], clk_cosched (tmxr_poll));
/* start service timer */
if (xu->var->etherface)
sim_activate_abs(&xu->unit[1], tmr_poll * clk_tps);
sim_activate_abs(&xu->unit[1], tmr_poll * clk_tps);
}
/* clear load_server address */
@ -1033,7 +1031,7 @@ int32 xu_command(CTLR* xu)
void xu_process_receive(CTLR* xu)
{
uint32 segb, ba;
int slen, wlen, off;
int slen, wlen, off = 0;
t_stat rstatus, wstatus;
ETH_ITEM* item = 0;
int state = xu->var->pcsr1 & PCSR1_STATE;
@ -1215,6 +1213,7 @@ void xu_process_transmit(CTLR* xu)
sim_debug(DBG_TRC, xu->dev, "xu_process_transmit()\n");
/* xu_dump_txring(xu); *//* debug receive ring */
off = giant = runt = 0;
for (;;) {
/* get next transmit buffer */
@ -1481,8 +1480,9 @@ t_stat xu_rd(int32 *data, int32 PA, int32 access)
break;
}
sim_debug(DBG_REG, xu->dev, "xu_rd(), PCSR%d, data=%04x\n", reg, *data);
if (PA & 1)
if (PA & 1) {
sim_debug(DBG_WRN, xu->dev, "xu_rd(), Unexpected Odd address access of PCSR%d\n", reg);
}
return SCPE_OK;
}
@ -1622,6 +1622,8 @@ t_stat xu_detach(UNIT* uptr)
sim_debug(DBG_TRC, xu->dev, "xu_detach()\n");
if (uptr->flags & UNIT_ATT) {
sim_cancel (uptr); /* stop the receiver */
sim_cancel (uptr+1); /* stop the timer services */
eth_close (xu->var->etherface);
free(xu->var->etherface);
xu->var->etherface = 0;
@ -1684,7 +1686,8 @@ void xu_dump_rxring (CTLR* xu)
int own = (rxhdr[2] & RXR_OWN) >> 15;
int len = rxhdr[0];
uint32 addr = rxhdr[1] + ((rxhdr[2] & 3) << 16);
printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", i, own, len, addr, rxhdr[0], rxhdr[1], rxhdr[2], rxhdr[3]);
if (rstatus == 0)
printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", i, own, len, addr, rxhdr[0], rxhdr[1], rxhdr[2], rxhdr[3]);
}
}
@ -1700,6 +1703,7 @@ void xu_dump_txring (CTLR* xu)
int own = (txhdr[2] & RXR_OWN) >> 15;
int len = txhdr[0];
uint32 addr = txhdr[1] + ((txhdr[2] & 3) << 16);
printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", i, own, len, addr, txhdr[0], txhdr[1], txhdr[2], txhdr[3]);
if (tstatus == 0)
printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", i, own, len, addr, txhdr[0], txhdr[1], txhdr[2], txhdr[3]);
}
}

2
PDP18B/pdp18b_drm.c
View File

@ -244,7 +244,7 @@ static const int32 boot_rom[] = {
t_stat drm_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 PC;
if (drm_dib.dev != DEV_DRM) /* non-std addr? */

6
PDP18B/pdp18b_stddev.c
View File

@ -453,7 +453,6 @@ int32 clk_task_upd (t_bool clr)
{
uint32 delta, val, iusec10;
uint32 cur = sim_grtime ();
uint32 old = clk_task_timer;
double usec10;
if (cur > clk_task_last)
@ -861,7 +860,8 @@ static const int32 boot_rom[] = {
t_stat ptr_boot (int32 unitno, DEVICE *dptr)
{
int32 i, mask, wd;
size_t i;
int32 mask, wd;
extern int32 sim_switches;
#if defined (PDP7)
@ -994,7 +994,7 @@ if (pulse & 001) { /* KSF */
}
if (pulse & 002) { /* KRS/KRB */
CLR_INT (TTI); /* clear flag */
dat = dat | tti_unit.buf & TTI_MASK; /* return buffer */
dat = dat | (tti_unit.buf & TTI_MASK); /* return buffer */
#if defined (PDP15)
if (pulse & 020) /* KRS? */
tti_fdpx = 1;

2
PDP18B/pdp18b_tt1.c
View File

@ -57,7 +57,7 @@ uint32 ttix_done = 0; /* input flags */
uint32 ttox_done = 0; /* output flags */
uint8 ttix_buf[TTX_MAXL] = { 0 }; /* input buffers */
uint8 ttox_buf[TTX_MAXL] = { 0 }; /* output buffers */
TMLN ttx_ldsc[TTX_MAXL] = { 0 }; /* line descriptors */
TMLN ttx_ldsc[TTX_MAXL] = { {0} }; /* line descriptors */
TMXR ttx_desc = { 1, 0, 0, ttx_ldsc }; /* mux descriptor */
#define ttx_lines ttx_desc.lines /* current number of lines */

2
PDP8/pdp8_df.c
View File

@ -334,7 +334,7 @@ static const uint16 dm4_rom[] = {
t_stat df_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 sim_switches, saved_PC;
if (sim_switches & SWMASK ('D')) {

2
PDP8/pdp8_dt.c
View File

@ -1178,7 +1178,7 @@ static const uint16 boot_rom[] = {
t_stat dt_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
if (unitno) /* only unit 0 */

2
PDP8/pdp8_pt.c
View File

@ -278,7 +278,7 @@ static const uint16 boot_rom[] = {
t_stat ptr_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
extern uint16 M[];

2
PDP8/pdp8_rf.c
View File

@ -398,7 +398,7 @@ static const uint16 dm4_rom[] = {
t_stat rf_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 sim_switches, saved_PC;
if (rf_dib.dev != DEV_RF) /* only std devno */

2
PDP8/pdp8_rk.c
View File

@ -450,7 +450,7 @@ static const uint16 boot_rom[] = {
t_stat rk_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
if (rk_dib.dev != DEV_RK) /* only std devno */

2
PDP8/pdp8_rl.c
View File

@ -689,7 +689,7 @@ static const uint16 boot_rom[] = {
t_stat rl_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
if (unitno) /* only unit 0 */

2
PDP8/pdp8_rx.c
View File

@ -733,7 +733,7 @@ static const uint16 boot2_rom[] = {
t_stat rx_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
extern uint16 M[];

2
PDP8/pdp8_td.c
View File

@ -742,7 +742,7 @@ static const uint16 boot_rom[] = {
t_stat td_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
size_t i;
extern int32 saved_PC;
if (unitno)

2
PDP8/pdp8_ttx.c
View File

@ -66,7 +66,7 @@ extern int32 tmxr_poll, sim_is_running;
uint8 ttix_buf[TTX_LINES] = { 0 }; /* input buffers */
uint8 ttox_buf[TTX_LINES] = { 0 }; /* output buffers */
int32 ttx_tps = 100; /* polls per second */
TMLN ttx_ldsc[TTX_LINES] = { 0 }; /* line descriptors */
TMLN ttx_ldsc[TTX_LINES] = { {0} }; /* line descriptors */
TMXR ttx_desc = { TTX_LINES, 0, 0, ttx_ldsc }; /* mux descriptor */
DEVICE ttix_dev, ttox_dev;

3
S3/s3_sys.c
View File

@ -270,13 +270,12 @@ int32 fprint_sym (FILE *of, int32 addr, uint32 *val,
int32 printf_sym (FILE *of, char *strg, int32 addr, uint32 *val,
UNIT *uptr, int32 sw)
{
int32 cflag, c1, c2, group, len1, len2, inst, aaddr, baddr;
int32 c1, c2, group, len1, len2, inst, aaddr, baddr;
int32 oplen, groupno, i, j, vpos, qbyte, da, m, n;
char bld[128], bldaddr[32], boperand[32], aoperand[32];
int32 blk[16], blt[16];
int32 blkadd;
cflag = (uptr == NULL) || (uptr == &cpu_unit);
c1 = val[0] & 0xff;
if (sw & SWMASK ('A')) {
for (i = 0; i < 16; i++) {

2
SDS/sds_cpu.c
View File

@ -1341,7 +1341,7 @@ if (sc >= 24) {
A = sgn;
}
else {
B = ((B >> sc) | (A << (24 - sc)) & DMASK);
B = ((B >> sc) | (A << (24 - sc))) & DMASK;
A = ((A >> sc) | (sgn << (24 - sc))) & DMASK;
}
return;

2
SDS/sds_io.c
View File

@ -224,7 +224,7 @@ uint32 dev_map[64][NUM_CHAN];
/* dev_dsp maps device and channel numbers to dispatch routines */
t_stat (*dev_dsp[64][NUM_CHAN])() = { NULL };
t_stat (*dev_dsp[64][NUM_CHAN])() = { {NULL} };
/* dev3_dsp maps system device numbers to dispatch routines */

2
SDS/sds_mux.c
View File

@ -112,7 +112,7 @@ uint32 mux_tps = 100; /* polls/second */
uint32 mux_scan = 0; /* scanner */
uint32 mux_slck = 0; /* scanner locked */
TMLN mux_ldsc[MUX_LINES] = { 0 }; /* line descriptors */
TMLN mux_ldsc[MUX_LINES] = { {0} }; /* line descriptors */
TMXR mux_desc = { MUX_LINES, 0, 0, mux_ldsc }; /* mux descriptor */
t_stat mux (uint32 fnc, uint32 inst, uint32 *dat);

4
VAX/vax610_mem.c
View File

@ -57,7 +57,7 @@ DIB mctl_dib = {
1, 0, 0, { NULL }
};
UNIT mctl_unit[] = { UDATA (NULL, 0, 0) };
UNIT mctl_unit = { UDATA (NULL, 0, 0) };
REG mctl_reg[] = {
{ DRDATA (COUNT, mctl_count, 16) },
@ -66,7 +66,7 @@ REG mctl_reg[] = {
};
DEVICE mctl_dev = {
"MCTL", mctl_unit, mctl_reg, NULL,
"MCTL", &mctl_unit, mctl_reg, NULL,
1, DEV_RDX, 20, 1, DEV_RDX, 8,
NULL, NULL, &mctl_reset,
NULL, NULL, NULL,

1
VAX/vax630_sysdev.c
View File

@ -831,7 +831,6 @@ return run_cmd (flag, "CPU");
t_stat cpu_boot (int32 unitno, DEVICE *dptr)
{
extern t_stat load_cmd (int32 flag, char *cptr);
extern FILE *sim_log;
t_stat r;
PC = ROMBASE;

2
VAX/vax730_mem.c
View File

@ -83,7 +83,7 @@ t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
mctlx_reg MCTLx register list
*/
DIB mctl_dib[] = { TR_MCTL, 0, &mctl_rdreg, &mctl_wrreg, 0 };
DIB mctl_dib = { TR_MCTL, 0, &mctl_rdreg, &mctl_wrreg, 0 };
UNIT mctl_unit = { UDATA (NULL, 0, 0) };

2
VAX/vax730_rb.c
View File

@ -490,7 +490,7 @@ if (func == RBCS_SEEK) { /* seek? */
if (uptr->SIP == 0) {
sim_debug(DBG_CMD, &rb_dev, "Seek, CYL=%d, TRK=%d, SECT=%d\n", GET_CYL(rbda), GET_TRACK(rbda), GET_SECT(rbda));
uptr->SIP = 1;
if (rbda == 0xFFFFFFFF) swait = rb_swait;
if ((uint32)rbda == 0xFFFFFFFF) swait = rb_swait;
else {
curr = GET_CYL (uptr->TRK); /* current cylinder */
newc = GET_CYL (rbda); /* offset */

2
VAX/vax750_mem.c
View File

@ -95,7 +95,7 @@ t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
mctl_reg MCTL register list
*/
DIB mctl_dib[] = { TR_MCTL, 0, &mctl_rdreg, &mctl_wrreg, 0 };
DIB mctl_dib = { TR_MCTL, 0, &mctl_rdreg, &mctl_wrreg, 0 };
UNIT mctl_unit = { UDATA (NULL, 0, 0) };

10
VAX/vax780_defs.h
View File

@ -319,6 +319,8 @@ typedef struct {
#define IOLN_PTR 004
#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */
#define IOLN_PTP 004
#define IOBA_DMC (IOPAGEBASE + 0760060) /* DMC11 */
#define IOLN_DMC 010
/* Interrupt assignments; within each level, priority is right to left */
@ -331,6 +333,8 @@ typedef struct {
#define INT_V_TS 6
#define INT_V_RY 7
#define INT_V_XU 8
#define INT_V_DMCRX 9
#define INT_V_DMCTX 10
#define INT_V_LPT 0 /* BR4 */
#define INT_V_PTR 1
@ -354,6 +358,8 @@ typedef struct {
#define INT_PTR (1u << INT_V_PTR)
#define INT_PTP (1u << INT_V_PTP)
#define INT_CR (1u << INT_V_CR)
#define INT_DMCRX (1u << INT_V_DMCRX)
#define INT_DMCTX (1u << INT_V_DMCTX)
#define IPL_DZRX (0x15 - IPL_HMIN)
#define IPL_DZTX (0x15 - IPL_HMIN)
@ -370,6 +376,8 @@ typedef struct {
#define IPL_CR (0x14 - IPL_HMIN)
#define IPL_VHRX (0x14 - IPL_HMIN)
#define IPL_VHTX (0x14 - IPL_HMIN)
#define IPL_DMCRX (0x15 - IPL_HMIN)
#define IPL_DMCTX (0x15 - IPL_HMIN)
/* Device vectors */
@ -392,6 +400,8 @@ typedef struct {
#define VEC_DZTX 0304
#define VEC_VHRX 0310
#define VEC_VHTX 0314
#define VEC_DMCRX 0310
#define VEC_DMCTX 0314
/* Interrupt macros */

4
VAX/vax780_mem.c
View File

@ -98,7 +98,7 @@ t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
mctlx_reg MCTLx register list
*/
DIB mctl0_dib[] = { TR_MCTL0, 0, &mctl_rdreg, &mctl_wrreg, 0 };
DIB mctl0_dib = { TR_MCTL0, 0, &mctl_rdreg, &mctl_wrreg, 0 };
UNIT mctl0_unit = { UDATA (NULL, 0, 0) };
@ -117,7 +117,7 @@ MTAB mctl0_mod[] = {
{ 0 }
};
DIB mctl1_dib[] = { TR_MCTL1, 0, &mctl_rdreg, &mctl_wrreg, 0 };
DIB mctl1_dib = { TR_MCTL1, 0, &mctl_rdreg, &mctl_wrreg, 0 };
UNIT mctl1_unit = { UDATA (NULL, 0, 0) };

5
VAX/vax780_syslist.c
View File

@ -54,6 +54,7 @@ extern DEVICE tu_dev;
extern DEVICE dz_dev;
extern DEVICE vh_dev;
extern DEVICE xu_dev, xub_dev;
extern DEVICE dmc_dev[];
extern int32 sim_switches;
extern UNIT cpu_unit;
@ -91,6 +92,10 @@ DEVICE *sim_devices[] = {
&tq_dev,
&xu_dev,
&xub_dev,
&dmc_dev[0],
&dmc_dev[1],
&dmc_dev[2],
&dmc_dev[3],
NULL
};

3
VAX/vax7x0_mba.c
View File

@ -820,8 +820,9 @@ if (mba_sr[mb] != o_sr)
sim_debug_bits(MBA_DEB_RWR, &mba_dev[mb], mba_sr_bits, o_sr, mba_sr[mb], 1);
if ((set & MBASR_INTR) && (mba_cr[mb] & MBACR_IE) && !(mba_sr[mb] & MBASR_DTBUSY))
mba_set_int (mb);
if (set & MBASR_ERRORS)
if (set & MBASR_ERRORS) {
sim_debug (MBA_DEB_ERR, &mba_dev[mb], "mba_upd_sr(CS error=0x%X)\n", mba_sr[mb]);
}
return;
}

4
VAX/vax_cis.c
View File

@ -71,8 +71,8 @@ typedef struct {
uint32 val[DSTRLNT];
} DSTR;
static DSTR Dstr_zero = { 0, 0, 0, 0, 0 };
static DSTR Dstr_one = { 0, 0x10, 0, 0, 0 };
static DSTR Dstr_zero = { 0, {0, 0, 0, 0} };
static DSTR Dstr_one = { 0, {0x10, 0, 0, 0} };
extern int32 R[16];
extern int32 PSL;

4
VAX/vax_cmode.c
View File

@ -597,7 +597,7 @@ switch ((IR >> 12) & 017) { /* decode IR<15:12> */
cc = CC_V | CC_C; /* set cc's */
break; /* done */
}
if ((src == LSIGN) && (src2 == WMASK)) { /* -2^31 / -1? */
if (((uint32)src == LSIGN) && ((uint32)src2 == WMASK)) { /* -2^31 / -1? */
cc = CC_V; /* overflow */
break; /* done */
}
@ -669,7 +669,7 @@ switch ((IR >> 12) & 017) { /* decode IR<15:12> */
dst = ((uint32) src) << src2;
i = ((src >> (32 - src2)) | (-sign << src2)) & LMASK;
oc = (i & 1)? CC_C: 0;
if ((dst & LSIGN)? (i != LMASK): (i != 0))
if ((dst & LSIGN)? ((uint32)i != LMASK): (i != 0))
oc = oc | CC_V;
}
else if (src2 == 32) { /* [32] = -32 */

11
VAX/vax_cpu.c
View File

@ -1941,7 +1941,8 @@ for ( ;; ) {
temp = CC_V;
SET_TRAP (TRAP_DIVZRO);
}
else if ((op0 == LMASK) && (op1 == LSIGN)) { /* overflow? */
else if ((((uint32)op0) == LMASK) &&
(((uint32)op1) == LSIGN)) { /* overflow? */
r = op1;
temp = CC_V;
INTOV;
@ -3205,7 +3206,7 @@ return SCPE_NXM;
t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
{
int32 mc = 0;
uint32 i, clim;
uint32 i, clim, uval = (uint32)val;
uint32 *nM = NULL;
if ((val <= 0) || (val > MAXMEMSIZE_X))
@ -3214,15 +3215,15 @@ for (i = val; i < MEMSIZE; i = i + 4)
mc = mc | M[i >> 2];
if ((mc != 0) && !get_yn ("Really truncate memory [N]?", FALSE))
return SCPE_OK;
nM = (uint32 *) calloc (val >> 2, sizeof (uint32));
nM = (uint32 *) calloc (uval >> 2, sizeof (uint32));
if (nM == NULL)
return SCPE_MEM;
clim = (uint32) ((((uint32) val) < MEMSIZE)? val: MEMSIZE);
clim = (uint32)((uval < MEMSIZE)? uval: MEMSIZE);
for (i = 0; i < clim; i = i + 4)
nM[i >> 2] = M[i >> 2];
free (M);
M = nM;
MEMSIZE = val;
MEMSIZE = uval;
return SCPE_OK;
}

14
VAX/vax_mmu.c
View File

@ -178,7 +178,10 @@ if (mapen) { /* mapping on? */
xpte = fill (va, lnt, acc, NULL); /* fill if needed */
pa = (xpte.pte & TLB_PFN) | off; /* get phys addr */
}
else pa = va & PAMASK;
else {
pa = va & PAMASK;
off = 0;
}
if ((pa & (lnt - 1)) == 0) { /* aligned? */
if (lnt >= L_LONG) /* long, quad? */
return ReadL (pa);
@ -186,7 +189,7 @@ if ((pa & (lnt - 1)) == 0) { /* aligned? */
return ReadW (pa);
return ReadB (pa); /* byte */
}
if (mapen && ((off + lnt) > VA_PAGSIZE)) { /* cross page? */
if (mapen && ((uint32)(off + lnt) > VA_PAGSIZE)) { /* cross page? */
vpn = VA_GETVPN (va + lnt); /* vpn 2nd page */
tbi = VA_GETTBI (vpn);
xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */
@ -240,7 +243,10 @@ if (mapen) {
xpte = fill (va, lnt, acc, NULL);
pa = (xpte.pte & TLB_PFN) | off;
}
else pa = va & PAMASK;
else {
pa = va & PAMASK;
off = 0;
}
if ((pa & (lnt - 1)) == 0) { /* aligned? */
if (lnt >= L_LONG) /* long, quad? */
WriteL (pa, val);
@ -249,7 +255,7 @@ if ((pa & (lnt - 1)) == 0) { /* aligned? */
else WriteB (pa, val); /* byte */
return;
}
if (mapen && ((off + lnt) > VA_PAGSIZE)) {
if (mapen && ((uint32)(off + lnt) > VA_PAGSIZE)) {
vpn = VA_GETVPN (va + 4);
tbi = VA_GETTBI (vpn);
xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */

1
VAX/vax_sysdev.c
View File

@ -1577,7 +1577,6 @@ return run_cmd (flag, "CPU");
t_stat cpu_boot (int32 unitno, DEVICE *dptr)
{
extern t_stat load_cmd (int32 flag, char *cptr);
extern FILE *sim_log;
t_stat r;
PC = ROMBASE;

5
VAX/vax_syslist.c
View File

@ -51,6 +51,7 @@ extern DEVICE dz_dev;
extern DEVICE csi_dev, cso_dev;
extern DEVICE xq_dev, xqb_dev;
extern DEVICE vh_dev;
extern DEVICE dmc_dev[];
extern int32 sim_switches;
extern void WriteB (uint32 pa, int32 val);
@ -83,6 +84,10 @@ DEVICE *sim_devices[] = {
&tq_dev,
&xq_dev,
&xqb_dev,
&dmc_dev[0],
&dmc_dev[1],
&dmc_dev[2],
&dmc_dev[3],
NULL
};

2
VAX/vax_watch.c
View File

@ -97,7 +97,7 @@ int32 wtc_rd (int32 pa)
int32 rg = (pa >> 1) & 0xF;
int32 val = 0;
time_t curr;
struct tm *ctm;
struct tm *ctm = NULL;
if (rg < 10) { /* time reg? */
curr = time (NULL); /* get curr time */

10
VAX/vaxmod_defs.h
View File

@ -327,6 +327,8 @@ typedef struct {
#define IOLN_PTR 004
#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */
#define IOLN_PTP 004
#define IOBA_DMC (IOPAGEBASE + 017060) /* DMC11 */
#define IOLN_DMC 010
/* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
however, DEC Qbus controllers all interrupt on IPL 14
@ -365,6 +367,8 @@ typedef struct {
#define INT_V_VHTX 18
#define INT_V_QDSS 19 /* QDSS */
#define INT_V_CR 20
#define INT_V_DMCRX 21 /* DMC11 */
#define INT_V_DMCTX 22
#define INT_CLK (1u << INT_V_CLK)
#define INT_RQ (1u << INT_V_RQ)
@ -388,6 +392,8 @@ typedef struct {
#define INT_VHTX (1u << INT_V_VHTX)
#define INT_QDSS (1u << INT_V_QDSS)
#define INT_CR (1u << INT_V_CR)
#define INT_DMCRX (1u << INT_V_DMCRX)
#define INT_DMCTX (1u << INT_V_DMCTX)
#define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */
#define IPL_RQ (0x14 - IPL_HMIN)
@ -411,6 +417,8 @@ typedef struct {
#define IPL_VHTX (0x14 - IPL_HMIN)
#define IPL_QDSS (0x14 - IPL_HMIN)
#define IPL_CR (0x14 - IPL_HMIN)
#define IPL_DMCRX (0x14 - IPL_HMIN)
#define IPL_DMCTX (0x14 - IPL_HMIN)
#define IPL_HMAX 0x17 /* highest hwre level */
#define IPL_HMIN 0x14 /* lowest hwre level */
@ -437,6 +445,8 @@ typedef struct {
#define VEC_DZTX (VEC_Q + 0304)
#define VEC_VHRX (VEC_Q + 0310)
#define VEC_VHTX (VEC_Q + 0314)
#define VEC_DMCRX (VEC_Q + 0310)
#define VEC_DMCTX (VEC_Q + 0314)
/* Interrupt macros */

8
Visual Studio Projects/ALTAIR.vcproj
View File

@ -218,6 +218,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -267,6 +271,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

8
Visual Studio Projects/AltairZ80.vcproj
View File

@ -321,6 +321,10 @@
RelativePath="..\AltairZ80\sim_imd.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -378,6 +382,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

2
Visual Studio Projects/BuildROMs.vcproj
View File

@ -50,7 +50,7 @@
UsePrecompiledHeader="0"
WarningLevel="3"
Detect64BitPortabilityProblems="false"
DebugInformationFormat="4"
DebugInformationFormat="3"
/>
<Tool
Name="VCManagedResourceCompilerTool"

8
Visual Studio Projects/ECLIPSE.vcproj
View File

@ -249,6 +249,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -294,6 +298,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

8
Visual Studio Projects/GRI.vcproj
View File

@ -213,6 +213,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -262,6 +266,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

8
Visual Studio Projects/H316.vcproj
View File

@ -229,6 +229,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -278,6 +282,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

8
Visual Studio Projects/HP2100.vcproj
View File

@ -317,6 +317,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -390,6 +394,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

8
Visual Studio Projects/I1401.vcproj
View File

@ -229,6 +229,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -282,6 +286,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

8
Visual Studio Projects/I1620.vcproj
View File

@ -233,6 +233,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -282,6 +286,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

8
Visual Studio Projects/I7094.vcproj
View File

@ -249,6 +249,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -302,6 +306,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

8
Visual Studio Projects/IBM1130.vcproj
View File

@ -253,6 +253,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -326,6 +330,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

8
Visual Studio Projects/ID16.vcproj
View File

@ -261,6 +261,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -310,6 +314,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

8
Visual Studio Projects/ID32.vcproj
View File

@ -261,6 +261,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -310,6 +314,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

8
Visual Studio Projects/NOVA.vcproj
View File

@ -249,6 +249,10 @@
RelativePath="..\sim_fio.c"
>
</File>
<File
RelativePath="..\sim_serial.c"
>
</File>
<File
RelativePath="..\sim_sock.c"
>
@ -298,6 +302,10 @@
RelativePath="..\sim_rev.h"
>
</File>
<File
RelativePath="..\sim_serial.h"
>
</File>
<File
RelativePath="..\sim_sock.h"
>

Some files were not shown because too many files have changed in this diff Show More