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Notes For V3.7-0
1. New Features 1.1 3.7-0 1.1.1 SCP - Added SET THROTTLE and SET NOTHROTTLE commands to regulate simulator execution rate and host resource utilization. - Added idle support (based on work by Mark Pizzolato). - Added -e to control error processing in nested DO commands (from Dave Bryan). 1.1.2 HP2100 - Added Double Integer instructions, 1000-F CPU, and Floating Point Processor (from Dave Bryan). - Added 2114 and 2115 CPUs, 12607B and 12578A DMA controllers, and 21xx binary loader protection (from Dave Bryan). 1.1.3 Interdata - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state. 1.1.4 PDP-11 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (WAIT instruction executed). - Added TA11/TU60 cassette support. 1.1.5 PDP-8 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). - Added TA8E/TU60 cassette support. 1.1.6 PDP-1 - Added support for 16-channel sequence break system. - Added support for PDP-1D extended features and timesharing clock. - Added support for Type 630 data communications subsystem. 1.1.6 PDP-4/7/9/15 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). 1.1.7 VAX, VAX780 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (more than 200 cycles at IPL's 0, 1, or 3 in kernel mode). 1.1.8 PDP-10 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (operating system dependent). - Added CD20 (CD11) support. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
This commit is contained in:
committed by
Mark Pizzolato
parent
15919a2dd7
commit
53d02f7fa7
@@ -25,6 +25,8 @@
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cpu 7094 central processor
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29-Oct-06 RMS Added additional expanded core instructions
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17-Oct-06 RMS Fixed the fix in halt IO wait loop
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16-Jun-06 RMS Fixed bug in halt IO wait loop
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The register state for the 7094 is:
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@@ -1576,11 +1578,22 @@ while (reason == SCPE_OK) { /* loop until error */
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reason = op_mse (ea);
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break;
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case 01761: /* (CTSS) SEA, SEB */
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case 01761: /* (CTSS) ext core */
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if (prot_trap (0)) break; /* user mode? */
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if (ea == 041) data_base = 0;
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else if (ea == 042) data_base = BCORE_BASE;
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else if (stop_illop) reason = STOP_ILLEG;
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if (ea == 041) /* SEA? */
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data_base = 0;
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else if (ea == 042) /* SEB? */
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data_base = BCORE_BASE;
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else if (ea == 043) { /* IFT? */
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if (inst_base == 0)
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PC = (PC + 1) & eamask;
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}
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else if (ea == 044) { /* EFT? */
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if (data_base == 0)
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PC = (PC + 1) & eamask;
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}
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else if (stop_illop)
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reason = STOP_ILLEG;
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break;
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case 01763: /* LGL */
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@@ -1775,7 +1788,7 @@ while (reason == SCPE_OK) { /* loop until error */
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if (r = sim_process_event ()) return r; /* process events */
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chtr_pend = chtr_eval (NULL); /* eval chan traps */
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while (ch_req) { /* until no ch req */
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for (j = 0; i < NUM_CHAN; j++) { /* loop thru channels */
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for (j = 0; j < NUM_CHAN; j++) { /* loop thru channels */
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if (ch_req & REQ_CH (j)) { /* channel request? */
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if (r = ch_proc (j)) return r;
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}
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@@ -23,6 +23,7 @@
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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29-Oct-06 RMS Added additional expanded core instructions
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08-Jun-06 RMS Added Dave Pitts' binary loader
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*/
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@@ -362,6 +363,7 @@ static const char *opcode[] = {
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"TIA", "TIB",
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"LRI", "LPI",
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"SEA", "SEB",
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"IFT", "EFT",
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"IOCD", "IOCDN", "TCH",
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"IORP", "IORPN",
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@@ -523,6 +525,7 @@ static const t_uint64 opc_v[] = {
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0010100000000+I_MXN, 0410100000000+I_MXN,
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0056200000000+I_MXN, 0456400000000+I_MXN,
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0476100000041+I_SNS, 0476100000042+I_SNS,
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0476100000043+I_SNS, 0476100000044+I_SNS,
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01000000000000+I_IOX, 01000000200000+I_IOX, 01100000000000+I_TCH,
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01200000000000+I_IOX, 01200000200000+I_IOX,
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