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Notes For V3.7-0

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1. New Features

1.1 3.7-0

1.1.1 SCP

- Added SET THROTTLE and SET NOTHROTTLE commands to regulate simulator
  execution rate and host resource utilization.
- Added idle support (based on work by Mark Pizzolato).
- Added -e to control error processing in nested DO commands (from
  Dave Bryan).

1.1.2 HP2100

- Added Double Integer instructions, 1000-F CPU, and Floating Point
  Processor (from Dave Bryan).
- Added 2114 and 2115 CPUs, 12607B and 12578A DMA controllers, and
  21xx binary loader protection (from Dave Bryan).

1.1.3 Interdata

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state.

1.1.4 PDP-11

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state (WAIT instruction executed).
- Added TA11/TU60 cassette support.

1.1.5 PDP-8

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state (keyboard poll loop or jump-to-self).
- Added TA8E/TU60 cassette support.

1.1.6 PDP-1

- Added support for 16-channel sequence break system.
- Added support for PDP-1D extended features and timesharing clock.
- Added support for Type 630 data communications subsystem.

1.1.6 PDP-4/7/9/15

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state (keyboard poll loop or jump-to-self).

1.1.7 VAX, VAX780

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state (more than 200 cycles at IPL's 0, 1, or 3 in kernel mode).

1.1.8 PDP-10

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state (operating system dependent).
- Added CD20 (CD11) support.

2. Bugs Fixed

Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.
This commit is contained in:
Bob Supnik
2007-02-03 14:59:00 -08:00
committed by Mark Pizzolato
parent 15919a2dd7
commit 53d02f7fa7
161 changed files with 18604 additions and 6903 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
Interdata/id16_cpu.c
View File

@@ -25,6 +25,8 @@
cpu Interdata 16b CPU
27-Oct-06 RMS Added idle support
Removed separate PASLA clock
06-Feb-06 RMS Fixed bug in DH (found by Mark Hittinger)
22-Sep-05 RMS Fixed declarations (from Sterling Garwood)
25-Aug-05 RMS Fixed DH integer overflow cases
@@ -219,7 +221,8 @@ uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL };
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern UNIT pic_unit, lfc_unit, pas_unit; /* timers */
extern t_bool sim_idle_enab;
extern UNIT pic_unit, lfc_unit; /* timers */
uint32 ReadB (uint32 loc);
uint32 ReadH (uint32 loc);
@@ -445,7 +448,7 @@ static uint32 s1_rel_const[16] = { /* addr 8000-FFFF */
DIB cpu_dib = { d_DS, -1, v_DS, NULL, &display, NULL };
UNIT cpu_unit = {
UDATA (NULL, UNIT_FIX + UNIT_BINK + UNIT_716, MAXMEMSIZE16)
UDATA (NULL, UNIT_FIX | UNIT_BINK | UNIT_716, MAXMEMSIZE16)
};
REG cpu_reg[] = {
@@ -513,6 +516,13 @@ REG cpu_reg[] = {
};
MTAB cpu_mod[] = {
{ UNIT_TYPE, 0, "I3", "I3", &cpu_set_model },
{ UNIT_TYPE, UNIT_ID4, "I4", "I4", &cpu_set_model },
{ UNIT_TYPE, UNIT_716, "7/16", "716", &cpu_set_model },
{ UNIT_TYPE, UNIT_816, "8/16", "816", &cpu_set_model },
{ UNIT_TYPE, UNIT_816E, "8/16E", "816E", &cpu_set_model },
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
{ UNIT_MSIZE, 8192, NULL, "8K", &cpu_set_size },
{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size },
{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size },
@@ -521,11 +531,6 @@ MTAB cpu_mod[] = {
{ UNIT_MSIZE, 65536, NULL, "64K", &cpu_set_size },
{ UNIT_MSIZE, 131072, NULL, "128K", &cpu_set_size },
{ UNIT_MSIZE, 262144, NULL, "256K", &cpu_set_size },
{ UNIT_TYPE, 0, "I3", "I3", &cpu_set_model },
{ UNIT_TYPE, UNIT_ID4, "I4", "I4", &cpu_set_model },
{ UNIT_TYPE, UNIT_716, "7/16", "716", &cpu_set_model },
{ UNIT_TYPE, UNIT_816, "8/16", "816", &cpu_set_model },
{ UNIT_TYPE, UNIT_816E, "8/16E", "816E", &cpu_set_model },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, NULL, "CONSINT",
&cpu_set_consint, NULL, NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
@@ -584,7 +589,6 @@ int_eval (); /* eval interrupts */
cc = newPSW (PSW & psw_mask); /* split PSW, eval wait */
sim_rtcn_init (lfc_unit.wait, TMR_LFC); /* init clock */
sim_rtcn_init (pic_unit.wait, TMR_PIC); /* init timer */
sim_rtcn_init (pas_unit.wait, TMR_PAS); /* init pas */
reason = 0;
/* Process events */
@@ -641,10 +645,9 @@ while (reason == 0) { /* loop until halted */
}
if (PSW & PSW_WAIT) { /* wait state? */
t = sim_qcount (); /* events in queue */
if ((t == 0) || ((t == 1) && stop_wait)) /* empty, or kbd only? */
reason = STOP_WAIT; /* then stop */
else sim_interval = 0; /* force check */
if (sim_idle_enab) /* idling enabled? */
sim_idle (TMR_LFC, TRUE);
else sim_interval = sim_interval - 1; /* no, count cycle */
continue;
}

7
Interdata/id16_sys.c
View File

@@ -1,6 +1,6 @@
/* id16_sys.c: Interdata 16b simulator interface
Copyright (c) 2000-2005, Robert M. Supnik
Copyright (c) 2000-2006, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
18-Oct-06 RMS Re-ordered device list
26-Mar-04 RMS Fixed warning with -std=c99
27-Feb-03 RMS Added relative addressing support
*/
@@ -69,13 +70,13 @@ int32 sim_emax = 2;
DEVICE *sim_devices[] = {
&cpu_dev,
&sch_dev,
&pic_dev,
&lfc_dev,
&pt_dev,
&tt_dev,
&ttp_dev,
&pas_dev,
&pasl_dev,
&pic_dev,
&lfc_dev,
&lpt_dev,
&dp_dev,
&idc_dev,

27
Interdata/id32_cpu.c
View File

@@ -25,7 +25,9 @@
cpu Interdata 32b CPU
09-Mar-06 RMS Added 8 register bank support for 8/32
27-Oct-06 RMS Added idle support
Removed separate PASLA clock
09-Mar-06 RMS Added 8 register bank support for 8/32
06-Feb-06 RMS Fixed bug in DH (found by Mark Hittinger)
22-Sep-05 RMS Fixed declarations (from Sterling Garwood)
16-Aug-05 RMS Fixed C++ declaration and cast problems
@@ -249,7 +251,8 @@ uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL };
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern UNIT pic_unit, lfc_unit, pas_unit; /* timers */
extern t_bool sim_idle_enab;
extern UNIT pic_unit, lfc_unit; /* timers */
extern FILE *sim_deb;
uint32 ReadB (uint32 loc, uint32 rel);
@@ -566,11 +569,6 @@ REG cpu_reg[] = {
};
MTAB cpu_mod[] = {
{ UNIT_MSIZE, 65536, NULL, "64K", &cpu_set_size },
{ UNIT_MSIZE, 131072, NULL, "128K", &cpu_set_size },
{ UNIT_MSIZE, 262144, NULL, "256K", &cpu_set_size },
{ UNIT_MSIZE, 524288, NULL, "512K", &cpu_set_size },
{ UNIT_MSIZE, 1048756, NULL, "1M", &cpu_set_size },
{ UNIT_8RS|UNIT_TYPE, 0, NULL, "732", NULL },
{ UNIT_DPFP, UNIT_DPFP, NULL, "DPFP", NULL },
{ UNIT_TYPE, 0, "7/32, single precision fp", "732", NULL },
@@ -579,6 +577,13 @@ MTAB cpu_mod[] = {
{ UNIT_8RS, 0, NULL, "2RS", NULL },
{ UNIT_8RS|UNIT_TYPE, UNIT_8RS|UNIT_DPFP|UNIT_832, "832, 8 register sets", NULL, NULL },
{ UNIT_8RS|UNIT_TYPE, UNIT_DPFP|UNIT_832, "832, 2 register sets", NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
{ UNIT_MSIZE, 65536, NULL, "64K", &cpu_set_size },
{ UNIT_MSIZE, 131072, NULL, "128K", &cpu_set_size },
{ UNIT_MSIZE, 262144, NULL, "256K", &cpu_set_size },
{ UNIT_MSIZE, 524288, NULL, "512K", &cpu_set_size },
{ UNIT_MSIZE, 1048756, NULL, "1M", &cpu_set_size },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, NULL, "CONSINT",
&cpu_set_consint, NULL, NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
@@ -624,7 +629,6 @@ int_eval (); /* eval interrupts */
cc = newPSW (PSW & PSW_MASK); /* split PSW, eval wait */
sim_rtcn_init (lfc_unit.wait, TMR_LFC); /* init clock */
sim_rtcn_init (pic_unit.wait, TMR_PIC); /* init timer */
sim_rtcn_init (pas_unit.wait, TMR_PAS); /* init pas */
reason = 0;
/* Abort handling
@@ -703,10 +707,9 @@ while (reason == 0) { /* loop until halted */
}
if (PSW & PSW_WAIT) { /* wait state? */
t = sim_qcount (); /* events in queue */
if ((t == 0) || ((t == 1) && stop_wait)) /* empty, or kbd only? */
reason = STOP_WAIT; /* then stop */
else sim_interval = 0; /* force check */
if (sim_idle_enab) /* idling enabled? */
sim_idle (TMR_LFC, TRUE);
else sim_interval = sim_interval - 1; /* no, count cycle */
continue;
}

14
Interdata/id32_sys.c
View File

@@ -1,6 +1,6 @@
/* id32_sys.c: Interdata 32b simulator interface
Copyright (c) 2000-2005, Robert M. Supnik
Copyright (c) 2000-2007, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,8 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
25-Jan-07 RMS Fixed conflict between -h (hex) and -h (halfword)
18-Oct-06 RMS Re-ordered device list
02-Jul-04 RMS Fixed missing type in declaration
15-Jul-03 RMS Fixed signed/unsigned bug in get_imm
27-Feb-03 RMS Added relative addressing support
@@ -72,13 +74,13 @@ int32 sim_emax = 6;
DEVICE *sim_devices[] = {
&cpu_dev,
&sch_dev,
&pic_dev,
&lfc_dev,
&pt_dev,
&tt_dev,
&ttp_dev,
&pas_dev,
&pasl_dev,
&pic_dev,
&lfc_dev,
&lpt_dev,
&dp_dev,
&idc_dev,
@@ -365,7 +367,7 @@ if (sw & SWMASK ('C')) { /* string? */
fprintf (of, (c2 < 0x20)? "<%02X>": "%c", c2);
return -1;
}
if (sw & SWMASK ('H')) { /* halfword? */
if (sw & SWMASK ('W')) { /* halfword? */
fprint_val (of, val[0], rdx, 16, PV_RZRO);
return -1;
}
@@ -584,7 +586,7 @@ if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* ASCII chars? */
val[0] = ((t_value) cptr[0] << 8) | (t_value) cptr[1];
return -1;
}
if (sw & SWMASK ('H')) { /* halfword? */
if (sw & SWMASK ('W')) { /* halfword? */
val[0] = (int32) get_uint (cptr, rdx, DMASK16, &r); /* get number */
if (r != SCPE_OK) return r;
return -1;
@@ -680,7 +682,7 @@ switch (j) { /* case on class */
val[2] = t & DMASK16;
return -5;
case I_V_RI: /* 16b immediate */
case I_V_RI: /* 16b immediate */
r = get_imm (gbuf, &t, &inst, DMASK16); /* process imm */
if (r != SCPE_OK) return r;
val[0] = inst;

1
Interdata/id_defs.h
View File

@@ -451,7 +451,6 @@ typedef struct {
#define TMR_LFC 0 /* LFC = timer 0 */
#define TMR_PIC 1 /* PIC = timer 1 */
#define TMR_PAS 2 /* PAS = timer 2 */
#define LPT_WIDTH 132
#define VFU_LNT 132
#define MIN(x,y) (((x) < (y))? (x): (y))

4
Interdata/id_idc.c
View File

@@ -128,8 +128,8 @@
#define HCYL_V_HD 10 /* head/cyl word */
#define HCYL_V_CYL 0
#define GET_SA(cy,sf,sc,t) (((((cy)*drv_tab[t].surf)+(sf))* \
IDC_NUMSC)+(sc))
#define GET_SA(cy,sf,sc,t) \
(((((cy)*drv_tab[t].surf)+(sf))*IDC_NUMSC)+(sc))
/* The MSM (IDC) controller supports (two) six different disk drive types:

7
Interdata/id_lp.c
View File

@@ -167,8 +167,9 @@ if ((uptr->flags & UNIT_ATT) == 0) /* attached? */
t = uptr->buf; /* get character */
if (lpt_spnd || ((t >= LF) && (t < CR))) { /* spc pend or spc op? */
lpt_spnd = 0;
if (lpt_bufout (uptr) != SCPE_OK) return SCPE_IOERR; /* print */
if ((t == 1) || (t == LF)) lpt_spc (uptr, 1); /* single space */
if (lpt_bufout (uptr) != SCPE_OK) /* print */
return SCPE_IOERR;
if ((t == 1) || (t == LF)) lpt_spc (uptr, 1); /* single space */
else if (t == VT) r = lpt_vfu (uptr, VT_VFU - 1); /* VT->VFU */
else if (t == 0xC) r = lpt_vfu (uptr, FF_VFU - 1); /* FF->VFU */
else if ((t >= SPC_BASE) && (t < VFU_BASE))
@@ -287,7 +288,7 @@ char cbuf[CBUFSIZE], gbuf[CBUFSIZE];
if (*cptr != 0) return SCPE_ARG;
ptr = 0;
for ( ; (cptr = fgets (cbuf, CBUFSIZE, fileref)) != NULL; ) { /* until eof */
for ( ; (cptr = fgets (cbuf, CBUFSIZE, fileref)) != NULL; ) { /* until eof */
mask = 0;
if (*cptr == '(') { /* repeat count? */
cptr = get_glyph (cptr + 1, gbuf, ')'); /* get 1st field */

8
Interdata/id_mt.c
View File

@@ -312,8 +312,8 @@ switch (uptr->UCMD) { /* case on function */
case MTC_RD: /* read */
if (mt_blnt == 0) { /* first time? */
st = sim_tape_rdrecf (uptr, mtxb, &tbc, MT_MAXFR); /* read rec */
if (st == MTSE_RECE) mt_sta = mt_sta | STA_ERR; /* rec in err? */
st = sim_tape_rdrecf (uptr, mtxb, &tbc, MT_MAXFR); /* read rec */
if (st == MTSE_RECE) mt_sta = mt_sta | STA_ERR; /* rec in err? */
else if (st != SCPE_OK) { /* other error? */
r = mt_map_err (uptr, st); /* map error */
if (sch_actv (mt_dib.sch, dev)) /* if sch, stop */
@@ -343,7 +343,7 @@ switch (uptr->UCMD) { /* case on function */
case MTC_WR: /* write */
if (sch_actv (mt_dib.sch, dev)) { /* sch active? */
mt_bptr = sch_rdmem (mt_dib.sch, mtxb, MT_MAXFR); /* get rec */
mt_bptr = sch_rdmem (mt_dib.sch, mtxb, MT_MAXFR); /* get rec */
if (sch_actv (mt_dib.sch, dev)) /* not done? */
sch_stop (mt_dib.sch); /* stop chan */
}
@@ -357,7 +357,7 @@ switch (uptr->UCMD) { /* case on function */
}
if (mt_bptr) { /* any chars? */
if (st = sim_tape_wrrecf (uptr, mtxb, mt_bptr)) /* write, err? */
if (st = sim_tape_wrrecf (uptr, mtxb, mt_bptr)) /* write, err? */
r = mt_map_err (uptr, st); /* map error */
}
break; /* record done */

26
Interdata/id_pas.c
View File

@@ -1,6 +1,6 @@
/* id_pas.c: Interdata programmable async line adapter simulator
Copyright (c) 2001-2005, Robert M Supnik
Copyright (c) 2001-2006, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
pas Programmable asynchronous line adapter(s)
18-Oct-06 RMS Synced PASLA to clock
22-Nov-05 RMS Revised for new terminal processing routines
29-Jun-05 RMS Added SET PASLn DISCONNECT
21-Jun-05 RMS Fixed bug in SHOW CONN/STATS
@@ -49,7 +50,6 @@
#define UNIT_V_MDM (TTUF_V_UF + 0) /* modem control */
#define UNIT_MDM (1 << UNIT_V_MDM)
#define PAS_INIT_POLL 8000
#define PASL_WAIT 500
/* Status byte */
@@ -88,6 +88,7 @@
#define CMD_TYP 0x01 /* command type */
extern uint32 int_req[INTSZ], int_enb[INTSZ];
extern int32 lfc_poll;
uint8 pas_sta[PAS_LINES]; /* status */
uint16 pas_cmd[PAS_LINES]; /* command */
@@ -96,7 +97,6 @@ uint8 pas_xbuf[PAS_LINES]; /* xmt buf */
uint8 pas_rarm[PAS_LINES]; /* rcvr int armed */
uint8 pas_xarm[PAS_LINES]; /* xmt int armed */
uint8 pas_rchp[PAS_LINES]; /* rcvr chr pend */
uint32 pas_tps = 50; /* polls/second */
uint8 pas_tplte[PAS_LINES * 2 + 1]; /* template */
TMLN pas_ldsc[PAS_LINES] = { 0 }; /* line descriptors */
@@ -126,7 +126,7 @@ void pas_reset_ln (int32 i);
DIB pas_dib = { d_PAS, -1, v_PAS, pas_tplte, &pas, &pas_ini };
UNIT pas_unit = { UDATA (&pasi_svc, UNIT_ATTABLE, 0), PAS_INIT_POLL };
UNIT pas_unit = { UDATA (&pasi_svc, UNIT_ATTABLE, 0), 0 };
REG pas_nlreg = { DRDATA (NLINES, PAS_ENAB, 6), PV_LEFT };
@@ -312,11 +312,10 @@ return 0;
t_stat pasi_svc (UNIT *uptr)
{
int32 ln, c, out, t;
int32 ln, c, out;
if ((uptr->flags & UNIT_ATT) == 0) return SCPE_OK; /* attached? */
t = sim_rtcn_calb (pas_tps, TMR_PAS); /* calibrate */
sim_activate (uptr, t); /* continue poll */
sim_activate (uptr, lfc_poll); /* continue poll */
ln = tmxr_poll_conn (&pas_desc); /* look for connect */
if (ln >= 0) { /* got one? */
if ((pasl_unit[ln].flags & UNIT_MDM) && /* modem control */
@@ -448,7 +447,7 @@ return c & 0xFF;
t_stat pas_reset (DEVICE *dptr)
{
int32 i, t;
int32 i;
if (dptr->flags & DEV_DIS) { /* disabled? */
pas_dev.flags = pas_dev.flags | DEV_DIS; /* disable lines */
@@ -458,12 +457,8 @@ else {
pas_dev.flags = pas_dev.flags & ~DEV_DIS; /* enable lines */
pasl_dev.flags = pasl_dev.flags & ~DEV_DIS;
}
if (pas_unit.flags & UNIT_ATT) { /* master att? */
if (!sim_is_active (&pas_unit)) {
t = sim_rtcn_init (pas_unit.wait, TMR_PAS);
sim_activate (&pas_unit, t); /* activate */
}
}
if (pas_unit.flags & UNIT_ATT) /* master att? */
sim_activate_abs (&pas_unit, lfc_poll); /* cosched with clock */
else sim_cancel (&pas_unit); /* else stop */
for (i = 0; i < PAS_LINES; i++) pas_reset_ln (i);
return SCPE_OK;
@@ -477,8 +472,7 @@ t_stat r;
r = tmxr_attach (&pas_desc, uptr, cptr); /* attach */
if (r != SCPE_OK) return r; /* error */
sim_rtcn_init (pas_unit.wait, TMR_PAS);
sim_activate (uptr, 100); /* quick poll */
sim_activate_abs (uptr, 100); /* quick poll */
return SCPE_OK;
}

17
Interdata/id_tt.c
View File

@@ -1,6 +1,6 @@
/* id_tt.c: Interdata teletype
Copyright (c) 2000-2005, Robert M. Supnik
Copyright (c) 2000-2006, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,8 @@
tt console
18-Oct-06 RMS Sync keyboard to LFC clock
30-Sep-06 RMS Fixed handling of non-printable characters in KSR mode
22-Nov-05 RMS Revised for new terminal processing routines
29-Dec-03 RMS Added support for console backpressure
25-Apr-03 RMS Revised for extended file support
@@ -49,6 +51,7 @@
#define CMD_V_RD 2 /* read/write */
extern uint32 int_req[INTSZ], int_enb[INTSZ];
extern int32 lfc_poll;
uint32 tt_sta = STA_BSY; /* status */
uint32 tt_fdpx = 1; /* tt mode */
@@ -74,7 +77,7 @@ t_stat tt_set_enbdis (UNIT *uptr, int32 val, char *cptr, void *desc);
DIB tt_dib = { d_TT, -1, v_TT, NULL, &tt, NULL };
UNIT tt_unit[] = {
{ UDATA (&tti_svc, TT_MODE_KSR, 0), KBD_POLL_WAIT },
{ UDATA (&tti_svc, TT_MODE_KSR, 0), 0 },
{ UDATA (&tto_svc, TT_MODE_KSR, 0), SERIAL_OUT_WAIT }
};
@@ -82,7 +85,7 @@ REG tt_reg[] = {
{ HRDATA (STA, tt_sta, 8) },
{ HRDATA (KBUF, tt_unit[TTI].buf, 8) },
{ DRDATA (KPOS, tt_unit[TTI].pos, T_ADDR_W), PV_LEFT },
{ DRDATA (KTIME, tt_unit[TTI].wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (KTIME, tt_unit[TTI].wait, 24), PV_LEFT },
{ HRDATA (TBUF, tt_unit[TTO].buf, 8) },
{ DRDATA (TPOS, tt_unit[TTO].pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TTIME, tt_unit[TTO].wait, 24), REG_NZ + PV_LEFT },
@@ -175,7 +178,7 @@ t_stat tti_svc (UNIT *uptr)
{
int32 out, temp;
sim_activate (uptr, uptr->wait); /* continue poll */
sim_activate (uptr, KBD_WAIT (uptr->wait, lfc_poll)); /* continue poll */
tt_sta = tt_sta & ~STA_BRK; /* clear break */
if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp; /* no char or error? */
if (tt_rd) { /* read mode? */
@@ -192,7 +195,7 @@ if (temp & SCPE_BREAK) { /* break? */
else uptr->buf = sim_tt_inpcvt (temp, TT_GET_MODE (uptr->flags) | TTUF_KSR);
uptr->pos = uptr->pos + 1; /* incr count */
if (!tt_fdpx) { /* half duplex? */
out = sim_tt_outcvt (out, TT_GET_MODE (uptr->flags));
out = sim_tt_outcvt (out, TT_GET_MODE (uptr->flags) | TTUF_KSR);
if (out >= 0) { /* valid echo? */
sim_putchar (out); /* write char */
tt_unit[TTO].pos = tt_unit[TTO].pos + 1;
@@ -206,7 +209,7 @@ t_stat tto_svc (UNIT *uptr)
int32 ch;
t_stat r;
ch = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags));
ch = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags) | TTUF_KSR);
if (ch >= 0) {
if ((r = sim_putchar_s (ch)) != SCPE_OK) { /* output; error? */
sim_activate (uptr, uptr->wait); /* try again */
@@ -226,7 +229,7 @@ return SCPE_OK;
t_stat tt_reset (DEVICE *dptr)
{
if (dptr->flags & DEV_DIS) sim_cancel (&tt_unit[TTI]); /* dis? cancel poll */
else sim_activate (&tt_unit[TTI], tt_unit[TTI].wait); /* activate input */
else sim_activate_abs (&tt_unit[TTI], KBD_WAIT (tt_unit[TTI].wait, lfc_poll));
sim_cancel (&tt_unit[TTO]); /* cancel output */
tt_rd = tt_fdpx = 1; /* read, full duplex */
tt_chp = 0; /* no char */

15
Interdata/id_ttp.c
View File

@@ -1,6 +1,6 @@
/* id_ttp.c: Interdata PASLA console interface
Copyright (c) 2000-2005, Robert M. Supnik
Copyright (c) 2000-2006, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
ttp console (on PAS)
18-Oct-06 RMS Sync keyboard to LFC clock
22-Nov-05 RMS Revised for new terminal processing routines
29-Dec-03 RMS Added support for console backpressure
25-Apr-03 RMS Revised for extended file support
@@ -52,6 +53,8 @@
#define CMD_TYP 0x01 /* command type */
extern uint32 int_req[INTSZ], int_enb[INTSZ];
extern int32 pas_par (int32 cmd, int32 c);
extern int32 lfc_poll;
uint32 ttp_sta = 0; /* status */
uint32 ttp_cmd = 0; /* command */
@@ -68,14 +71,12 @@ t_stat ttp_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat ttp_set_break (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat ttp_set_enbdis (UNIT *uptr, int32 val, char *cptr, void *desc);
extern int32 pas_par (int32 cmd, int32 c);
/* TTP data structures */
DIB ttp_dib = { d_TTP, -1, v_TTP, ttp_tplte, &ttp, NULL };
UNIT ttp_unit[] = {
{ UDATA (&ttpi_svc, 0, 0), KBD_POLL_WAIT },
{ UDATA (&ttpi_svc, 0, 0), 0 },
{ UDATA (&ttpo_svc, 0, 0), SERIAL_OUT_WAIT }
};
@@ -83,7 +84,7 @@ REG ttp_reg[] = {
{ HRDATA (CMD, ttp_cmd, 16) },
{ HRDATA (KBUF, ttp_unit[TTI].buf, 8) },
{ DRDATA (KPOS, ttp_unit[TTI].pos, T_ADDR_W), PV_LEFT },
{ DRDATA (KTIME, ttp_unit[TTI].wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (KTIME, ttp_unit[TTI].wait, 24), REG_NZ + PV_LEFT + REG_HRO },
{ FLDATA (KIREQ, int_req[l_TTP], i_TTP) },
{ FLDATA (KIENB, int_enb[l_TTP], i_TTP) },
{ FLDATA (KARM, ttp_karm, 0) },
@@ -175,7 +176,7 @@ t_stat ttpi_svc (UNIT *uptr)
{
int32 c, out;
sim_activate (uptr, uptr->wait); /* continue poll */
sim_activate (uptr, KBD_WAIT (uptr->wait, lfc_poll)); /* continue poll */
ttp_sta = ttp_sta & ~STA_FR; /* clear break */
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c; /* no char or error? */
ttp_sta = ttp_sta & ~STA_PF; /* clear parity err */
@@ -227,7 +228,7 @@ return SCPE_OK;
t_stat ttp_reset (DEVICE *dptr)
{
if (dptr->flags & DEV_DIS) sim_cancel (&ttp_unit[TTI]);
else sim_activate (&ttp_unit[TTI], ttp_unit[TTI].wait);
else sim_activate_abs (&ttp_unit[TTI], KBD_WAIT (ttp_unit[TTI].wait, lfc_poll));
sim_cancel (&ttp_unit[TTO]);
CLR_INT (v_TTP); /* clear int */
CLR_ENB (v_TTP);

20
Interdata/id_uvc.c
View File

@@ -1,6 +1,6 @@
/* id_uvc.c: Interdata universal clock
Copyright (c) 2001-2005, Robert M. Supnik
Copyright (c) 2001-2006, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -26,6 +26,7 @@
pic precision incremental clock
lfc line frequency clock
18-Oct-06 RMS Changed LFC to be free running, export tmr_poll
23-Jul-05 RMS Fixed {} error in OC
01-Mar-03 RMS Added SET/SHOW LFC FREQ support
Changed precision clock algorithm for V7 UNIX
@@ -75,6 +76,7 @@ void pic_sched (t_bool strt);
uint32 pic_rd_cic (void);
int32 lfc_tps = 120; /* ticks per */
int32 lfc_poll = 8000;
uint32 lfc_arm = 0; /* int arm */
DEVICE lfc_dev;
@@ -314,8 +316,6 @@ return SCPE_OK;
uint32 lfc (uint32 dev, uint32 op, uint32 dat)
{
int32 t;
switch (op) { /* case IO op */
case IO_ADR: /* select */
@@ -323,10 +323,6 @@ switch (op) { /* case IO op */
case IO_OC: /* command */
lfc_arm = int_chg (v_LFC, dat, lfc_arm); /* upd int ctrl */
if (lfc_arm && !sim_is_active (&lfc_unit)) { /* starting? */
t = sim_rtcn_init (lfc_unit.wait, TMR_LFC);
sim_activate (&lfc_unit, t); /* init clock */
}
break;
}
return 0;
@@ -336,13 +332,10 @@ return 0;
t_stat lfc_svc (UNIT *uptr)
{
int32 t;
lfc_poll = sim_rtcn_calb (lfc_tps, TMR_LFC); /* calibrate */
sim_activate (uptr, lfc_poll); /* reactivate */
if (lfc_arm) { /* armed? */
SET_INT (v_LFC); /* req intr */
if (pic_unit.flags & UNIT_DIAG) t = uptr->wait; /* diag? fixed delay */
else t = sim_rtcn_calb (lfc_tps, TMR_LFC); /* else calibrate */
sim_activate (uptr, t); /* reactivate */
}
return SCPE_OK;
}
@@ -351,7 +344,8 @@ return SCPE_OK;
t_stat lfc_reset (DEVICE *dptr)
{
sim_cancel (&lfc_unit); /* cancel unit */
lfc_poll = sim_rtcn_init (lfc_unit.wait, TMR_LFC);
sim_activate_abs (&lfc_unit, lfc_poll); /* init clock */
CLR_INT (v_LFC); /* clear int */
CLR_ENB (v_LFC); /* disable int */
lfc_arm = 0; /* disarm int */