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sigma: Update latest from Bob Supnik's v3.12-5

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- Add new CP and CR devices
- COC: Zero delay from SIO to INIT state Detect and UEN on 0xFF order
- COC: Moved SIO int pending test to devices
- DK: Zero delay from SIO to INIT state
- DP: Added case points for RDEES, dp_aio_status
- DP: Zero delay from SIO to INIT state
 - defs:  Added chaining modifier flag
 - defs:  Fixed DVT_NODEV definition
 - defs:  Added chan_chk_dvi definition
 - io: Added chaining modifier flag
- LP: Zero delay from SIO to INIT state
- LP: Added INIT test for illegal command
- LP: Moved SIO interrupt test to devices
- MT: Zero delay from SIO to INIT state
- PT: Zero delay from SIO to INIT state
- PT: Moved SIO interrupt test to devices
- RAD: Zero delay from SIO to INIT state
- RAD: Fixed nx unit test
- RAD: Fixed write protect test
- TT: Zero delay from SIO to INIT state
- TT: Moved SIO int pending test to devices
This commit is contained in:
Ken Rector
2024-07-29 10:10:17 -10:00
committed by Mark Pizzolato
parent d2cd594cde
commit 5421c9c22e
17 changed files with 954 additions and 46 deletions
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74
sigma/sigma_sys.c
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@@ -1,6 +1,6 @@
/* sigma_sys.c: Sigma system interface
Copyright (c) 2007-2017, Robert M Supnik
Copyright (c) 2007-2024, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
03-Apr-2024 RMS Added CR, CP support (Ken Rector)
09-Mar-2017 RMS Added LOAD processor for CCT
*/
@@ -43,6 +44,8 @@ extern DEVICE rad_dev;
extern DEVICE dk_dev;
extern DEVICE dp_dev[];
extern DEVICE mt_dev;
extern DEVICE cr_dev;
extern DEVICE cp_dev;
extern DEVICE mux_dev, muxl_dev;
extern REG cpu_reg[];
extern uint32 *M;
@@ -93,6 +96,8 @@ DEVICE *sim_devices[] = {
&dp_dev[1],
&mux_dev,
&muxl_dev,
&cr_dev,
&cp_dev,
NULL
};
@@ -166,6 +171,73 @@ uint8 ebcdic_to_ascii[256] = {
'8', '9', 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F,
};
uint16 ebcdic_to_hol[256] = {
/* T918 T91 T92 T93 T94 T95 T96 T97 0x0x */
0xB03, 0x901, 0x881, 0x841, 0x821, 0x811, 0x809, 0x805,
/* T98, T189 , T289, T389, T489, T589, T689, T789 */
0x803, 0x903, 0x883, 0x843, 0x823, 0x813, 0x80B, 0x807,
/* TE189 E91 E92 E93 E94 E95 E96 E97 0x1x */
0xD03, 0x501, 0x481, 0x441, 0x421, 0x411, 0x409, 0x405,
/* E98 E918 E928 E938 E948 E958 E968 E978 */
0x403, 0x503, 0x483, 0x443, 0x423, 0x413, 0x40B, 0x407,
/* E0918 091 092 093 094 095 096 097 0x2x */
0x703, 0x301, 0x281, 0x241, 0x221, 0x211, 0x209, 0x205,
/* 098 0918 0928 0938 0948 0958 0968 0978 */
0x203, 0x303, 0x283, 0x243, 0x223, 0x213, 0x20B, 0x207,
/* TE0918 91 92 93 94 95 96 97 0x3x */
0xF03, 0x101, 0x081, 0x041, 0x021, 0x011, 0x009, 0x005,
/* 98 189 289 389 489 589 689 789 */
0x003, 0x103, 0x083, 0x043, 0x023, 0x013, 0x00B, 0x007,
/* T091 T092 T093 T094 T095 T096 T097 0x4x */
0x000, 0xB01, 0xA81, 0xA41, 0xA21, 0xA11, 0xA09, 0xA05,
/* T098 T18 T28 T38 T48 T58 T68 T78 */
0xA03, 0x902, 0x882, 0x842, 0x822, 0x812, 0x80A, 0x806,
/* T TE91 TE92 TE93 TE94 TE95 TE96 TE97 0x5x */
0x800, 0xD01, 0xC81, 0xC41, 0xC21, 0xC11, 0xC09, 0xC05,
/* TE98 E18 E28 E38 E48 E58 E68 E78 */
0xC03, 0x502, 0x482, 0x442, 0x422, 0x412, 0x40A, 0x406,
/* E 01 E092 E093 E094 E095 E096 E097 0x6x */
0x400, 0x300, 0x681, 0x641, 0x621, 0x611, 0x609, 0x605,
/* E098 018 TE 038 048 68 068 078 */
0x603, 0x302, 0xC00, 0x242, 0x222, 0x212, 0x20A, 0x206,
/* TE0 TE091 TE092 TE093 TE094 TE095 TE096 TE097 0x7x */
0xE00, 0xF01, 0xE81, 0xE41, 0xE21, 0xE11, 0xE09, 0xE05,
/* TE098 18 28 38 48 58 68 78 */
0xE03, 0x102, 0x082, 0x042, 0x022, 0x012, 0x00A, 0x006,
/* T018 T01 T02 T03 T04 T05 T06 T07 0x8x */
0xB02, 0xB00, 0xA80, 0xA40, 0xA20, 0xA10, 0xA08, 0xA04,
/* T08 T09 T028 T038 T048 T058 T068 T078 */
0xA02, 0xA01, 0xA82, 0xA42, 0xA22, 0xA12, 0xA0A, 0xA06,
/* TE18 TE1 TE2 TE3 TE4 TE5 TE6 TE7 0x9x */
0xD02, 0xD00, 0xC80, 0xC40, 0xC20, 0xC10, 0xC08, 0xC04,
/* TE8 TE9 TE28 TE38 TE48 TE58 TE68 TE78 */
0xC02, 0xC01, 0xC82, 0xC42, 0xC22, 0xC12, 0xC0A, 0xC06,
/* E018 E01 E02 E03 E04 E05 E06 E07 0xax */
0x702, 0x700, 0x680, 0x640, 0x620, 0x610, 0x608, 0x604,
/* E08 E09 E028 E038 E048 E058 E068 E078 */
0x602, 0x601, 0x682, 0x642, 0x622, 0x612, 0x60A, 0x606,
/* TE018 TE01 TE02 TE03 TE04 TE05 TE06 TE07 0xbx */
0xF02, 0xF00, 0xE80, 0xE40, 0xE20, 0xE10, 0xE08, 0xE04,
/* TE08 TE09 TE028 TE038 TE048 TE058 TE068 TE078 */
0xE02, 0xE01, 0xE82, 0xE42, 0xE22, 0xE12, 0xE0A, 0xE06,
/* T0 T1 T2 T3 T4 T5 T6 T7 0xcx */
0xA00, 0x900, 0x880, 0x840, 0x820, 0x810, 0x808, 0x804,
/* T8 T9 T0928 T0938 T0948 T0958 T0968 T0978 */
0x802, 0x801, 0xA83, 0xA43, 0xA23, 0xA13, 0xA0B, 0xA07,
/* E0 E1 E2 E3 E4 E5 E6 E7 0xdx */
0x600, 0x500, 0x480, 0x440, 0x420, 0x410, 0x408, 0x404,
/* E8 E9 TE928 TE938 TE948 TE958 TE968 TE978 */
0x402, 0x401, 0xC83, 0xC43, 0xC23, 0xC13, 0xC0B, 0xC07,
/* 028 E091 02 03 04 05 06 07 0xex */
0x282, 0x701, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
/* 08 09 E0928 E0938 E0948 E0958 E0968 E0978 */
0x202, 0x201, 0x683, 0x643, 0x623, 0x613, 0x60B, 0x607,
/* 0 1 2 3 4 5 6 7 0xfx */
0x200, 0x100, 0x080, 0x040, 0x020, 0x010, 0x008, 0x004,
/* 8 9 TE0928 TE0938 TE0948 TE0958 TE0968 TE0978 */
0x002, 0x001, 0xE83, 0xE43, 0xE23, 0xE13, 0xE0B, 0xE07
};
/* Binary loader */
t_stat sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)