github.com/simh.simh
1
0
Fork 0
mirror of https://github.com/simh/simh.git synced 2026-01-13 15:27:14 +00:00
Code Releases Activity

PDP-10: added register descriptions

Browse Source
This commit is contained in:
Ray Jewhurst 2016-04-10 19:19:40 -04:00 committed by Mark Pizzolato
parent 60c9289c1d
commit 5433561314
7 changed files with 131 additions and 131 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

102
PDP10/pdp10_cpu.c
View File

@ -341,59 +341,59 @@ extern t_stat tim_set_mod (UNIT *uptr, int32 val, char *cptr, void *desc);
UNIT cpu_unit = { UDATA (NULL, UNIT_FIX + UNIT_BINK, MAXMEMSIZE) };
REG cpu_reg[] = {
{ ORDATA (PC, saved_PC, VASIZE) },
{ ORDATA (FLAGS, flags, 18) },
{ ORDATA (AC0, acs[0], 36) }, /* addr in memory */
{ ORDATA (AC1, acs[1], 36) }, /* modified at exit */
{ ORDATA (AC2, acs[2], 36) }, /* to SCP */
{ ORDATA (AC3, acs[3], 36) },
{ ORDATA (AC4, acs[4], 36) },
{ ORDATA (AC5, acs[5], 36) },
{ ORDATA (AC6, acs[6], 36) },
{ ORDATA (AC7, acs[7], 36) },
{ ORDATA (AC10, acs[10], 36) },
{ ORDATA (AC11, acs[11], 36) },
{ ORDATA (AC12, acs[12], 36) },
{ ORDATA (AC13, acs[13], 36) },
{ ORDATA (AC14, acs[14], 36) },
{ ORDATA (AC15, acs[15], 36) },
{ ORDATA (AC16, acs[16], 36) },
{ ORDATA (AC17, acs[17], 36) },
{ ORDATA (PFW, pager_word, 36) },
{ ORDATA (EBR, ebr, EBR_N_EBR) },
{ FLDATA (PGON, ebr, EBR_V_PGON) },
{ FLDATA (T20P, ebr, EBR_V_T20P) },
{ ORDATA (UBR, ubr, 36) },
{ GRDATA (CURAC, ubr, 8, 3, UBR_V_CURAC), REG_RO },
{ GRDATA (PRVAC, ubr, 8, 3, UBR_V_PRVAC) },
{ ORDATA (SPT, spt, 36) },
{ ORDATA (CST, cst, 36) },
{ ORDATA (PUR, pur, 36) },
{ ORDATA (CSTM, cstm, 36) },
{ ORDATA (HSB, hsb, 36) },
{ ORDATA (DBR1, dbr1, PASIZE) },
{ ORDATA (DBR2, dbr2, PASIZE) },
{ ORDATA (DBR3, dbr3, PASIZE) },
{ ORDATA (DBR4, dbr4, PASIZE) },
{ ORDATA (PCST, pcst, 36) },
{ ORDATA (PIENB, pi_enb, 7) },
{ FLDATA (PION, pi_on, 0) },
{ ORDATA (PIACT, pi_act, 7) },
{ ORDATA (PIPRQ, pi_prq, 7) },
{ ORDATA (PIIOQ, pi_ioq, 7), REG_RO },
{ ORDATA (PIAPR, pi_apr, 7), REG_RO },
{ ORDATA (APRENB, apr_enb, 8) },
{ ORDATA (APRFLG, apr_flg, 8) },
{ ORDATA (APRLVL, apr_lvl, 3) },
{ ORDATA (RLOG, rlog, 10) },
{ FLDATA (F1PR, its_1pr, 0) },
{ BRDATA (PCQ, pcq, 8, VASIZE, PCQ_SIZE), REG_RO+REG_CIRC },
{ ORDATAD (PC, saved_PC, VASIZE, "program counter") },
{ ORDATAD (FLAGS, flags, 18, "processor flags (<13:17> unused") },
{ ORDATAD (AC0, acs[0], 36, "active register 0") }, /* addr in memory */
{ ORDATAD (AC1, acs[1], 36, "active register 1") }, /* modified at exit */
{ ORDATAD (AC2, acs[2], 36, "active register 2") }, /* to SCP */
{ ORDATAD (AC3, acs[3], 36, "active register 3") },
{ ORDATAD (AC4, acs[4], 36, "active register 4") },
{ ORDATAD (AC5, acs[5], 36, "active register 5") },
{ ORDATAD (AC6, acs[6], 36, "active register 6") },
{ ORDATAD (AC7, acs[7], 36, "active register 7") },
{ ORDATAD (AC10, acs[10], 36, "active register 10") },
{ ORDATAD (AC11, acs[11], 36, "active register 11") },
{ ORDATAD (AC12, acs[12], 36, "active register 12") },
{ ORDATAD (AC13, acs[13], 36, "active register 13") },
{ ORDATAD (AC14, acs[14], 36, "active register 14") },
{ ORDATAD (AC15, acs[15], 36, "active register 15") },
{ ORDATAD (AC16, acs[16], 36, "active register 16") },
{ ORDATAD (AC17, acs[17], 36, "active register 17") },
{ ORDATAD (PFW, pager_word, 36, "pager word register") },
{ ORDATAD (EBR, ebr, EBR_N_EBR, "executive base register") },
{ FLDATAD (PGON, ebr, EBR_V_PGON, "paging enabled flag") },
{ FLDATAD (T20P, ebr, EBR_V_T20P, "TOPS-20 paging") },
{ ORDATAD (UBR, ubr, 36, "user base register") },
{ GRDATAD (CURAC, ubr, 8, 3, UBR_V_CURAC, "current AC block"), REG_RO },
{ GRDATAD (PRVAC, ubr, 8, 3, UBR_V_PRVAC, "previous AC block") },
{ ORDATAD (SPT, spt, 36, "shared pointer table") },
{ ORDATAD (CST, cst, 36, "core status table") },
{ ORDATAD (PUR, pur, 36, "process update register") },
{ ORDATAD (CSTM, cstm, 36, "CST mask") },
{ ORDATAD (HSB, hsb, 36, "halt status block address") },
{ ORDATAD (DBR1, dbr1, PASIZE, "descriptor base register 1 (ITS)") },
{ ORDATAD (DBR2, dbr2, PASIZE, "descriptor base register 2 (ITS)") },
{ ORDATAD (DBR3, dbr3, PASIZE, "descriptor base register 3 (ITS)") },
{ ORDATAD (DBR4, dbr4, PASIZE, "descriptor base register 4 (ITS)") },
{ ORDATAD (PCST, pcst, 36, "ITS PC sampling register") },
{ ORDATAD (PIENB, pi_enb, 7, "PI levels enabled") },
{ FLDATAD (PION, pi_on, 0, "PI system enable") },
{ ORDATAD (PIACT, pi_act, 7, "PI levels active") },
{ ORDATAD (PIPRQ, pi_prq, 7, "PI levels with program requests") },
{ ORDATAD (PIIOQ, pi_ioq, 7, "PI levels with I/O requests"), REG_RO },
{ ORDATAD (PIAPR, pi_apr, 7, "PI levels with APR requests"), REG_RO },
{ ORDATAD (APRENB, apr_enb, 8, "APR flags enabled") },
{ ORDATAD (APRFLG, apr_flg, 8, "APR flags active") },
{ ORDATAD (APRLVL, apr_lvl, 3, "PI level for APR interrupt") },
{ ORDATAD (RLOG, rlog, 10, "extend fix up log") },
{ FLDATAD (F1PR, its_1pr, 0, "ITS 1-proceed") },
{ BRDATAD (PCQ, pcq, 8, VASIZE, PCQ_SIZE, "PC prior to last jump or interrupt; most recent PC change first"), REG_RO+REG_CIRC },
{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
{ DRDATA (INDMAX, ind_max, 8), PV_LEFT },
{ DRDATA (XCTMAX, xct_max, 8), PV_LEFT },
{ ORDATA (WRU, sim_int_char, 8) },
{ DRDATAD (INDMAX, ind_max, 8, "indirect address nesting limit; if 0, no limit"), PV_LEFT },
{ DRDATAD (XCTMAX, xct_max, 8, "execute chaining limit; if 0, no limit"), PV_LEFT },
{ ORDATAD (WRU, sim_int_char, 8, "interrupt character") },
{ FLDATA (STOP_ILL, stop_op0, 0) },
{ BRDATA (REG, acs, 8, 36, AC_NUM * AC_NBLK) },
{ BRDATAD (REG, acs, 8, 36, AC_NUM * AC_NBLK, "register sets") },
{ NULL }
};

12
PDP10/pdp10_fe.c
View File

@ -73,12 +73,12 @@ UNIT fe_unit[] = {
};
REG fe_reg[] = {
{ ORDATA (IBUF, fei_unit.buf, 8) },
{ DRDATA (ICOUNT, fei_unit.pos, T_ADDR_W), REG_RO + PV_LEFT },
{ DRDATA (ITIME, fei_unit.wait, 24), PV_LEFT },
{ ORDATA (OBUF, feo_unit.buf, 8) },
{ DRDATA (OCOUNT, feo_unit.pos, T_ADDR_W), REG_RO + PV_LEFT },
{ DRDATA (OTIME, feo_unit.wait, 24), REG_NZ + PV_LEFT },
{ ORDATAD (IBUF, fei_unit.buf, 8, "input buffer") },
{ DRDATAD (ICOUNT, fei_unit.pos, T_ADDR_W, "count of input characters"), REG_RO + PV_LEFT },
{ DRDATAD (ITIME, fei_unit.wait, 24, "input polling interval (if 0, the keyboard is polled synchronously with the clock"), PV_LEFT },
{ ORDATAD (OBUF, feo_unit.buf, 8, "output buffer") },
{ DRDATAD (OCOUNT, feo_unit.pos, T_ADDR_W, "count of output characters"), REG_RO + PV_LEFT },
{ DRDATAD (OTIME, feo_unit.wait, 24, "console output response time"), REG_NZ + PV_LEFT },
{ NULL }
};

6
PDP10/pdp10_ksio.c
View File

@ -194,9 +194,9 @@ UNIT uba_unit[] = {
};
REG uba_reg[] = {
{ ORDATA (INTREQ, int_req, 32), REG_RO },
{ ORDATA (UB1CS, ubcs[0], 18) },
{ ORDATA (UB3CS, ubcs[1], 18) },
{ ORDATAD (INTREQ, int_req, 32, "interrupt request"), REG_RO },
{ ORDATAD (UB1CS, ubcs[0], 18, "Unibus adapter 1 control/status") },
{ ORDATAD (UB3CS, ubcs[1], 18, "Unibus adapter 3 control/status") },
{ NULL }
};

44
PDP10/pdp10_lp20.c
View File

@ -352,30 +352,30 @@ static UNIT lp20_idle = {
};
static REG lp20_reg[] = {
{ ORDATA (LPCSA, lpcsa, 16) },
{ ORDATA (LPCSB, lpcsb, 16) },
{ ORDATA (LPBA, lpba, 16) },
{ ORDATA (LPBC, lpbc, 12) },
{ ORDATA (LPPAGC, lppagc, 12) },
{ ORDATA (LPRDAT, lprdat, 13) },
{ ORDATA (LPCBUF, lpcbuf, 8) },
{ ORDATA (LPCOLC, lpcolc, 8) },
{ ORDATA (LPPDAT, lppdat, 8) },
{ ORDATA (LPCSUM, lpcsum, 8) },
{ ORDATA (DVPTR, dvptr, 7) },
{ ORDATA (DVLNT, dvlnt, 7), REG_RO + REG_NZ },
{ ORDATAD (LPCSA, lpcsa, 16, "control/status register A") },
{ ORDATAD (LPCSB, lpcsb, 16, "control/status register B") },
{ ORDATAD (LPBA, lpba, 16, "bus address register") },
{ ORDATAD (LPBC, lpbc, 12, "byte count register") },
{ ORDATAD (LPPAGC, lppagc, 12, "page count register") },
{ ORDATAD (LPRDAT, lprdat, 13, "RAM data register") },
{ ORDATAD (LPCBUF, lpcbuf, 8, "character buffer register") },
{ ORDATAD (LPCOLC, lpcolc, 8, "column counter register") },
{ ORDATAD (LPPDAT, lppdat, 8, "printer data register") },
{ ORDATAD (LPCSUM, lpcsum, 8, "checksum register") },
{ ORDATAD (DVPTR, dvptr, 7, "vertical forms unit pointer") },
{ ORDATAD (DVLNT, dvlnt, 7, "vertical forms unit length"), REG_RO + REG_NZ },
{ ORDATA (DVLD, dvld, 2), REG_RO | REG_HIDDEN },
{ ORDATA (DVLDH, dvld_hold, 6), REG_RO | REG_HIDDEN },
{ FLDATA (INT, int_req, INT_V_LP20) },
{ FLDATA (IRQ, lp20_irq, 0) },
{ FLDATA (ERR, lpcsa, CSR_V_ERR) },
{ FLDATA (DONE, lpcsa, CSR_V_DONE) },
{ FLDATA (IE, lpcsa, CSR_V_IE) },
{ DRDATA (POS, lp20_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, lp20_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, lp20_stopioe, 0) },
{ BRDATA (TXRAM, txram, 8, 13, TX_SIZE) },
{ BRDATA (DAVFU, davfu, 8, 12, DV_SIZE) },
{ FLDATAD (INT, int_req, INT_V_LP20, "interrupt request") },
{ FLDATAD (IRQ, lp20_irq, 0, "clear interrupt request") },
{ FLDATAD (ERR, lpcsa, CSR_V_ERR, "error flag") },
{ FLDATAD (DONE, lpcsa, CSR_V_DONE, "done flag") },
{ FLDATAD (IE, lpcsa, CSR_V_IE, "interrupt enable flag") },
{ DRDATAD (POS, lp20_unit.pos, T_ADDR_W, "position in output file"), PV_LEFT },
{ DRDATAD (TIME, lp20_unit.wait, 24, "response time"), PV_LEFT },
{ FLDATAD (STOP_IOE, lp20_stopioe, 0, "stop on I/O error") },
{ BRDATAD (TXRAM, txram, 8, 13, TX_SIZE, "translation RAM") },
{ BRDATAD (DAVFU, davfu, 8, 12, DV_SIZE, "vertical forms unit array") },
{ DRDATA (LPI, lpi, 8), REG_RO | REG_HIDDEN },
{ ORDATA (DEVADDR, lp20_dib.ba, 32), REG_HRO },
{ ORDATA (DEVVEC, lp20_dib.vec, 16), REG_HRO },

50
PDP10/pdp10_rp.c
View File

@ -410,34 +410,34 @@ UNIT rp_unit[] = {
};
REG rp_reg[] = {
{ ORDATA (RPCS1, rpcs1, 16) },
{ ORDATA (RPWC, rpwc, 16) },
{ ORDATA (RPBA, rpba, 16) },
{ ORDATA (RPCS2, rpcs2, 16) },
{ ORDATA (RPDB, rpdb, 16) },
{ BRDATA (RPDA, rpda, 8, 16, RP_NUMDR) },
{ BRDATA (RPDS, rpds, 8, 16, RP_NUMDR) },
{ BRDATA (RPER1, rper1, 8, 16, RP_NUMDR) },
{ BRDATA (RPHR, rmhr, 8, 16, RP_NUMDR) },
{ BRDATA (RPOF, rpof, 8, 16, RP_NUMDR) },
{ BRDATA (RPDC, rpdc, 8, 16, RP_NUMDR) },
{ BRDATA (RPER2, rper2, 8, 16, RP_NUMDR) },
{ BRDATA (RPER3, rper3, 8, 16, RP_NUMDR) },
{ BRDATA (RPEC1, rpec1, 8, 16, RP_NUMDR) },
{ BRDATA (RPEC2, rpec2, 8, 16, RP_NUMDR) },
{ BRDATA (RMMR, rpmr, 8, 16, RP_NUMDR) },
{ BRDATA (RMMR2, rmmr2, 8, 16, RP_NUMDR) },
{ FLDATA (IFF, rpiff, 0) },
{ FLDATA (INT, int_req, INT_V_RP) },
{ FLDATA (SC, rpcs1, CSR_V_ERR) },
{ FLDATA (DONE, rpcs1, CSR_V_DONE) },
{ FLDATA (IE, rpcs1, CSR_V_IE) },
{ DRDATA (STIME, rp_swait, 24), REG_NZ + PV_LEFT },
{ DRDATA (RTIME, rp_rwait, 24), REG_NZ + PV_LEFT },
{ ORDATAD (RPCS1, rpcs1, 16, "control status 1") },
{ ORDATAD (RPWC, rpwc, 16, "word count") },
{ ORDATAD (RPBA, rpba, 16, "bus address") },
{ ORDATAD (RPCS2, rpcs2, 16, "control status") },
{ ORDATAD (RPDB, rpdb, 16, "data buffer") },
{ BRDATAD (RPDA, rpda, 8, 16, RP_NUMDR, "desired surface, sector") },
{ BRDATAD (RPDS, rpds, 8, 16, RP_NUMDR, "drive status, drives 0 to 7") },
{ BRDATAD (RPER1, rper1, 8, 16, RP_NUMDR, "drive errors, drives 0 to 7") },
{ BRDATAD (RPHR, rmhr, 8, 16, RP_NUMDR, "holding register, drives 0 to 7") },
{ BRDATAD (RPOF, rpof, 8, 16, RP_NUMDR, "offset, drives 0 to 7") },
{ BRDATAD (RPDC, rpdc, 8, 16, RP_NUMDR, "desired cylinder, drives 0 to 7") },
{ BRDATAD (RPER2, rper2, 8, 16, RP_NUMDR, "error status 2, drives 0 to 7") },
{ BRDATAD (RPER3, rper3, 8, 16, RP_NUMDR, "error status 3, drives 0 to 7") },
{ BRDATAD (RPEC1, rpec1, 8, 16, RP_NUMDR, "ECC syndrome 1, drives 0 to 7") },
{ BRDATAD (RPEC2, rpec2, 8, 16, RP_NUMDR, "ECC syndrome 2, drives 0 to 7") },
{ BRDATAD (RMMR, rpmr, 8, 16, RP_NUMDR, "maintenance register, drives 0 to 7") },
{ BRDATAD (RMMR2, rmmr2, 8, 16, RP_NUMDR, "maintenance register 2, drives 0 to 7") },
{ FLDATAD (IFF, rpiff, 0, "transfer complete interrupt request flop") },
{ FLDATAD (INT, int_req, INT_V_RP, "interrupt pending flag") },
{ FLDATAD (SC, rpcs1, CSR_V_ERR, "special condition (CSR1<15>)") },
{ FLDATAD (DONE, rpcs1, CSR_V_DONE, "device done flag (CSR1<7>)") },
{ FLDATAD (IE, rpcs1, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (STIME, rp_swait, 24, "seek time, per cylinder"), REG_NZ + PV_LEFT },
{ DRDATAD (RTIME, rp_rwait, 24, "rotational delay"), REG_NZ + PV_LEFT },
{ URDATA (FNC, rp_unit[0].FUNC, 8, 5, 0, RP_NUMDR, REG_HRO) },
{ URDATA (CAPAC, rp_unit[0].capac, 10, T_ADDR_W, 0,
RP_NUMDR, PV_LEFT | REG_HRO) },
{ FLDATA (STOP_IOE, rp_stopioe, 0) },
{ FLDATAD (STOP_IOE, rp_stopioe, 0, "stop on I/O error") },
{ NULL }
};

8
PDP10/pdp10_tim.c
View File

@ -171,10 +171,10 @@ DIB tcu_dib = { IOBA_TCU, IOLN_TCU, &tcu_rd, &wr_nop, 0 };
static UNIT tim_unit = { UDATA (&tim_svc, UNIT_IDLE, 0), 0 };
static REG tim_reg[] = {
{ BRDATA (TIMEBASE, tim_base, 8, 36, 2) },
{ ORDATA (PERIOD, tim_period, 36) },
{ ORDATA (QUANT, quant, 36) },
{ DRDATA (TIME, tim_unit.wait, 24), REG_NZ + PV_LEFT },
{ BRDATAD (TIMEBASE, tim_base, 8, 36, 2, "time base (double precision)") },
{ ORDATAD (PERIOD, tim_period, 36, "reset value for interval") },
{ ORDATAD (QUANT, quant, 36, "quantum timer (ITS only)") },
{ DRDATAD (TIME, tim_unit.wait, 24, "tick delay"), REG_NZ + PV_LEFT },
{ DRDATA (PROB, tim_t20_prob, 6), REG_NZ + PV_LEFT + REG_HIDDEN },
{ DRDATA (POLL, tmr_poll, 32), REG_HRO + PV_LEFT },
{ DRDATA (MUXPOLL, tmxr_poll, 32), REG_HRO + PV_LEFT },

40
PDP10/pdp10_tu.c
View File

@ -374,26 +374,26 @@ UNIT tu_unit[] = {
};
REG tu_reg[] = {
{ ORDATA (MTCS1, tucs1, 16) },
{ ORDATA (MTWC, tuwc, 16) },
{ ORDATA (MTBA, tuba, 16) },
{ ORDATA (MTFC, tufc, 16) },
{ ORDATA (MTCS2, tucs2, 16) },
{ ORDATA (MTFS, tufs, 16) },
{ ORDATA (MTER, tuer, 16) },
{ ORDATA (MTCC, tucc, 16) },
{ ORDATA (MTDB, tudb, 16) },
{ ORDATA (MTMR, tumr, 16) },
{ ORDATA (MTTC, tutc, 16) },
{ FLDATA (IFF, tuiff, 0) },
{ FLDATA (INT, int_req, INT_V_TU) },
{ FLDATA (DONE, tucs1, CSR_V_DONE) },
{ FLDATA (IE, tucs1, CSR_V_IE) },
{ FLDATA (STOP_IOE, tu_stopioe, 0) },
{ DRDATA (TIME, tu_time, 24), PV_LEFT },
{ URDATA (UST, tu_unit[0].USTAT, 8, 17, 0, TU_NUMDR, 0) },
{ URDATA (POS, tu_unit[0].pos, 10, T_ADDR_W, 0,
TU_NUMDR, PV_LEFT | REG_RO) },
{ ORDATAD (MTCS1, tucs1, 16, "control/status 1") },
{ ORDATAD (MTWC, tuwc, 16, "word count") },
{ ORDATAD (MTBA, tuba, 16, "memory address") },
{ ORDATAD (MTFC, tufc, 16, "frame count") },
{ ORDATAD (MTCS2, tucs2, 1, "control/status 2") },
{ ORDATAD (MTFS, tufs, 16, "formatter status") },
{ ORDATAD (MTER, tuer, 16, "error status") },
{ ORDATAD (MTCC, tucc, 16, "check character") },
{ ORDATAD (MTDB, tudb, 16, "data buffer") },
{ ORDATAD (MTMR, tumr, 16, "maintenance register") },
{ ORDATAD (MTTC, tutc, 16, "tape control register") },
{ FLDATAD (IFF, tuiff, 0, "interrupt flip/flop") },
{ FLDATAD (INT, int_req, INT_V_TU, "interrupt pending") },
{ FLDATAD (DONE, tucs1, CSR_V_DONE, "device done flag") },
{ FLDATAD (IE, tucs1, CSR_V_IE, "interrupt enable flag") },
{ FLDATAD (STOP_IOE, tu_stopioe, 0, "stop on I/O error") },
{ DRDATAD (TIME, tu_time, 24, "delay"), PV_LEFT },
{ URDATAD (UST, tu_unit[0].USTAT, 8, 17, 0, TU_NUMDR, 0, "unit status, units 0 to 7") },
{ URDATAD (POS, tu_unit[0].pos, 10, T_ADDR_W, 0,
TU_NUMDR, PV_LEFT | REG_RO, "position, units 0 to 7") },
{ ORDATA (LOG, tu_log, 8), REG_HIDDEN },
{ NULL }
};