3b2: Fix for critical MMU caching bugs

Two critical issues are fixed with this commit:

1. The MMU cache was being corrupted by writing the 'Last Used'
   bit into the wrong half of the PD cache (low word vs. high word)

2. The MMU cache was being too aggressively flushed on SRAMA
   write, because the wrong length was being used. In addition,
   the code was walking off the end of the cache array when
   flushing any section other than section 0, potentially causing
   memory corruption.

3B2/3b2_iu.c

@@ -66,9 +66,6 @@ IU_PORT iu_contty;
 /* The timer state */
 IU_TIMER_STATE iu_timer_state;
 
-/* The power flag */
-t_bool iu_killpower = FALSE;
-
 /* Flags for incrementing mode pointers */
 t_bool iu_increment_a = FALSE;
 t_bool iu_increment_b = FALSE;