mirror of
https://github.com/simh/simh.git
synced 2026-04-27 04:26:41 +00:00
ALPHA, ALTAIR, AltairZ80, I7094, NOVA, PDP1, PDP10, PDP11, PDP18B, PDP8, SAGE, sigma, swtp6800, TX-0, VAX: Change tabs to spaces which had crept in over time
This commit is contained in:
Mark Pizzolato
352
SAGE/chip_defs.h
352
SAGE/chip_defs.h
@@ -55,7 +55,7 @@
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/* generic debug tracing support */
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#if DBG_MSG==1
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#define ADDRESS_FORMAT "[0x%08x]"
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#define ADDRESS_FORMAT "[0x%08x]"
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#if UNIX_PLATFORM
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#define NLP "\r\n"
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#else
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@@ -63,21 +63,21 @@
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#endif
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#define TRACE_PRINT(level,args)\
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if(sim_deb && chip->dev->dctrl & level) { \
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fprintf(sim_deb,"%-4s: " ADDRESS_FORMAT " ", chip->dev->name, PCX); \
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fprintf args; fputs(NLP,sim_deb); }
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if(sim_deb && chip->dev->dctrl & level) { \
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fprintf(sim_deb,"%-4s: " ADDRESS_FORMAT " ", chip->dev->name, PCX); \
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fprintf args; fputs(NLP,sim_deb); }
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#define TRACE_PRINT0(level,fmt)\
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if(sim_deb && chip->dev->dctrl & level) { \
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fprintf(sim_deb,"%-4s: " ADDRESS_FORMAT " ", chip->dev->name, PCX); \
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fprintf(sim_deb,fmt NLP); }
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if(sim_deb && chip->dev->dctrl & level) { \
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fprintf(sim_deb,"%-4s: " ADDRESS_FORMAT " ", chip->dev->name, PCX); \
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fprintf(sim_deb,fmt NLP); }
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#define TRACE_PRINT1(level,fmt,arg1)\
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if(sim_deb && chip->dev->dctrl & level) { \
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fprintf(sim_deb,"%-4s: " ADDRESS_FORMAT " ", chip->dev->name, PCX); \
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fprintf(sim_deb,fmt NLP,arg1); }
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if(sim_deb && chip->dev->dctrl & level) { \
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fprintf(sim_deb,"%-4s: " ADDRESS_FORMAT " ", chip->dev->name, PCX); \
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fprintf(sim_deb,fmt NLP,arg1); }
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#define TRACE_PRINT2(level,fmt,arg1,arg2)\
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if(sim_deb && chip->dev->dctrl & level) { \
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fprintf(sim_deb,"%-4s: " ADDRESS_FORMAT " ", chip->dev->name, PCX); \
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fprintf(sim_deb,fmt NLP,arg1,arg2); }
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if(sim_deb && chip->dev->dctrl & level) { \
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fprintf(sim_deb,"%-4s: " ADDRESS_FORMAT " ", chip->dev->name, PCX); \
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fprintf(sim_deb,fmt NLP,arg1,arg2); }
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#else
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#define TRACE_PRINT(level,args)
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#define TRACE_PRINT0(level,fmt)
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@@ -90,12 +90,12 @@
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*****************************************************************************************/
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typedef struct {
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int pfirst;
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int prate;
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TMLN ldsc;
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TMXR desc;
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UNIT* term;
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UNIT* poll;
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int pfirst;
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int prate;
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TMLN ldsc;
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TMXR desc;
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UNIT* term;
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UNIT* poll;
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} SERMUX;
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t_stat mux_attach(UNIT*,char*,SERMUX*);
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t_stat mux_detach(UNIT*,SERMUX*);
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@@ -103,44 +103,44 @@ t_stat mux_detach(UNIT*,SERMUX*);
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/*****************************************************************************************
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* 8259 PIC
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*****************************************************************************************/
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#define I8259_ICW1 0x10
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#define I8259_ICW1_A765 0xe0
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#define I8259_ICW1_LTIM 0x08
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#define I8259_ICW1_ADI 0x04
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#define I8259_ICW1_SNGL 0x02
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#define I8259_ICW1_IC4 0x01
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#define I8259_ICW4_SFNM 0x10
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#define I8259_ICW4_BUF 0x08
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#define I8259_ICW4_MS 0x04
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#define I8259_ICW4_AEOI 0x02
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#define I8259_ICW4_UPM 0x01
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#define I8259_OCW2_MODE 0xe0
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#define I8259_OCW2_LEVEL 0x07
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#define I8259_OCW3_ESMM 0x40
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#define I8259_OCW3_SMM 0x20
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#define I8259_OCW3 0x08
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#define I8259_OCW3_POLL 0x04
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#define I8259_OCW3_RR 0x02
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#define I8259_OCW3_RIS 0x01
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#define I8259_ICW1 0x10
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#define I8259_ICW1_A765 0xe0
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#define I8259_ICW1_LTIM 0x08
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#define I8259_ICW1_ADI 0x04
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#define I8259_ICW1_SNGL 0x02
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#define I8259_ICW1_IC4 0x01
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#define I8259_ICW4_SFNM 0x10
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#define I8259_ICW4_BUF 0x08
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#define I8259_ICW4_MS 0x04
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#define I8259_ICW4_AEOI 0x02
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#define I8259_ICW4_UPM 0x01
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#define I8259_OCW2_MODE 0xe0
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#define I8259_OCW2_LEVEL 0x07
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#define I8259_OCW3_ESMM 0x40
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#define I8259_OCW3_SMM 0x20
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#define I8259_OCW3 0x08
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#define I8259_OCW3_POLL 0x04
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#define I8259_OCW3_RR 0x02
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#define I8259_OCW3_RIS 0x01
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typedef struct i8259 {
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PNP_INFO pnp;
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DEVICE* dev; /* backlink to device */
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t_stat (*write)(struct i8259* chip,int port,uint32 value);
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t_stat (*read)(struct i8259* chip,int port,uint32* value);
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t_stat (*reset)(struct i8259* chip);
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int state;
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int rmode;
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int32 imr;
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int32 isr;
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int32 irr;
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int32 icw1;
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int32 icw2;
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int32 icw4;
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int32 prio; /* which IR* has prio 7? */
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t_bool autoint;
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int intlevel;
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int intvector;
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PNP_INFO pnp;
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DEVICE* dev; /* backlink to device */
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t_stat (*write)(struct i8259* chip,int port,uint32 value);
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t_stat (*read)(struct i8259* chip,int port,uint32* value);
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t_stat (*reset)(struct i8259* chip);
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int state;
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int rmode;
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int32 imr;
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int32 isr;
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int32 irr;
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int32 icw1;
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int32 icw2;
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int32 icw4;
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int32 prio; /* which IR* has prio 7? */
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t_bool autoint;
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int intlevel;
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int intvector;
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} I8259;
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extern t_stat i8259_io(IOHANDLER* ioh,uint32* value,uint32 rw,uint32 mask);
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@@ -159,63 +159,63 @@ extern DEBTAB i8259_dt[];
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/*****************************************************************************************
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* 8251 USART
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*****************************************************************************************/
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#define I8251_AMODE_STOP 0xc0
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#define I8251_AMODE_S1 0x40
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#define I8251_AMODE_S15 0x80
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#define I8251_AMODE_S2 0xc0
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#define I8251_MODE_EP 0x20
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#define I8251_MODE_PEN 0x10
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#define I8251_AMODE_BITS 0x0c
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#define I8251_AMODE_BITS5 0x00
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#define I8251_AMODE_BITS6 0x04
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#define I8251_AMODE_BITS7 0x08
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#define I8251_AMODE_BITS8 0x0c
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#define I8251_MODE_BAUD 0x03
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#define I8251_MODE_SYNC 0x00
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#define I8251_AMODE_BAUD1 0x01
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#define I8251_AMODE_BAUD16 0x02
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#define I8251_AMODE_BAUD64 0x03
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#define I8251_SMODE_ESD 0x40
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#define I8251_SMODE_SCS 0x80
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#define I8251_CMD_EH 0x80
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#define I8251_CMD_IR 0x40
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#define I8251_CMD_RTS 0x20
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#define I8251_CMD_ER 0x10
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#define I8251_CMD_SBRK 0x08
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#define I8251_CMD_RXE 0x04
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#define I8251_CMD_DTR 0x02
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#define I8251_CMD_TXEN 0x01
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#define I8251_ST_DSR 0x80
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#define I8251_ST_SYNBRK 0x40
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#define I8251_ST_FE 0x20
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#define I8251_ST_OE 0x10
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#define I8251_ST_PE 0x08
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#define I8251_ST_TXEMPTY 0x04
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#define I8251_ST_RXRDY 0x02
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#define I8251_ST_TXRDY 0x01
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#define I8251_AMODE_STOP 0xc0
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#define I8251_AMODE_S1 0x40
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#define I8251_AMODE_S15 0x80
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#define I8251_AMODE_S2 0xc0
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#define I8251_MODE_EP 0x20
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#define I8251_MODE_PEN 0x10
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#define I8251_AMODE_BITS 0x0c
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#define I8251_AMODE_BITS5 0x00
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#define I8251_AMODE_BITS6 0x04
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#define I8251_AMODE_BITS7 0x08
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#define I8251_AMODE_BITS8 0x0c
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#define I8251_MODE_BAUD 0x03
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#define I8251_MODE_SYNC 0x00
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#define I8251_AMODE_BAUD1 0x01
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#define I8251_AMODE_BAUD16 0x02
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#define I8251_AMODE_BAUD64 0x03
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#define I8251_SMODE_ESD 0x40
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#define I8251_SMODE_SCS 0x80
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#define I8251_CMD_EH 0x80
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#define I8251_CMD_IR 0x40
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#define I8251_CMD_RTS 0x20
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#define I8251_CMD_ER 0x10
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#define I8251_CMD_SBRK 0x08
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#define I8251_CMD_RXE 0x04
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#define I8251_CMD_DTR 0x02
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#define I8251_CMD_TXEN 0x01
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#define I8251_ST_DSR 0x80
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#define I8251_ST_SYNBRK 0x40
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#define I8251_ST_FE 0x20
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#define I8251_ST_OE 0x10
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#define I8251_ST_PE 0x08
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#define I8251_ST_TXEMPTY 0x04
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#define I8251_ST_RXRDY 0x02
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#define I8251_ST_TXRDY 0x01
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typedef struct i8251 {
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PNP_INFO pnp;
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DEVICE* dev; /* backlink to device */
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t_stat (*write)(struct i8251* chip,int port,uint32 value);
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t_stat (*read)(struct i8251* chip,int port,uint32* value);
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t_stat (*reset)(struct i8251* chip);
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t_stat (*txint)(struct i8251* chip);
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t_stat (*rxint)(struct i8251* chip);
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UNIT* in;
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UNIT* out;
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SERMUX* mux;
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int init;
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int mode;
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int sync1;
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int sync2;
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int cmd;
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int ibuf;
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int obuf;
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int status;
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int bitmask;
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t_bool oob; /* out-of-band=1 will allow a console to receive CTRL-E even when receiver is disabled */
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int crlf; /* CRLF state machine to suppress NUL bytes */
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PNP_INFO pnp;
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DEVICE* dev; /* backlink to device */
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t_stat (*write)(struct i8251* chip,int port,uint32 value);
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t_stat (*read)(struct i8251* chip,int port,uint32* value);
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t_stat (*reset)(struct i8251* chip);
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t_stat (*txint)(struct i8251* chip);
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t_stat (*rxint)(struct i8251* chip);
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UNIT* in;
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UNIT* out;
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SERMUX* mux;
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int init;
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int mode;
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int sync1;
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int sync2;
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int cmd;
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int ibuf;
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int obuf;
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int status;
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int bitmask;
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t_bool oob; /* out-of-band=1 will allow a console to receive CTRL-E even when receiver is disabled */
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int crlf; /* CRLF state machine to suppress NUL bytes */
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} I8251;
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/* default handlers */
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@@ -236,48 +236,48 @@ extern DEBTAB i8251_dt[];
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*****************************************************************************************/
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/*forward*/ struct i8253;
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typedef struct {
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t_stat (*call)(struct i8253* chip,int rw,uint32* src);
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int state; /* the current output state (latching, MSB/LSB out */
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int mode; /* programmed mode */
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int32 latch; /* the latched value of count */
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int32 divider; /* programmed divider value */
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int32 count; /* the real count value as calculated by rcall callback */
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t_stat (*call)(struct i8253* chip,int rw,uint32* src);
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int state; /* the current output state (latching, MSB/LSB out */
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int mode; /* programmed mode */
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int32 latch; /* the latched value of count */
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int32 divider; /* programmed divider value */
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int32 count; /* the real count value as calculated by rcall callback */
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} I8253CNTR;
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typedef struct i8253 {
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PNP_INFO pnp;
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DEVICE* dev; /* backlink to device */
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UNIT* unit; /* backlink to unit */
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t_stat (*reset)(struct i8253* chip);
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t_stat (*ckmode)(struct i8253* chip, uint32 value);
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I8253CNTR cntr[3];
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int init;
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PNP_INFO pnp;
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DEVICE* dev; /* backlink to device */
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UNIT* unit; /* backlink to unit */
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t_stat (*reset)(struct i8253* chip);
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t_stat (*ckmode)(struct i8253* chip, uint32 value);
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I8253CNTR cntr[3];
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int init;
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} I8253;
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#define I8253_SCMASK 0xc0
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#define I8253_SC0 0x00
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#define I8253_SC1 0x40
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#define I8253_SC2 0x80
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#define I8253_RLMASK 0x30
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#define I8253_LATCH 0x00
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#define I8253_LSB 0x10
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#define I8253_MSB 0x20
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#define I8253_BOTH 0x30
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#define I8253_MODEMASK 0xe0
|
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#define I8253_MODE0 0x00
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#define I8253_MODE1 0x02
|
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#define I8253_MODE2 0x04
|
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#define I8253_MODE2a 0x0c
|
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#define I8253_MODE3 0x06
|
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#define I8253_MODE3a 0x0e
|
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#define I8253_MODE4 0x08
|
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#define I8253_MODE5 0x0a
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#define I8253_MODEBIN 0x00
|
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#define I8253_MODEBCD 0x01
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#define I8253_SCMASK 0xc0
|
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#define I8253_SC0 0x00
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#define I8253_SC1 0x40
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#define I8253_SC2 0x80
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#define I8253_RLMASK 0x30
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#define I8253_LATCH 0x00
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#define I8253_LSB 0x10
|
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#define I8253_MSB 0x20
|
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#define I8253_BOTH 0x30
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#define I8253_MODEMASK 0xe0
|
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#define I8253_MODE0 0x00
|
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#define I8253_MODE1 0x02
|
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#define I8253_MODE2 0x04
|
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#define I8253_MODE2a 0x0c
|
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#define I8253_MODE3 0x06
|
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#define I8253_MODE3a 0x0e
|
||||
#define I8253_MODE4 0x08
|
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#define I8253_MODE5 0x0a
|
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#define I8253_MODEBIN 0x00
|
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#define I8253_MODEBCD 0x01
|
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|
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#define I8253_ST_LSBNEXT 0x01
|
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#define I8253_ST_MSBNEXT 0x02
|
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#define I8253_ST_LATCH 0x08
|
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#define I8253_ST_LSBNEXT 0x01
|
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#define I8253_ST_MSBNEXT 0x02
|
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#define I8253_ST_LATCH 0x08
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/* default handlers */
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extern t_stat i8253_io(IOHANDLER* ioh,uint32* value,uint32 rw,uint32 mask);
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@@ -311,20 +311,20 @@ typedef struct {
|
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} I8272_DRIVE_INFO;
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typedef enum i8272state {
|
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S_CMD=1, S_CMDREAD, S_EXEC, S_DATAWRITE, S_SECWRITE, S_SECREAD, S_DATAREAD, S_RESULT
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S_CMD=1, S_CMDREAD, S_EXEC, S_DATAWRITE, S_SECWRITE, S_SECREAD, S_DATAREAD, S_RESULT
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} I8272_STATE;
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typedef struct i8272 {
|
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PNP_INFO pnp; /* Plug-n-Play Information */
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DEVICE* dev; /* backlink to device */
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||||
t_stat (*write)(struct i8272* chip,int port,uint32 data);
|
||||
t_stat (*read)(struct i8272* chip,int port,uint32* data);
|
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t_stat (*reset)(struct i8272* chip);
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void (*seldrv)(struct i8272* chip,int seldrv);
|
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void (*irq)(struct i8272* chip,int delay);
|
||||
|
||||
I8272_STATE fdc_state; /* internal state machine */
|
||||
uint32 fdc_dma_addr;/* DMA Transfer Address */
|
||||
PNP_INFO pnp; /* Plug-n-Play Information */
|
||||
DEVICE* dev; /* backlink to device */
|
||||
t_stat (*write)(struct i8272* chip,int port,uint32 data);
|
||||
t_stat (*read)(struct i8272* chip,int port,uint32* data);
|
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t_stat (*reset)(struct i8272* chip);
|
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void (*seldrv)(struct i8272* chip,int seldrv);
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void (*irq)(struct i8272* chip,int delay);
|
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|
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I8272_STATE fdc_state; /* internal state machine */
|
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uint32 fdc_dma_addr;/* DMA Transfer Address */
|
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uint8 fdc_msr; /* 8272 Main Status Register */
|
||||
uint8 fdc_nd; /* Non-DMA Mode 1=Non-DMA, 0=DMA */
|
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uint8 fdc_head; /* H Head Number */
|
||||
@@ -340,9 +340,9 @@ typedef struct i8272 {
|
||||
uint8 fdc_seek_end; /* Seek was executed successfully */
|
||||
int fdc_secsz; /* N Sector Length in bytes: 2^(7 + fdc_sec_len), fdc_sec_len <= I8272_MAX_N */
|
||||
int fdc_nd_cnt; /* read/write count in non-DMA mode, -1 if start read */
|
||||
uint8 fdc_sdata[I8272_MAX_SECTOR_SZ]; /* sector buffer */
|
||||
uint8 fdc_fault; /* error code passed from some commands to sense_int */
|
||||
|
||||
uint8 fdc_sdata[I8272_MAX_SECTOR_SZ]; /* sector buffer */
|
||||
uint8 fdc_fault; /* error code passed from some commands to sense_int */
|
||||
|
||||
uint8 cmd_cnt; /* command read count */
|
||||
uint8 cmd[10]; /* Storage for current command */
|
||||
uint8 cmd_len; /* FDC Command Length */
|
||||
@@ -397,22 +397,22 @@ extern DEVICE* i8272_dev;
|
||||
* 8255 PARPORT
|
||||
*****************************************************************************************/
|
||||
typedef struct i8255 {
|
||||
PNP_INFO pnp;
|
||||
DEVICE* dev; /* backlink to device */
|
||||
t_stat (*write)(struct i8255* chip,int port,uint32 data);
|
||||
t_stat (*read)(struct i8255* chip,int port,uint32* data);
|
||||
t_stat (*reset)(struct i8255* chip);
|
||||
t_stat (*calla)(struct i8255* chip,int rw);
|
||||
t_stat (*callb)(struct i8255* chip,int rw);
|
||||
t_stat (*callc)(struct i8255* chip,int rw);
|
||||
t_stat (*ckmode)(struct i8255* chip,uint32 data);
|
||||
uint32 porta;
|
||||
uint32 last_porta; /* for edge detection */
|
||||
uint32 portb;
|
||||
uint32 last_portb; /* for edge detection */
|
||||
uint32 portc;
|
||||
uint32 last_portc; /* for edge detection */
|
||||
uint32 ctrl;
|
||||
PNP_INFO pnp;
|
||||
DEVICE* dev; /* backlink to device */
|
||||
t_stat (*write)(struct i8255* chip,int port,uint32 data);
|
||||
t_stat (*read)(struct i8255* chip,int port,uint32* data);
|
||||
t_stat (*reset)(struct i8255* chip);
|
||||
t_stat (*calla)(struct i8255* chip,int rw);
|
||||
t_stat (*callb)(struct i8255* chip,int rw);
|
||||
t_stat (*callc)(struct i8255* chip,int rw);
|
||||
t_stat (*ckmode)(struct i8255* chip,uint32 data);
|
||||
uint32 porta;
|
||||
uint32 last_porta; /* for edge detection */
|
||||
uint32 portb;
|
||||
uint32 last_portb; /* for edge detection */
|
||||
uint32 portc;
|
||||
uint32 last_portc; /* for edge detection */
|
||||
uint32 ctrl;
|
||||
} I8255;
|
||||
extern t_stat i8255_io(IOHANDLER* ioh,uint32* value,uint32 rw,uint32 mask);
|
||||
extern t_stat i8255_read(I8255* chip,int port,uint32* data);
|
||||
|
||||
Reference in New Issue
Block a user