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ALPHA, ALTAIR, AltairZ80, I7094, NOVA, PDP1, PDP10, PDP11, PDP18B, PDP8, SAGE, sigma, swtp6800, TX-0, VAX: Change tabs to spaces which had crept in over time
This commit is contained in:
118
SAGE/i8255.c
118
SAGE/i8255.c
@@ -32,75 +32,75 @@
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static t_stat i8255_error(const char* err)
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{
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sim_printf("I8255: Missing method '%s'\n",err);
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return STOP_IMPL;
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sim_printf("I8255: Missing method '%s'\n",err);
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return STOP_IMPL;
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}
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t_stat i8255_io(IOHANDLER* ioh,uint32* value,uint32 rw,uint32 mask)
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{
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int port = ioh->offset;
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I8255* chip = (I8255*)ioh->ctxt;
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if (rw==MEM_WRITE) {
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return chip->write ? chip->write(chip,port,*value) : i8255_error("write");
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} else {
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return chip->read ? chip->read(chip,port,value) : i8255_error("read");
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}
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int port = ioh->offset;
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I8255* chip = (I8255*)ioh->ctxt;
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if (rw==MEM_WRITE) {
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return chip->write ? chip->write(chip,port,*value) : i8255_error("write");
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} else {
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return chip->read ? chip->read(chip,port,value) : i8255_error("read");
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}
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}
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t_stat i8255_read(I8255* chip,int port,uint32* data)
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{
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t_stat rc;
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switch (port) {
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case 0:
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if (chip->calla && (rc=(*chip->calla)(chip,0)) != SCPE_OK) return rc;
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*data = chip->porta;
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return SCPE_OK;
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case 1:
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if (chip->callb && (rc=(*chip->callb)(chip,0)) != SCPE_OK) return rc;
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*data = chip->portb;
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return SCPE_OK;
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case 2:
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if (chip->callc && (rc=(*chip->callc)(chip,0)) != SCPE_OK) return rc;
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*data = chip->portc;
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return SCPE_OK;
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case 3:
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*data = 0xff; /* undefined */
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return SCPE_OK;
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default:
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return SCPE_IERR;
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}
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t_stat rc;
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switch (port) {
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case 0:
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if (chip->calla && (rc=(*chip->calla)(chip,0)) != SCPE_OK) return rc;
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*data = chip->porta;
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return SCPE_OK;
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case 1:
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if (chip->callb && (rc=(*chip->callb)(chip,0)) != SCPE_OK) return rc;
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*data = chip->portb;
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return SCPE_OK;
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case 2:
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if (chip->callc && (rc=(*chip->callc)(chip,0)) != SCPE_OK) return rc;
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*data = chip->portc;
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return SCPE_OK;
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case 3:
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*data = 0xff; /* undefined */
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return SCPE_OK;
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default:
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return SCPE_IERR;
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}
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}
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t_stat i8255_write(I8255* chip,int port,uint32 data)
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{
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t_stat rc;
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uint32 bit;
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switch(port) {
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case 0: /*port a*/
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chip->last_porta = chip->porta;
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chip->porta = data;
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return chip->calla ? (*chip->calla)(chip,1) : SCPE_OK;
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case 1: /*port b*/
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chip->last_portb = chip->portb;
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return chip->callb ? (*chip->callb)(chip,1) : SCPE_OK;
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case 2:
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chip->last_portc = chip->portc;
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chip->portc = data & 0xff;
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return chip->callc ? (*chip->callc)(chip,1) : SCPE_OK;
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case 3:
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if (data & 0x80) { /* mode set mode */
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if (chip->ckmode && (rc=chip->ckmode(chip,data))) return rc;
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chip->ctrl = data & 0x7f;
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return SCPE_OK;
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} else { /* bit set mode */
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chip->last_portc = chip->portc;
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bit = 1 << ((data & 0x0e)>>1);
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TRACE_PRINT2(DBG_PP_WRC,"WR PORTC %s bit=%x",data&1 ? "SET": "CLR",bit);
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if (data & 1) chip->portc |= bit; else chip->portc &= ~bit;
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chip->portc &= 0xff;
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return chip->callc ? (*chip->callc)(chip,1) : SCPE_OK;
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}
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default:
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return SCPE_IERR;
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}
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t_stat rc;
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uint32 bit;
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switch(port) {
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case 0: /*port a*/
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chip->last_porta = chip->porta;
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chip->porta = data;
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return chip->calla ? (*chip->calla)(chip,1) : SCPE_OK;
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case 1: /*port b*/
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chip->last_portb = chip->portb;
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return chip->callb ? (*chip->callb)(chip,1) : SCPE_OK;
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case 2:
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chip->last_portc = chip->portc;
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chip->portc = data & 0xff;
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return chip->callc ? (*chip->callc)(chip,1) : SCPE_OK;
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case 3:
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if (data & 0x80) { /* mode set mode */
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if (chip->ckmode && (rc=chip->ckmode(chip,data))) return rc;
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chip->ctrl = data & 0x7f;
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return SCPE_OK;
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} else { /* bit set mode */
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chip->last_portc = chip->portc;
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bit = 1 << ((data & 0x0e)>>1);
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TRACE_PRINT2(DBG_PP_WRC,"WR PORTC %s bit=%x",data&1 ? "SET": "CLR",bit);
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if (data & 1) chip->portc |= bit; else chip->portc &= ~bit;
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chip->portc &= 0xff;
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return chip->callc ? (*chip->callc)(chip,1) : SCPE_OK;
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}
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default:
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return SCPE_IERR;
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}
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}
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