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Intel-Systems: Update and cleanup components
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Bill Beech
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Mark Pizzolato
Mark Pizzolato
parent
fac5bc96fb
commit
6af0958209
275
Intel-Systems/common/i3214.c
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275
Intel-Systems/common/i3214.c
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/* i3214.c: Intel i3214 PICU adapter
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Copyright (c) 2019, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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12 OCT 19 - Original file.
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NOTES:
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These functions support a simulated i3214 interface device on an iSBC.
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The device had three physical I/O port which could be connected
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as needed. This device was replaced by the 8259.
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All I/O is via programmed I/O. The i3214 has a status port
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and two data port.
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save for now!
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A write to the status port can select some options for the device:
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Asynchronous Mode Instruction
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7 6 5 4 3 2 1 0
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+---+---+---+---+---+---+---+---+
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| S2 S1 EP PEN L2 L1 B2 B1|
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+---+---+---+---+---+---+---+---+
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Baud Rate Factor
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B2 0 1 0 1
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B1 0 0 1 1
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sync 1X 16X 64X
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mode
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Character Length
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L2 0 1 0 1
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L1 0 0 1 1
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5 6 7 8
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bits bits bits bits
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EP - A 1 in this bit position selects even parity.
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PEN - A 1 in this bit position enables parity.
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Number of Stop Bits
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S2 0 1 0 1
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S1 0 0 1 1
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invalid 1 1.5 2
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bit bits bits
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Command Instruction Format
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7 6 5 4 3 2 1 0
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+---+---+---+---+---+---+---+---+
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| EH IR RTS ER SBRK RxE DTR TxE|
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+---+---+---+---+---+---+---+---+
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TxE - A 1 in this bit position enables transmit.
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DTR - A 1 in this bit position forces *DTR to zero.
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RxE - A 1 in this bit position enables receive.
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SBRK - A 1 in this bit position forces TxD to zero.
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ER - A 1 in this bit position resets the error bits
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RTS - A 1 in this bit position forces *RTS to zero.
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IR - A 1 in this bit position returns the 8251 to Mode Instruction Format.
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EH - A 1 in this bit position enables search for sync characters.
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A read of the status port gets the port status:
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Status Read Format
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7 6 5 4 3 2 1 0
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+---+---+---+---+---+---+---+---+
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|DSR SD FE OE PE TxE RxR TxR|
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+---+---+---+---+---+---+---+---+
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TxR - A 1 in this bit position signals transmit ready to receive a character.
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RxR - A 1 in this bit position signals receiver has a character.
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TxE - A 1 in this bit position signals transmitter has no more characters to transmit.
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PE - A 1 in this bit signals a parity error.
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OE - A 1 in this bit signals an transmit overrun error.
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FE - A 1 in this bit signals a framing error.
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SD - A 1 in this bit position returns the 8251 to Mode Instruction Format.
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DSR - A 1 in this bit position signals *DSR is at zero.
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A read from the data port gets the typed character, a write
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to the data port writes the character to the device.
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*/
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#include "system_defs.h"
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// 3214 status bits
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/* external globals */
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
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/* globals */
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uint8 i3214_mask = 0;
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uint8 i3214_cnt = 0;
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uint8 i3214_ram[16];
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uint8 EPROM_enable = 1;
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uint8 BUS_OVERRIDE = 0;
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uint8 monitor_boot = 0x00;
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/* function prototypes */
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t_stat i3214_cfg(uint8 base, uint8 devnum);
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t_stat i3214_reset (DEVICE *dptr);
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t_stat i3214_reset_dev (uint8 devnum);
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t_stat i3214_svc (UNIT *uptr);
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uint8 i3214_do_mask(t_bool io, uint8 data, uint8 devnum);
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uint8 i3214_do_status(t_bool io, uint8 data, uint8 devnum);
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uint8 i3214_cpu_bus_override(t_bool io, uint8 data, uint8 devnum);
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uint8 i3214_monitor_do_boot(t_bool io, uint8 data, uint8 devnum);
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/* i3214 Standard I/O Data Structures */
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/* 1 i3214 device */
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UNIT i3214_unit[] = {
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{ UDATA (&i3214_svc, 0, 0), KBD_POLL_WAIT }
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};
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REG i3214_reg[] = {
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{ HRDATA (MASK0, i3214_mask, 8) },
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{ HRDATA (CNT0, i3214_cnt, 8) },
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{ HRDATA (RAM0, i3214_ram, 8) },
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{ NULL }
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};
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DEBTAB i3214_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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MTAB i3214_mod[] = {
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{ 0 }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE i3214_dev = {
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"I3214", //name
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i3214_unit, //units
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i3214_reg, //registers
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i3214_mod, //modifiers
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I3214_NUM, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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i3214_reset, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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0, //flags
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0, //dctrl
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i3214_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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// i3214 configuration
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t_stat i3214_cfg(uint8 base, uint8 devnum)
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{
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sim_printf(" i3214[%d]: at base port 0%02XH\n",
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devnum, base & 0xFF);
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reg_dev(i3214_do_mask, base, devnum);
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reg_dev(i3214_do_status, base + 1, devnum);
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reg_dev(i3214_cpu_bus_override, base + 2, devnum);
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reg_dev(i3214_monitor_do_boot, base + 3, devnum);
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return SCPE_OK;
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}
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/* Service routines to handle simulator functions */
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/* i3214_svc - actually gets char & places in buffer */
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t_stat i3214_svc (UNIT *uptr)
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{
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat i3214_reset (DEVICE *dptr)
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{
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uint8 devnum;
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for (devnum=0; devnum<I3214_NUM; devnum++) {
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i3214_reset_dev(devnum);
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sim_activate (&i3214_unit[devnum], i3214_unit[devnum].wait); /* activate unit */
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}
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return SCPE_OK;
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}
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t_stat i3214_reset_dev (uint8 devnum)
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{
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return SCPE_OK;
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}
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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// 3214 device routines
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uint8 i3214_do_mask(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) /* read status port */
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return i3214_mask;
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else
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i3214_mask = data;
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return 0;
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}
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uint8 i3214_do_status(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0)
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return 0;
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else {
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i3214_cnt--;
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}
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return 0;
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}
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uint8 i3214_cpu_bus_override(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) /* read status port */
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return 0;
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else
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BUS_OVERRIDE = data & 0x01;
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return 0;
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}
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uint8 i3214_monitor_do_boot(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) /* read status port */
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return monitor_boot;
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else
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monitor_boot = data;
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return 0;
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}
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/* end of i3214.c */
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