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Intel-Systems: Update and cleanup components
This commit is contained in:
Bill Beech
committed by
Mark Pizzolato
Mark Pizzolato
parent
fac5bc96fb
commit
6af0958209
@@ -1,4 +1,4 @@
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/* zx-200a.c: Intel double density disk adapter adapter
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/* zx-200a.c: ZENDEX single/double density disk adapter
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Copyright (c) 2010, William A. Beech
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@@ -127,7 +127,7 @@
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u3 -
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u4 -
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u5 - fdc number (board instance number).
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u5 -
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u6 - fdd number.
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The ZX-200A appears to the multibus system as if there were an iSBC-201
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@@ -139,12 +139,11 @@
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#include "system_defs.h" /* system header in system dir */
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#define DEBUG 0
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#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
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#define UNIT_WPMODE (1 << UNIT_V_WPMODE)
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#define FDD_NUM 4
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#define FDD_NUM 6
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//disk controoler operations
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#define DNOP 0x00 //disk no operation
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@@ -165,10 +164,10 @@
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#define RDY3 0x40 //FDD 3 ready
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//result type
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#define RERR 0x00 //FDC returned error
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#define ROK 0x02 //FDC returned ok
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#define ROK 0x00 //FDC error
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#define RCHG 0x02 //FDC OK OR disk changed
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// If result type is RERR then rbyte is
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// If result type is ROK then rbyte is
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#define RB0DR 0x01 //deleted record
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#define RB0CRC 0x02 //CRC error
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#define RB0SEK 0x04 //seek error
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@@ -178,7 +177,7 @@
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#define RB0WE 0x40 //write error
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#define RB0NR 0x80 //not ready
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// If result type is ROK then rbyte is
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// If result type is RCHG then rbyte is
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#define RB1RD2 0x10 //drive 2 ready
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#define RB1RD3 0x20 //drive 3 ready
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#define RB1RD0 0x40 //drive 0 ready
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@@ -193,38 +192,37 @@
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/* external function prototypes */
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extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8), uint16, uint8);
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
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extern uint8 multibus_get_mbyte(uint16 addr);
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extern uint16 multibus_get_mword(uint16 addr);
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extern void multibus_put_mbyte(uint16 addr, uint8 val);
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extern uint8 multibus_put_mword(uint16 addr, uint16 val);
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/* external globals */
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extern uint16 port; //port called in dev_table[port]
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extern int32 PCX;
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/* internal function prototypes */
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t_stat zx200a_reset(DEVICE *dptr, uint16 base);
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void zx200a_reset1(uint8);
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t_stat isbc064_cfg(uint16 base);
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t_stat zx200a_reset(DEVICE *dptr);
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void zx200a_reset1(void);
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t_stat zx200a_attach (UNIT *uptr, CONST char *cptr);
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t_stat zx200a_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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uint8 zx200a0(t_bool io, uint8 data);
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uint8 zx200a1(t_bool io, uint8 data);
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uint8 zx200a2(t_bool io, uint8 data);
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uint8 zx200a3(t_bool io, uint8 data);
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uint8 zx200a7(t_bool io, uint8 data);
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void zx200a_diskio(uint8 fdcnum);
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uint8 zx200ar0SD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar0DD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar1SD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar1DD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar2SD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar2DD(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar3(t_bool io, uint8 data, uint8 devnum);
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uint8 zx200ar7(t_bool io, uint8 data, uint8 devnum);
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void zx200a_diskio(void);
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/* globals */
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int32 zx200a_fdcnum = 0; //actual number of ZX-200A instances + 1
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typedef struct { //FDD definition
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// uint8 *buf;
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int t0;
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int rdy;
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// int t0;
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// int rdy;
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uint8 sec;
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uint8 cyl;
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uint8 dd;
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@@ -235,7 +233,8 @@ typedef struct { //FDD definition
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typedef struct { //FDC definition
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uint16 baseport; //FDC base port
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uint16 iopb; //FDC IOPB
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uint8 stat; //FDC status
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uint8 DDstat; //FDC DD status
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uint8 SDstat; //FDC SD status
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uint8 rdychg; //FDC ready change
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uint8 rtype; //FDC result type
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uint8 rbyte0; //FDC result byte for type 00
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@@ -244,36 +243,26 @@ typedef struct { //FDC definition
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FDDDEF fdd[FDD_NUM]; //indexed by the FDD number
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} FDCDEF;
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FDCDEF zx200a[4]; //indexed by the zx200a instance number
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FDCDEF zx200a;
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/* ZX-200A Standard I/O Data Structures */
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UNIT zx200a_unit[] = {
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, MDSDD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, MDSDD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, MDSDD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF, MDSDD), 20 }
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSDD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSSD), 20 },
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{ UDATA (0, UNIT_ATTABLE+UNIT_DISABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_FIX, MDSSD), 20 },
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};
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REG zx200a_reg[] = {
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{ HRDATA (STAT0, zx200a[0].stat, 8) }, /* zx200a 0 status */
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{ HRDATA (RTYP0, zx200a[0].rtype, 8) }, /* zx200a 0 result type */
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{ HRDATA (RBYT0A, zx200a[0].rbyte0, 8) }, /* zx200a 0 result byte 0 */
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{ HRDATA (RBYT0B, zx200a[0].rbyte1, 8) }, /* zx200a 0 result byte 1 */
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{ HRDATA (INTFF0, zx200a[0].intff, 8) }, /* zx200a 0 interrupt f/f */
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{ HRDATA (STAT1, zx200a[1].stat, 8) }, /* zx200a 1 status */
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{ HRDATA (RTYP1, zx200a[1].rtype, 8) }, /* zx200a 1 result type */
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{ HRDATA (RBYT1A, zx200a[1].rbyte0, 8) }, /* zx200a 1 result byte 0 */
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{ HRDATA (RBYT1B, zx200a[1].rbyte1, 8) }, /* zx200a 1 result byte 1 */
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{ HRDATA (INTFF1, zx200a[1].intff, 8) }, /* zx200a 1 interrupt f/f */
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{ HRDATA (STAT2, zx200a[2].stat, 8) }, /* zx200a 2 status */
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{ HRDATA (RTYP2, zx200a[2].rtype, 8) }, /* zx200a 2 result type */
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{ HRDATA (RBYT2A, zx200a[2].rbyte0, 8) }, /* zx200a 2 result byte 0 */
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{ HRDATA (RBYT2B, zx200a[2].rbyte1, 8) }, /* zx200a 2 result byte 1 */
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{ HRDATA (INTFF2, zx200a[2].intff, 8) }, /* zx200a 2 interrupt f/f */
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{ HRDATA (STAT3, zx200a[3].stat, 8) }, /* zx200a 3 status */
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{ HRDATA (RTYP3, zx200a[3].rtype, 8) }, /* zx200a 3 result type */
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{ HRDATA (RBYT3A, zx200a[3].rbyte0, 8) }, /* zx200a 3 result byte 0 */
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{ HRDATA (RBYT3B, zx200a[3].rbyte1, 8) }, /* zx200a 3 result byte 1 */
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{ HRDATA (INTFF3, zx200a[3].intff, 8) }, /* zx200a 3 interrupt f/f */
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{ HRDATA (STAT0, zx200a.SDstat, 8) }, /* zx200a 0 SD status */
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{ HRDATA (STAT0, zx200a.DDstat, 8) }, /* zx200a 0 DD status */
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{ HRDATA (RTYP0, zx200a.rtype, 8) }, /* zx200a 0 result type */
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{ HRDATA (RBYT0A, zx200a.rbyte0, 8) }, /* zx200a 0 result byte 0 */
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{ HRDATA (RBYT0B, zx200a.rbyte1, 8) }, /* zx200a 0 result byte 1 */
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{ HRDATA (INTFF0, zx200a.intff, 8) }, /* zx200a 0 interrupt f/f */
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{ NULL }
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};
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@@ -309,14 +298,15 @@ DEVICE zx200a_dev = {
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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NULL, //reset
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zx200a_reset, //reset
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NULL, //boot
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&zx200a_attach, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG+DEV_DISABLE+DEV_DIS, //flags
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DEBUG_flow + DEBUG_read + DEBUG_write, //dctrl
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zx200a_debug, //debflags
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// DEBUG_flow + DEBUG_read + DEBUG_write, //dctrl
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0, //dctrl
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zx200a_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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@@ -327,81 +317,90 @@ DEVICE zx200a_dev = {
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/* Service routines to handle simulator functions */
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/* Reset routine */
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// configuration routine
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t_stat zx200a_reset(DEVICE *dptr, uint16 base)
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t_stat zx200a_cfg(uint8 base)
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{
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int32 i;
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UNIT *uptr;
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sim_printf(" ZX-200A FDC Board");
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if (ZX200A_NUM) {
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sim_printf(" - Found on Port %02X\n", base);
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sim_printf(" ZX200A-%d: Hardware Reset\n", zx200a_fdcnum);
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sim_printf(" ZX200A-%d: Registered at %04X\n", zx200a_fdcnum, base);
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//register base port address for this FDC instance
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zx200a[zx200a_fdcnum].baseport = base;
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//register I/O port addresses for each function
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reg_dev(zx200a0, base, zx200a_fdcnum);
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reg_dev(zx200a1, base + 1, zx200a_fdcnum);
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reg_dev(zx200a2, base + 2, zx200a_fdcnum);
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reg_dev(zx200a3, base + 3, zx200a_fdcnum);
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reg_dev(zx200a7, base + 7, zx200a_fdcnum);
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reg_dev(zx200a0, base+16, zx200a_fdcnum);
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reg_dev(zx200a1, base+16 + 1, zx200a_fdcnum);
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reg_dev(zx200a2, base+16 + 2, zx200a_fdcnum);
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reg_dev(zx200a3, base+16 + 3, zx200a_fdcnum);
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reg_dev(zx200a7, base+16 + 7, zx200a_fdcnum);
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// one-time initialization for all FDDs for this FDC instance
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for (i = 0; i < FDD_NUM; i++) {
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uptr = zx200a_dev.units + i;
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uptr->u5 = zx200a_fdcnum; //fdc device number
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uptr->u6 = i; //fdd unit number
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uptr->flags |= UNIT_WPMODE; //set WP in unit flags
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}
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zx200a_reset1(zx200a_fdcnum);
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zx200a_fdcnum++;
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} else
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sim_printf(" - Not Found\n");
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sim_printf(" zx200a: at base 0%02XH\n",
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base);
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//register I/O port addresses for each function
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reg_dev(zx200ar0DD, base, 0); //read status
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reg_dev(zx200ar1DD, base + 1, 0); //read rslt type/write IOPB addr-l
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reg_dev(zx200ar2DD, base + 2, 0); //write IOPB addr-h and start
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reg_dev(zx200ar3, base + 3, 0); //read rstl byte
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reg_dev(zx200ar7, base + 7, 0); //write reset zx200a
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reg_dev(zx200ar0SD, base + 16, 0); //read status
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reg_dev(zx200ar1SD, base + 17, 0); //read rslt type/write IOPB addr-l
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reg_dev(zx200ar2SD, base + 18, 0); //write IOPB addr-h and start
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reg_dev(zx200ar3, base + 19, 0); //read rstl byte
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reg_dev(zx200ar7, base + 23, 0); //write reset zx200a
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// one-time initialization for all FDDs
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for (i = 0; i < FDD_NUM; i++) {
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uptr = zx200a_dev.units + i;
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uptr->u6 = i; //fdd unit number
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}
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat zx200a_reset(DEVICE *dptr)
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{
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zx200a_reset1(); //software reset
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return SCPE_OK;
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}
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/* Software reset routine */
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void zx200a_reset1(uint8 fdcnum)
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void zx200a_reset1(void)
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{
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int32 i;
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UNIT *uptr;
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sim_printf(" ZX-200A-%d: Initializing\n", fdcnum);
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zx200a[fdcnum].stat = 0; //clear status
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zx200a.DDstat = 0; //clear the FDC DD status
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zx200a.SDstat = 0; //clear the FDC SD status
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for (i = 0; i < FDD_NUM; i++) { /* handle all units */
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uptr = zx200a_dev.units + i;
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zx200a[fdcnum].stat |= FDCPRE | FDCDD; //set the FDC status
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zx200a[fdcnum].rtype = ROK;
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if (uptr->capac == 0) { /* if not configured */
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sim_printf(" ZX-200A%d: Configured, Status=%02X Not attached\n", i, zx200a[fdcnum].stat);
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zx200a.DDstat |= FDCPRE | FDCDD; //set the FDC DD status
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zx200a.SDstat |= FDCPRE; //set the FDC SD status
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if (i <= 3 ) { //first 4 are DD, last 2 are SD
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zx200a.fdd[i].dd = 1; //set double density
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} else {
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zx200a.fdd[i].dd = 0; //set single density
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}
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zx200a.rtype = ROK;
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zx200a.rbyte0 = 0; //set no error
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if (uptr->flags & UNIT_ATT) { /* if attached */
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switch(i){
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case 0:
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zx200a[fdcnum].stat |= RDY0; //set FDD 0 ready
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zx200a[fdcnum].rbyte1 |= RB1RD0;
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zx200a.DDstat |= RDY0; //set FDD 0 ready
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zx200a.rbyte1 |= RB1RD0;
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break;
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case 1:
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zx200a[fdcnum].stat |= RDY1; //set FDD 1 ready
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zx200a[fdcnum].rbyte1 |= RB1RD1;
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zx200a.DDstat |= RDY1; //set FDD 1 ready
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zx200a.rbyte1 |= RB1RD1;
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break;
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case 2:
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zx200a[fdcnum].stat |= RDY2; //set FDD 2 ready
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zx200a[fdcnum].rbyte1 |= RB1RD2;
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zx200a.DDstat |= RDY2; //set FDD 2 ready
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zx200a.rbyte1 |= RB1RD2;
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break;
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case 3:
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zx200a[fdcnum].stat |= RDY3; //set FDD 3 ready
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zx200a[fdcnum].rbyte1 |= RB1RD3;
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zx200a.DDstat |= RDY3; //set FDD 3 ready
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zx200a.rbyte1 |= RB1RD3;
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break;
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case 4:
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zx200a.SDstat |= RDY0; //set FDD 0 ready
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zx200a.rbyte1 |= RB1RD0;
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break;
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case 5:
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zx200a.SDstat |= RDY1; //set FDD 1 ready
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zx200a.rbyte1 |= RB1RD1;
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break;
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}
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zx200a[fdcnum].rdychg = 0;
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sim_printf(" ZX-200A%d: Configured, Status=%02X Attached to %s\n",
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i, zx200a[fdcnum].stat, uptr->filename);
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zx200a.rdychg = 0;
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}
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}
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}
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@@ -411,52 +410,42 @@ void zx200a_reset1(uint8 fdcnum)
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t_stat zx200a_attach (UNIT *uptr, CONST char *cptr)
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{
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t_stat r;
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uint8 fdcnum, fddnum;
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uint8 fddnum;
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sim_debug (DEBUG_flow, &zx200a_dev, " zx200a_attach: Entered with cptr=%s\n", cptr);
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if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
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sim_printf(" zx200a_attach: Attach error\n");
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sim_printf(" zx200a_attach: Attach error %d\n", r);
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return r;
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}
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fdcnum = uptr->u5;
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fddnum = uptr->u6;
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switch(fddnum){
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case 0:
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zx200a[fdcnum].stat |= RDY0; //set FDD 0 ready
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zx200a[fdcnum].rbyte1 |= RB1RD0;
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zx200a.DDstat |= RDY0; //set FDD 0 ready
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zx200a.rbyte1 |= RB1RD0;
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break;
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case 1:
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zx200a[fdcnum].stat |= RDY1; //set FDD 1 ready
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zx200a[fdcnum].rbyte1 |= RB1RD1;
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zx200a.DDstat |= RDY1; //set FDD 1 ready
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zx200a.rbyte1 |= RB1RD1;
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break;
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case 2:
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zx200a[fdcnum].stat |= RDY2; //set FDD 2 ready
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zx200a[fdcnum].rbyte1 |= RB1RD2;
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zx200a.DDstat |= RDY2; //set FDD 2 ready
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zx200a.rbyte1 |= RB1RD2;
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break;
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case 3:
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zx200a[fdcnum].stat |= RDY3; //set FDD 3 ready
|
||||
zx200a[fdcnum].rbyte1 |= RB1RD3;
|
||||
zx200a.DDstat |= RDY3; //set FDD 3 ready
|
||||
zx200a.rbyte1 |= RB1RD3;
|
||||
break;
|
||||
case 4:
|
||||
zx200a.SDstat |= RDY0; //set FDD 0 ready
|
||||
zx200a.rbyte1 |= RB1RD0;
|
||||
break;
|
||||
case 5:
|
||||
zx200a.SDstat |= RDY1; //set FDD 1 ready
|
||||
zx200a.rbyte1 |= RB1RD1;
|
||||
break;
|
||||
}
|
||||
zx200a[fdcnum].rtype = ROK;
|
||||
if (uptr->capac == 256256 && (fddnum == 2 || fddnum == 3)) { /* 8" 256K SSSD */
|
||||
zx200a[fdcnum].fdd[fddnum].dd = 0;
|
||||
// zx200a[fdcnum].fdd[fddnum].maxcyl = 77;
|
||||
// zx200a[fdcnum].fdd[fddnum].maxsec = 26;
|
||||
zx200a[fdcnum].fdd[fddnum].sec = 1;
|
||||
zx200a[fdcnum].fdd[fddnum].cyl = 0;
|
||||
}
|
||||
else if (uptr->capac == 512512) { /* 8" 512K SSDD */
|
||||
zx200a[fdcnum].fdd[fddnum].dd = 1;
|
||||
// zx200a[fdcnum].fdd[fddnum].maxcyl = 77;
|
||||
// zx200a[fdcnum].fdd[fddnum].maxsec = 52;
|
||||
zx200a[fdcnum].fdd[fddnum].sec = 1;
|
||||
zx200a[fdcnum].fdd[fddnum].cyl = 0;
|
||||
} else
|
||||
sim_printf(" ZX-200A-%d: Invalid disk image or SD on drive 0 or 1\n", fdcnum);
|
||||
sim_printf(" ZX-200A-%d: Configured %d bytes, Attached to %s\n",
|
||||
fdcnum, uptr->capac, uptr->filename);
|
||||
sim_debug (DEBUG_flow, &zx200a_dev, " ZX-200A_attach: Done\n");
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = 0; //set no error
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
@@ -464,141 +453,134 @@ t_stat zx200a_attach (UNIT *uptr, CONST char *cptr)
|
||||
|
||||
t_stat zx200a_set_mode (UNIT *uptr, int32 val, CONST char *cptr, void *desc)
|
||||
{
|
||||
// sim_debug (DEBUG_flow, &zx200a_dev, " zx200a_set_mode: Entered with val=%08XH uptr->flags=%08X\n",
|
||||
// val, uptr->flags);
|
||||
if (uptr->flags & UNIT_ATT)
|
||||
return sim_messagef (SCPE_ALATT, "%s is already attached to %s\n", sim_uname(uptr), uptr->filename);
|
||||
if (val & UNIT_WPMODE) { /* write protect */
|
||||
uptr->flags |= val;
|
||||
} else { /* read write */
|
||||
uptr->flags &= ~val;
|
||||
}
|
||||
// sim_debug (DEBUG_flow, &zx200a_dev, " zx200a_set_mode: Done\n");
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
uint8 zx200_get_dn(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0; i<ZX200A_NUM; i++)
|
||||
if ((port >= zx200a[i].baseport && port <= zx200a[i].baseport + 7) ||
|
||||
(port >= zx200a[i].baseport+16 && port <= zx200a[i].baseport+16 + 7))
|
||||
return i;
|
||||
sim_printf("zx200_get_dn: port %04X not in zx200 device table\n", port);
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
/* I/O instruction handlers, called from the CPU module when an
|
||||
IN or OUT instruction is issued.
|
||||
*/
|
||||
|
||||
/* zx200a control port functions */
|
||||
|
||||
uint8 zx200a0(t_bool io, uint8 data)
|
||||
uint8 zx200ar0SD(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
uint8 fdcnum;
|
||||
|
||||
if ((fdcnum = zx200_get_dn()) != 0xFF) {
|
||||
if (io == 0) { /* read ststus*/
|
||||
if (DEBUG)
|
||||
sim_printf("\n zx-200a0-%d: 0x78/88 returned status=%02X PCX=%04X",
|
||||
fdcnum, zx200a[fdcnum].stat, PCX);
|
||||
return zx200a[fdcnum].stat;
|
||||
}
|
||||
if (io == 0) { /* read ststus*/
|
||||
return zx200a.SDstat;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8 zx200a1(t_bool io, uint8 data)
|
||||
uint8 zx200ar0DD(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
uint8 fdcnum;
|
||||
|
||||
if ((fdcnum = zx200_get_dn()) != 0xFF) {
|
||||
if (io == 0) { /* read operation */
|
||||
zx200a[fdcnum].intff = 0; //clear interrupt FF
|
||||
zx200a[fdcnum].stat &= ~FDCINT;
|
||||
if (DEBUG)
|
||||
sim_printf("\n zx-200a1-%d: 0x79/89 returned rtype=%02X intff=%02X status=%02X PCX=%04X",
|
||||
fdcnum, zx200a[fdcnum].rtype, zx200a[fdcnum].intff, zx200a[fdcnum].stat, PCX);
|
||||
return zx200a[fdcnum].rtype;
|
||||
} else { /* write control port */
|
||||
zx200a[fdcnum].iopb = data;
|
||||
if (DEBUG)
|
||||
sim_printf("\n zx-200a1-%d: 0x79/88 IOPB low=%02X PCX=%04X",
|
||||
fdcnum, data, PCX);
|
||||
}
|
||||
if (io == 0) { /* read ststus*/
|
||||
return zx200a.DDstat;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8 zx200a2(t_bool io, uint8 data)
|
||||
uint8 zx200ar1SD(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
uint8 fdcnum;
|
||||
|
||||
if ((fdcnum = zx200_get_dn()) != 0xFF) {
|
||||
if (io == 0) { /* read data port */
|
||||
;
|
||||
} else { /* write data port */
|
||||
zx200a[fdcnum].iopb |= (data << 8);
|
||||
if (DEBUG)
|
||||
sim_printf("\n zx-200a2-%d: 0x7A/8A IOPB=%04X PCX=%04X",
|
||||
fdcnum, zx200a[fdcnum].iopb, PCX);
|
||||
zx200a_diskio(fdcnum);
|
||||
if (zx200a[fdcnum].intff)
|
||||
zx200a[fdcnum].stat |= FDCINT;
|
||||
if (io == 0) { /* read operation */
|
||||
zx200a.intff = 0; //clear interrupt FF
|
||||
if (zx200a.intff)
|
||||
zx200a.SDstat &= ~FDCINT;
|
||||
if (zx200a.rdychg) {
|
||||
zx200a.rtype = ROK;
|
||||
return zx200a.rtype;
|
||||
} else {
|
||||
zx200a.rtype = ROK;
|
||||
return zx200a.rtype;
|
||||
}
|
||||
} else { /* write control port */
|
||||
zx200a.iopb = data;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8 zx200a3(t_bool io, uint8 data)
|
||||
uint8 zx200ar1DD(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
uint8 fdcnum;
|
||||
if (io == 0) { /* read operation */
|
||||
zx200a.intff = 0; //clear interrupt FF
|
||||
if (zx200a.intff)
|
||||
zx200a.DDstat &= ~FDCINT;
|
||||
if (zx200a.rdychg) {
|
||||
zx200a.rtype = ROK;
|
||||
return zx200a.rtype;
|
||||
} else {
|
||||
zx200a.rtype = ROK;
|
||||
return zx200a.rtype;
|
||||
}
|
||||
} else { /* write control port */
|
||||
zx200a.iopb = data;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
if ((fdcnum = zx200_get_dn()) != 0xFF) {
|
||||
if (io == 0) { /* read data port */
|
||||
if (zx200a[fdcnum].rtype == 0) {
|
||||
if (DEBUG)
|
||||
sim_printf("\n zx200a3-%d: 0x7B/8B returned rbyte0=%02X PCX=%04X",
|
||||
fdcnum, zx200a[fdcnum].rbyte0, PCX);
|
||||
return zx200a[fdcnum].rbyte0;
|
||||
uint8 zx200ar2SD(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
if (io == 0) { /* read data port */
|
||||
;
|
||||
} else { /* write data port */
|
||||
zx200a.iopb |= (data << 8);
|
||||
zx200a_diskio();
|
||||
if (zx200a.intff)
|
||||
zx200a.SDstat |= FDCINT;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8 zx200ar2DD(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
if (io == 0) { /* read data port */
|
||||
;
|
||||
} else { /* write data port */
|
||||
zx200a.iopb |= (data << 8);
|
||||
zx200a_diskio();
|
||||
if (zx200a.intff)
|
||||
zx200a.DDstat |= FDCINT;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8 zx200ar3(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
if (io == 0) { /* read data port */
|
||||
if (zx200a.rtype == 0) {
|
||||
return zx200a.rbyte0;
|
||||
} else {
|
||||
if (zx200a.rdychg) {
|
||||
return zx200a.rbyte1;
|
||||
} else {
|
||||
if (zx200a[fdcnum].rdychg) {
|
||||
if (DEBUG)
|
||||
sim_printf("\n zx200a3-%d: 0x7B/8B returned rbyte1=%02X PCX=%04X",
|
||||
fdcnum, zx200a[fdcnum].rbyte1, PCX);
|
||||
return zx200a[fdcnum].rbyte1;
|
||||
} else {
|
||||
if (DEBUG)
|
||||
sim_printf("\n zx200a3-%d: 0x7B/8B returned rbytex=%02X PCX=%04X",
|
||||
fdcnum, 0, PCX);
|
||||
return 0;
|
||||
}
|
||||
return zx200a.rbyte0;
|
||||
}
|
||||
} else { /* write data port */
|
||||
; //stop diskette operation
|
||||
}
|
||||
} else { /* write data port */
|
||||
; //stop diskette operation
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* reset ZX-200A */
|
||||
uint8 zx200a7(t_bool io, uint8 data)
|
||||
uint8 zx200ar7(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
uint8 fdcnum;
|
||||
|
||||
if ((fdcnum = zx200_get_dn()) != 0xFF) {
|
||||
if (io == 0) { /* read data port */
|
||||
;
|
||||
} else { /* write data port */
|
||||
zx200a_reset1(fdcnum);
|
||||
}
|
||||
if (io == 0) { /* read data port */
|
||||
;
|
||||
} else { /* write data port */
|
||||
zx200a_reset1();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
// perform the actual disk I/O operation
|
||||
|
||||
void zx200a_diskio(uint8 fdcnum)
|
||||
void zx200a_diskio(void)
|
||||
{
|
||||
uint8 cw, di, nr, ta, sa, data, nrptr;
|
||||
uint16 ba;
|
||||
@@ -609,62 +591,75 @@ void zx200a_diskio(uint8 fdcnum)
|
||||
uint8 *fbuf;
|
||||
|
||||
//parse the IOPB
|
||||
cw = multibus_get_mbyte(zx200a[fdcnum].iopb);
|
||||
di = multibus_get_mbyte(zx200a[fdcnum].iopb + 1);
|
||||
nr = multibus_get_mbyte(zx200a[fdcnum].iopb + 2);
|
||||
ta = multibus_get_mbyte(zx200a[fdcnum].iopb + 3);
|
||||
sa = multibus_get_mbyte(zx200a[fdcnum].iopb + 4);
|
||||
ba = multibus_get_mword(zx200a[fdcnum].iopb + 5);
|
||||
cw = multibus_get_mbyte(zx200a.iopb);
|
||||
di = multibus_get_mbyte(zx200a.iopb + 1);
|
||||
nr = multibus_get_mbyte(zx200a.iopb + 2);
|
||||
ta = multibus_get_mbyte(zx200a.iopb + 3);
|
||||
sa = multibus_get_mbyte(zx200a.iopb + 4);
|
||||
ba = multibus_get_mbyte(zx200a.iopb + 5);
|
||||
ba |= (multibus_get_mbyte(zx200a.iopb + 6) << 8);
|
||||
fddnum = (di & 0x30) >> 4;
|
||||
uptr = zx200a_dev.units + fddnum;
|
||||
fbuf = (uint8 *) (zx200a_dev.units + fddnum)->filebuf;
|
||||
if (DEBUG) {
|
||||
sim_printf("\n zx200a-%d: zx200a_diskio IOPB=%04X FDD=%02X STAT=%02X",
|
||||
fdcnum, zx200a[fdcnum].iopb, fddnum, zx200a[fdcnum].stat);
|
||||
sim_printf("\n zx200a-%d: cw=%02X di=%02X nr=%02X ta=%02X sa=%02X ba=%04X",
|
||||
fdcnum, cw, di, nr, ta, sa, ba);
|
||||
}
|
||||
fbuf = (uint8 *) uptr->filebuf;
|
||||
//check for not ready
|
||||
switch(fddnum) {
|
||||
case 0:
|
||||
if ((zx200a[fdcnum].stat & RDY0) == 0) {
|
||||
zx200a[fdcnum].rtype = RERR;
|
||||
zx200a[fdcnum].rbyte0 = RB0NR;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a-%d: Ready error on drive %d", fdcnum, fddnum);
|
||||
if ((zx200a.DDstat & RDY0) == 0) {
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = RB0NR;
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
if ((zx200a[fdcnum].stat & RDY1) == 0) {
|
||||
zx200a[fdcnum].rtype = RERR;
|
||||
zx200a[fdcnum].rbyte0 = RB0NR;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a-%d: Ready error on drive %d", fdcnum, fddnum);
|
||||
if ((zx200a.DDstat & RDY1) == 0) {
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = RB0NR;
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
if ((zx200a[fdcnum].stat & RDY2) == 0) {
|
||||
zx200a[fdcnum].rtype = RERR;
|
||||
zx200a[fdcnum].rbyte0 = RB0NR;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a-%d: Ready error on drive %d", fdcnum, fddnum);
|
||||
if ((zx200a.DDstat & RDY2) == 0) {
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = RB0NR;
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
if ((zx200a[fdcnum].stat & RDY3) == 0) {
|
||||
zx200a[fdcnum].rtype = RERR;
|
||||
zx200a[fdcnum].rbyte0 = RB0NR;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a-%d: Ready error on drive %d", fdcnum, fddnum);
|
||||
if ((zx200a.DDstat & RDY3) == 0) {
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = RB0NR;
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
if ((zx200a.SDstat & RDY0) == 0) {
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = RB0NR;
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
case 5:
|
||||
if ((zx200a.SDstat & RDY1) == 0) {
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = RB0NR;
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a: Ready error on drive %d", fddnum);
|
||||
return;
|
||||
}
|
||||
break;
|
||||
}
|
||||
//check for address error
|
||||
if (zx200a[fdcnum].fdd[fddnum].dd == 1) {
|
||||
if (zx200a.fdd[fddnum].dd == 1) {
|
||||
if (
|
||||
((di & 0x07) != DHOME) && (
|
||||
(sa > MAXSECDD) ||
|
||||
@@ -672,13 +667,14 @@ void zx200a_diskio(uint8 fdcnum)
|
||||
(sa == 0) ||
|
||||
(ta > MAXTRK)
|
||||
)) {
|
||||
zx200a[fdcnum].rtype = RERR;
|
||||
zx200a[fdcnum].rbyte0 = RB0ADR;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a-%d: Address error on drive %d", fdcnum, fddnum);
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = RB0ADR;
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
sim_printf("\n ZX200A: FDD %d - Address error sa=%02X nr=%02X ta=%02X PCX=%04X",
|
||||
fddnum, sa, nr, ta, PCX);
|
||||
return;
|
||||
}
|
||||
} else if (zx200a[fdcnum].fdd[fddnum].dd == 0) {
|
||||
} else {
|
||||
if (
|
||||
((di & 0x07) != DHOME) && (
|
||||
(sa > MAXSECSD) ||
|
||||
@@ -686,45 +682,50 @@ void zx200a_diskio(uint8 fdcnum)
|
||||
(sa == 0) ||
|
||||
(ta > MAXTRK)
|
||||
)) {
|
||||
zx200a[fdcnum].rtype = RERR;
|
||||
zx200a[fdcnum].rbyte0 = RB0ADR;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a-%d: Address error on drive %d", fdcnum, fddnum);
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = RB0ADR;
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
sim_printf("\n ZX200A: FDD %d - Address error sa=%02X nr=%02X ta=%02X PCX=%04X",
|
||||
fddnum, sa, nr, ta, PCX);
|
||||
return;
|
||||
}
|
||||
}
|
||||
switch (di & 0x07) {
|
||||
case DNOP:
|
||||
zx200a[fdcnum].rtype = ROK;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = 0; //set no error
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
break;
|
||||
case DSEEK:
|
||||
zx200a[fdcnum].fdd[fddnum].sec = sa;
|
||||
zx200a[fdcnum].fdd[fddnum].cyl = ta;
|
||||
zx200a[fdcnum].rtype = ROK;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
zx200a.fdd[fddnum].sec = sa;
|
||||
zx200a.fdd[fddnum].cyl = ta;
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = 0; //set no error
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
break;
|
||||
case DHOME:
|
||||
zx200a[fdcnum].fdd[fddnum].sec = sa;
|
||||
zx200a[fdcnum].fdd[fddnum].cyl = 0;
|
||||
zx200a[fdcnum].rtype = ROK;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
zx200a.fdd[fddnum].sec = sa;
|
||||
zx200a.fdd[fddnum].cyl = 0;
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = 0; //set no error
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
break;
|
||||
case DVCRC:
|
||||
zx200a[fdcnum].rtype = ROK;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = 0; //set no error
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
break;
|
||||
case DFMT:
|
||||
//check for WP
|
||||
if(uptr->flags & UNIT_WPMODE) {
|
||||
zx200a[fdcnum].rtype = RERR;
|
||||
zx200a[fdcnum].rbyte0 = RB0WP;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a-%d: Write protect error 1 on drive %d", fdcnum, fddnum);
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = RB0WP;
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a: Write protect error 1 on drive %d", fddnum);
|
||||
return;
|
||||
}
|
||||
fmtb = multibus_get_mbyte(ba); //get the format byte
|
||||
if (zx200a[fdcnum].fdd[fddnum].dd == 1) {
|
||||
if (zx200a.fdd[fddnum].dd == 1) {
|
||||
//calculate offset into DD disk image
|
||||
dskoff = ((ta * MAXSECDD) + (sa - 1)) * 128;
|
||||
for(i=0; i<=((uint32)(MAXSECDD) * 128); i++) {
|
||||
@@ -737,21 +738,19 @@ void zx200a_diskio(uint8 fdcnum)
|
||||
*(fbuf + (dskoff + i)) = fmtb;
|
||||
}
|
||||
}
|
||||
zx200a[fdcnum].rtype = ROK;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = 0; //set no error
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
break;
|
||||
case DREAD:
|
||||
nrptr = 0;
|
||||
while(nrptr < nr) {
|
||||
//calculate offset into disk image
|
||||
if (zx200a[fdcnum].fdd[fddnum].dd == 1) {
|
||||
if (zx200a.fdd[fddnum].dd == 1) {
|
||||
dskoff = ((ta * MAXSECDD) + (sa - 1)) * 128;
|
||||
} else {
|
||||
dskoff = ((ta * MAXSECSD) + (sa - 1)) * 128;
|
||||
}
|
||||
if (DEBUG)
|
||||
sim_printf("\n isbc202-%d: cw=%02X di=%02X nr=%02X ta=%02X sa=%02X ba=%04X dskoff=%06X",
|
||||
fdcnum, cw, di, nr, ta, sa, ba, dskoff);
|
||||
//copy sector from image to RAM
|
||||
for (i=0; i<128; i++) {
|
||||
data = *(fbuf + (dskoff + i));
|
||||
@@ -761,29 +760,27 @@ void zx200a_diskio(uint8 fdcnum)
|
||||
ba+=0x80;
|
||||
nrptr++;
|
||||
}
|
||||
zx200a[fdcnum].rtype = ROK;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = 0; //set no error
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
break;
|
||||
case DWRITE:
|
||||
//check for WP
|
||||
if(uptr->flags & UNIT_WPMODE) {
|
||||
zx200a[fdcnum].rtype = RERR;
|
||||
zx200a[fdcnum].rbyte0 = RB0WP;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a-%d: Write protect error 2 on drive %d", fdcnum, fddnum);
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = RB0WP;
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
sim_printf("\n zx200a: Write protect error 2 on drive %d", fddnum);
|
||||
return;
|
||||
}
|
||||
nrptr = 0;
|
||||
while(nrptr < nr) {
|
||||
//calculate offset into disk image
|
||||
if (zx200a[fdcnum].fdd[fddnum].dd == 1) {
|
||||
if (zx200a.fdd[fddnum].dd == 1) {
|
||||
dskoff = ((ta * MAXSECDD) + (sa - 1)) * 128;
|
||||
} else {
|
||||
dskoff = ((ta * MAXSECSD) + (sa - 1)) * 128;
|
||||
}
|
||||
if (DEBUG)
|
||||
sim_printf("\n isbc202-%d: cw=%02X di=%02X nr=%02X ta=%02X sa=%02X ba=%04X dskoff=%06X",
|
||||
fdcnum, cw, di, nr, ta, sa, ba, dskoff);
|
||||
for (i=0; i<128; i++) { //copy sector from image to RAM
|
||||
data = multibus_get_mbyte(ba + i);
|
||||
*(fbuf + (dskoff + i)) = data;
|
||||
@@ -792,11 +789,12 @@ void zx200a_diskio(uint8 fdcnum)
|
||||
ba+=0x80;
|
||||
nrptr++;
|
||||
}
|
||||
zx200a[fdcnum].rtype = ROK;
|
||||
zx200a[fdcnum].intff = 1; //set interrupt FF
|
||||
zx200a.rtype = ROK;
|
||||
zx200a.rbyte0 = 0; //set no error
|
||||
zx200a.intff = 1; //set interrupt FF
|
||||
break;
|
||||
default:
|
||||
sim_printf("\n zx200a-%d: zx200a_diskio bad di=%02X", fdcnum, di & 0x07);
|
||||
sim_printf("\n zx200a: zx200a_diskio bad di=%02X", di & 0x07);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user