mirror of
https://github.com/simh/simh.git
synced 2026-04-15 16:11:13 +00:00
Intel-Systems: Update and cleanup components
This commit is contained in:
Bill Beech
committed by
Mark Pizzolato
Mark Pizzolato
parent
fac5bc96fb
commit
6af0958209
98
Intel-Systems/imds-210/imds-210_sys.c
Normal file
98
Intel-Systems/imds-210/imds-210_sys.c
Normal file
@@ -0,0 +1,98 @@
|
||||
/* mds210_sys.c: multibus system interface
|
||||
|
||||
Copyright (c) 2017, William A. Beech
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
||||
28 Oct 17 - Original file.
|
||||
|
||||
18 May 19 - Equipment Emulated:
|
||||
Model 210 chassis.
|
||||
Integrated processor board (IPB).
|
||||
Parallel I/O board (PIO).
|
||||
ROM-resident system monitor.
|
||||
Auxiliary ROM board with MCS-80/MCS-85 assembler
|
||||
and text editor.
|
||||
|
||||
*/
|
||||
|
||||
#include "system_defs.h"
|
||||
|
||||
extern DEVICE i8080_dev;
|
||||
extern REG i8080_reg[];
|
||||
extern DEVICE i8251_dev;
|
||||
extern DEVICE i8253_dev;
|
||||
extern DEVICE i8255_dev;
|
||||
extern DEVICE i8259_dev;
|
||||
extern DEVICE EPROM_dev;
|
||||
extern DEVICE RAM_dev;
|
||||
extern DEVICE ipc_cont_dev;
|
||||
extern DEVICE multibus_dev;
|
||||
//extern DEVICE isbc201_dev;
|
||||
//extern DEVICE isbc202_dev;
|
||||
//extern DEVICE isbc206_dev;
|
||||
//extern DEVICE zx200a_dev;
|
||||
extern DEVICE isbc464_dev;
|
||||
|
||||
/* SCP data structures
|
||||
|
||||
sim_name simulator name string
|
||||
sim_PC pointer to saved PC register descriptor
|
||||
sim_emax number of words needed for examine
|
||||
sim_devices array of pointers to simulated devices
|
||||
sim_stop_messages array of pointers to stop messages
|
||||
*/
|
||||
|
||||
char sim_name[] = "Intel MDS-210";
|
||||
|
||||
REG *sim_PC = &i8080_reg[0];
|
||||
|
||||
int32 sim_emax = 4;
|
||||
|
||||
DEVICE *sim_devices[] = {
|
||||
&i8080_dev,
|
||||
&EPROM_dev,
|
||||
&RAM_dev,
|
||||
&i8251_dev,
|
||||
&i8253_dev,
|
||||
&i8255_dev,
|
||||
&i8259_dev,
|
||||
&ipc_cont_dev,
|
||||
&multibus_dev,
|
||||
// &isbc201_dev,
|
||||
// &isbc202_dev,
|
||||
// &isbc206_dev,
|
||||
// &zx200a_dev,
|
||||
&isbc464_dev,
|
||||
NULL
|
||||
};
|
||||
|
||||
const char *sim_stop_messages[] = {
|
||||
"Unknown error",
|
||||
"Unknown I/O Instruction",
|
||||
"HALT instruction",
|
||||
"Breakpoint",
|
||||
"Invalid Opcode",
|
||||
"Invalid Memory",
|
||||
"XACK Error"
|
||||
};
|
||||
|
||||
156
Intel-Systems/imds-210/system_defs.h
Normal file
156
Intel-Systems/imds-210/system_defs.h
Normal file
@@ -0,0 +1,156 @@
|
||||
/* system_defs.h: Intel iSBC simulator definitions
|
||||
|
||||
Copyright (c) 2017, William A. Beech
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
||||
28 Oct 17 - Original file.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <ctype.h>
|
||||
#include "sim_defs.h" /* simulator defns */
|
||||
|
||||
#define IPC 0
|
||||
#define SET_XACK(VAL) (xack = VAL)
|
||||
|
||||
/* set the base for the DBB ports */
|
||||
#define DBB_BASE 0xC0
|
||||
|
||||
/* set the base I/O address for the 8255 */
|
||||
#define I8255_BASE_0 0xE4
|
||||
#define I8255_BASE_1 0xE8
|
||||
#define I8255_NUM 2
|
||||
|
||||
/* set the base I/O address for the 8253 */
|
||||
#define I8253_BASE 0xF0
|
||||
#define I8253_NUM 1
|
||||
|
||||
/* set the base I/O address for the 8251 */
|
||||
#define I8251_BASE_0 0xF4
|
||||
#define I8251_BASE_1 0xF6
|
||||
#define I8251_NUM 2
|
||||
|
||||
/* set the base I/O address for the 8259 */
|
||||
#define I8259_BASE_0 0xFA
|
||||
#define I8259_BASE_1 0xFC
|
||||
#define I8259_NUM 2
|
||||
|
||||
/* set the base I/O address for the IPC control port */
|
||||
#define ICONT_BASE 0xFF
|
||||
|
||||
/* set the base and size for the EPROM on the MDS 210 */
|
||||
#define ROM_BASE 0x0000
|
||||
#define ROM_SIZE 0x0FFF
|
||||
#define ROM_DISABLE 1
|
||||
#define EPROM_NUM 1
|
||||
|
||||
/* set the base and size for the RAM on the MDS 210 */
|
||||
#define RAM_BASE 0x0000
|
||||
#define RAM_SIZE 0x7FFF
|
||||
|
||||
//board definitions for the multibus
|
||||
/* set the base I/O address for the iSBC 201 */
|
||||
#define SBC201_BASE 0x78
|
||||
#define SBC201_INT INT_1
|
||||
#define SBC201_NUM 0
|
||||
|
||||
/* set the base I/O address for the iSBC 202 */
|
||||
#define SBC202_BASE 0x78
|
||||
#define SBC202_INT INT_1
|
||||
#define SBC202_NUM 1
|
||||
|
||||
/* set the base I/O address for the iSBC 206 */
|
||||
#define SBC206_BASE 0x68
|
||||
#define SBC206_INT INT_1
|
||||
#define SBC206_NUM 0
|
||||
|
||||
/* set the base I/O address for the iSBC 208 */
|
||||
#define SBC208_BASE 0x40
|
||||
#define SBC208_INT INT_1
|
||||
#define SBC208_NUM 0
|
||||
|
||||
/* set the base for the zx-200a disk controller */
|
||||
#define ZX200A_BASE 0x78
|
||||
#define ZX200A_INT INT_1
|
||||
#define ZX200A_NUM 0
|
||||
|
||||
/* set the base and size for the iSBC 464 ROM */
|
||||
#define SBC464_BASE 0xA800
|
||||
#define SBC464_SIZE 0x4800
|
||||
#define SBC464_NUM 1
|
||||
|
||||
/* set the base and size for the iSBC 064 RAM */
|
||||
#define SBC064_BASE 0x8000
|
||||
#define SBC064_SIZE 0x7FFF
|
||||
#define SBC064_NUM 1
|
||||
|
||||
/* set INTR for CPU */
|
||||
#define INTR INT_1
|
||||
|
||||
/* multibus interrupt definitions */
|
||||
|
||||
#define INT_0 0x01
|
||||
#define INT_1 0x02
|
||||
#define INT_2 0x04
|
||||
#define INT_3 0x08
|
||||
#define INT_4 0x10
|
||||
#define INT_5 0x20
|
||||
#define INT_6 0x40
|
||||
#define INT_7 0x80
|
||||
|
||||
/* CPU interrupts definitions */
|
||||
|
||||
#define INT_R 0x200
|
||||
#define I75 0x40
|
||||
#define I65 0x20
|
||||
#define I55 0x10
|
||||
|
||||
/* Memory */
|
||||
|
||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
||||
|
||||
/* debug definitions */
|
||||
|
||||
#define DEBUG_flow 0x0001
|
||||
#define DEBUG_read 0x0002
|
||||
#define DEBUG_write 0x0004
|
||||
#define DEBUG_level1 0x0008
|
||||
#define DEBUG_level2 0x0010
|
||||
#define DEBUG_reg 0x0020
|
||||
#define DEBUG_asm 0x0040
|
||||
#define DEBUG_xack 0x0080
|
||||
#define DEBUG_all 0xFFFF
|
||||
|
||||
/* Simulator stop codes */
|
||||
|
||||
#define STOP_RSRV 1 /* must be 1 */
|
||||
#define STOP_HALT 2 /* HALT */
|
||||
#define STOP_IBKPT 3 /* breakpoint */
|
||||
#define STOP_OPCODE 4 /* Invalid Opcode */
|
||||
#define STOP_IO 5 /* I/O error */
|
||||
#define STOP_MEM 6 /* Memory error */
|
||||
#define STOP_XACK 7 /* XACK error */
|
||||
|
||||
Reference in New Issue
Block a user