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Intel-Systems: Update and cleanup components

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This commit is contained in:
Bill Beech
2019-10-16 13:41:27 -07:00
committed by Mark Pizzolato
parent fac5bc96fb
commit 6af0958209
68 changed files with 10662 additions and 3758 deletions
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80
Intel-Systems/isys8024/isbc8024.c
View File

@@ -37,6 +37,7 @@
/* function prototypes */
t_stat SBC_config(void);
uint8 get_mbyte(uint16 addr);
uint16 get_mword(uint16 addr);
void put_mbyte(uint16 addr, uint8 val);
@@ -53,39 +54,74 @@ extern int32 PCX; /* External view of PC */
extern uint8 multibus_get_mbyte(uint16 addr);
extern void multibus_put_mbyte(uint16 addr, uint8 val);
extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
extern int32 i8251_devnum;
extern t_stat i8251_reset (DEVICE *dptr, uint16 base);
extern int32 i8253_devnum;
extern t_stat i8253_reset (DEVICE *dptr, uint16 base);
extern int32 i8255_devnum;
extern t_stat i8255_reset (DEVICE *dptr, uint16 base);
extern int32 i8259_devnum;
extern t_stat i8259_reset (DEVICE *dptr, uint16 base);
extern DEVICE *i8080_dev;
extern t_stat i8251_reset (DEVICE *dptr);
extern uint8 i8251s(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8251d(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8251_dev;
extern t_stat i8253_reset (DEVICE *dptr);
extern uint8 i8253t0(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8253t1(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8253t2(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8253c(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8253_dev;
extern t_stat i8255_reset (DEVICE *dptr);
extern uint8 i8255a(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8255b(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8255c(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8255s(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8255_dev;
extern t_stat i8259_reset (DEVICE *dptr);
extern uint8 i8259a(t_bool io, uint8 data, uint8 devnum);
extern uint8 i8259b(t_bool io, uint8 data, uint8 devnum);
extern DEVICE *i8259_dev;
extern uint8 EPROM_get_mbyte(uint16 addr);
extern UNIT EPROM_unit;
extern t_stat EPROM_reset (DEVICE *dptr, uint16 size);
extern t_stat EPROM_reset (DEVICE *dptr, uint16 base, uint16 size);
extern uint8 RAM_get_mbyte(uint16 addr);
extern void RAM_put_mbyte(uint16 addr, uint8 val);
extern UNIT RAM_unit;
extern t_stat RAM_reset (DEVICE *dptr, uint16 base, uint16 size);
extern t_stat i8251_cfg(uint8 base, uint8 devnum);
extern t_stat i8253_cfg(uint8 base, uint8 devnum);
extern t_stat i8255_cfg(uint8 base, uint8 devnum);
extern t_stat i8259_cfg(uint8 base, uint8 devnum);
extern t_stat RAM_cfg(uint16 base, uint16 size);
extern t_stat EPROM_cfg(uint16 base, uint16 size);
extern t_stat multibus_cfg();
// globals
int onetime = 0;
t_stat SBC_config(void)
{
sim_printf("Configuring iSBC-80/24 SBC\n Onboard Devices:\n");
i8251_cfg(I8251_BASE, 0);
i8253_cfg(I8253_BASE, 0);
i8255_cfg(I8255_BASE_0, 0);
i8255_cfg(I8255_BASE_1, 1);
i8259_cfg(I8259_BASE, 0);
EPROM_cfg(ROM_BASE, ROM_SIZE);
RAM_cfg(RAM_BASE, RAM_SIZE);
return SCPE_OK;
}
/* SBC reset routine */
t_stat SBC_reset (DEVICE *dptr)
{
sim_printf("Initializing iSBC-80/24 SBC\n Onboard Devices:\n");
i8080_reset (NULL);
i8251_devnum = 0;
i8251_reset (NULL, I8251_BASE);
i8253_devnum = 0;
i8253_reset (NULL, I8253_BASE);
i8255_devnum = 0;
i8255_reset (NULL, I8255_BASE_0);
i8255_reset (NULL, I8255_BASE_1);
i8259_devnum = 0;
i8259_reset (NULL, I8259_BASE);
EPROM_reset (NULL, ROM_SIZE);
RAM_reset (NULL, RAM_BASE, RAM_SIZE);
if (onetime == 0) {
SBC_config();
multibus_cfg();
onetime++;
}
i8080_reset(i8080_dev);
i8251_reset(i8251_dev);
i8253_reset(i8253_dev);
i8255_reset(i8255_dev);
i8255_reset(i8255_dev);
i8259_reset(i8259_dev);
return SCPE_OK;
}

27
Intel-Systems/isys8024/system_defs.h
View File

@@ -52,12 +52,13 @@
/* set the base and size for the EPROM on the iSBC 80/10 */
#define ROM_BASE 0x0000
#define ROM_SIZE 0x1000
#define ROM_SIZE 0x0FFF
#define ROM_DISABLE 1
#define EPROM_NUM 1
/* set the base and size for the RAM on the iSBC 80/10 */
#define RAM_BASE 0xF000
#define RAM_SIZE 0x1000
#define RAM_SIZE 0x0FFF
#define RAM_DISABLE 0
/* set INTR for CPU on the iSBC 80/10 */
@@ -74,21 +75,39 @@
#define SBC202_INT INT_1
#define SBC202_NUM 1
/* set the base I/O address for the iSBC 206 */
#define SBC206_BASE 0x68
#define SBC206_INT INT_2
#define SBC206_NUM 0
/* set the base for the zx-200a disk controller */
#define ZX200A_BASE 0x78
#define ZX200A_INT INT_1
#define ZX200A_NUM 0
/* set the base I/O address for the iSBX 218 */
#define SBC208_BASE 0x40
#define SBC208_INT INT_1
#define SBC208_NUM 0
#define I8272_BASE 0xF0
#define I8272_NUM 1
#define I8272_INT INT_1
/* set the base I/O address for the iSBC 208 */
#define SBC208_BASE 0x40
#define SBC208_BASE 0x40
#define SBC208_INT INT_1
#define SBC208_NUM 0
/* set the base and size for the iSBC 064 */
#define SBC064_BASE 0x0000
#define SBC064_SIZE 0x10000
#define SBC064_SIZE 0xFFFF
#define SBC064_NUM 1
/* set the base and size for the iSBC 464 ROM */
#define SBC464_BASE 0xA800
#define SBC464_SIZE 0x4800
#define SBC464_NUM 0
/* multibus interrupt definitions */
#define INT_0 0x01