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PDP8, PDP18b: Fixed RF, DF, DT device bug if read overwrites WC memory location

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This commit is contained in:
Bob Supnik
2021-06-08 01:43:32 -07:00
committed by Mark Pizzolato
parent e039527a34
commit 6edc4994eb
5 changed files with 42 additions and 32 deletions
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20
PDP18B/pdp18b_dt.c
View File

@@ -27,6 +27,7 @@
(PDP-9) TC02/TU55 DECtape
(PDP-15) TC15/TU56 DECtape
03-May-21 RMS Fixed bug if read overwrites WC memory location
15-Mar-17 RMS Fixed dt_seterr to clear successor states
09-Mar-17 RMS Fixed dt_seterr to handle nx unit select (COVERITY)
10-Mar-16 RMS Added 3-cycle databreak set/show entries
@@ -959,10 +960,10 @@ switch (fnc) { /* at speed, check fnc *
sim_activate (uptr, DTU_LPERB (uptr) * dt_ltime);/* sched next block */
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* inc WC */
ma = M[DT_CA] & AMASK; /* get mem addr */
if (MEM_ADDR_OK (ma)) /* store block # */
M[ma] = blk;
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; /* set DTF */
if (MEM_ADDR_OK (ma)) /* store block # */
M[ma] = blk;
if (DEBUG_PRI (dt_dev, LOG_MS))
fprintf (sim_deb, ">>DT%d: found block %d\n", unum, blk);
break;
@@ -998,6 +999,8 @@ switch (fnc) { /* at speed, check fnc *
case 0: /* normal read */
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & DMASK;
if (M[DT_WC] == 0) /* wc ovf? */
dt_substate = DTO_WCO;
ma = M[DT_CA] & AMASK; /* mem addr */
ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
dtdb = fbuf[ba]; /* get tape word */
@@ -1005,16 +1008,15 @@ switch (fnc) { /* at speed, check fnc *
dtdb = dt_comobv (dtdb);
if (MEM_ADDR_OK (ma)) /* mem addr legal? */
M[ma] = dtdb;
if (M[DT_WC] == 0) /* wc ovf? */
dt_substate = DTO_WCO;
/* fall through */
case DTO_WCO: /* wc ovf, not sob */
if (wrd != (dir? 0: DTU_BSIZE (uptr) - 1)) /* not last? */
sim_activate (uptr, DT_WSIZE * dt_ltime);
else {
dt_substate = dt_substate | DTO_SOB;
sim_activate (uptr, ((2 * DT_HTLIN) + DT_WSIZE) * dt_ltime);
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
if (((dtsa & DTA_MODE) == 0) || (dt_substate == DTO_WCO))
dtsb = dtsb | DTB_DTF; /* set DTF */
dt_substate = dt_substate | DTO_SOB;
}
break;
@@ -1100,6 +1102,8 @@ switch (fnc) { /* at speed, check fnc *
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & DMASK;
if (M[DT_WC] == 0)
dt_substate = DTO_WCO;
ma = M[DT_CA] & AMASK; /* mem addr */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
@@ -1113,9 +1117,7 @@ switch (fnc) { /* at speed, check fnc *
sim_activate (uptr, DT_WSIZE * dt_ltime);
if (MEM_ADDR_OK (ma)) /* mem addr legal? */
M[ma] = dtdb;
if (M[DT_WC] == 0)
dt_substate = DTO_WCO;
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
if (((dtsa & DTA_MODE) == 0) || (dt_substate == DTO_WCO))
dtsb = dtsb | DTB_DTF; /* set DTF */
break;

12
PDP18B/pdp18b_rf.c
View File

@@ -1,6 +1,6 @@
/* pdp18b_rf.c: fixed head disk simulator
Copyright (c) 1993-2016, Robert M Supnik
Copyright (c) 1993-2021, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -26,6 +26,7 @@
rf (PDP-9) RF09/RF09
(PDP-15) RF15/RS09
21-Apr-21 RMS Fixed bug if read overwrites WC memory location
10-Mar-16 RMS Added 3-cycle databreak set/show entries
07-Mar-16 RMS Revised for dynamically allocated memory
13-Sep-15 RMS Added APIVEC register
@@ -271,6 +272,7 @@ return dat;
t_stat rf_svc (UNIT *uptr)
{
int32 f, pa, d, t;
int32 wc = 0;
int32 *fbuf = (int32 *) uptr->filebuf;
if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? abort */
@@ -284,8 +286,8 @@ do {
rf_updsta (RFS_NED); /* nx disk error */
break;
}
M[RF_WC] = (M[RF_WC] + 1) & DMASK; /* incr word count */
pa = M[RF_CA] = (M[RF_CA] + 1) & AMASK; /* incr mem addr */
wc = M[RF_WC] = (M[RF_WC] + 1) & DMASK; /* incr word count */
pa = M[RF_CA] = (M[RF_CA] + 1) & AMASK; /* incr mem addr */
if ((f == FN_READ) && MEM_ADDR_OK (pa)) /* read? */
M[pa] = fbuf[rf_da];
if ((f == FN_WCHK) && (M[pa] != fbuf[rf_da])) { /* write check? */
@@ -306,9 +308,9 @@ do {
}
}
rf_da = rf_da + 1; /* incr disk addr */
} while ((M[RF_WC] != 0) && (rf_burst != 0)); /* brk if wc, no brst */
} while ((wc != 0) && (rf_burst != 0)); /* brk if wc, no brst */
if ((M[RF_WC] != 0) && ((rf_sta & RFS_ERR) == 0)) /* more to do? */
if ((wc != 0) && ((rf_sta & RFS_ERR) == 0)) /* more to do? */
sim_activate (&rf_unit, rf_time); /* sched next */
else rf_updsta (RFS_DON);
return SCPE_OK;