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Code Releases Activity

Notes For V2.8

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1. New Features

1.1 Directory and documentation

- Only common files (SCP and libraries) are in the top level
  directory.  Individual simulator files are in their individual
  directories.
- simh_doc.txt has been split up.  simh_doc.txt now documents
  only SCP.  The individual simulators are documented in separate
  text files in their own directories.
- mingw_build.bat is a batch file for the MINGW/gcc environment
  that will build all the simulators, assuming the root directory
  structure is at c:\sim.
- Makefile is a UNIX make file for the gcc environment that will
  build all the simulators, assuming the root directory is at
  c:\sim.

1.2 SCP

- DO <file name> executes the SCP commands in the specified file.
- Replicated registers in unit structures can now be declared as
  arrays for examine, modify, save, and restore.  Most replicated
  unit registers (for example, mag tape position registers) have
  been changed to arrays.
- The ADD/REMOVE commands have been replaced by SET unit ONLINE
  and SET unit OFFLINE, respectively.
- Register names that are unique within an entire simulator do
  not have to be prefaced with the device name.
- The ATTACH command can attach files read only, either under
  user option (-r), or because the attached file is ready only.
- The SET/SHOW capabilities have been extended.  New forms include:

	SET <dev> param{=value}{ param ...}
	SET <unit> param{=value}{ param ...}
	SHOW <dev> {param param ...}
	SHOW <unit> {param param ...}

- Multiple breakpoints have been implemented.  Breakpoints are
  set/cleared/displayed by:

	BREAK addr_list{[count]}
	NOBREAK addr_list
	SHOW BREAK addr_list

1.3 PDP-11 simulator

- Unibus map implemented, with 22b RP controller (URH70) or 18b
  RP controller (URH11) (in debug).
- All DMA peripherals rewritten to use map.
- Many peripherals modified for source sharing with VAX.
- RQDX3 implemented.
- Bugs fixed in RK11 and RL11 write check.

1.4 PDP-10 simulator

- ITS 1-proceed implemented.
- Bugs fixed in ITS PC sampling and LPMR

1.5 18b PDP simulator

- Interrupts split out to multiple levels to allow easier
  expansion.

1.5 IBM System 3 Simulator

- Written by Charles (Dutch) Owen.

1.6 VAX Simulator (in debug)

- Simulates MicroVAX 3800 (KA655) with 16MB-64MB memory, RQDX3,
  RLV12, TSV11, DZV11, LPV11, PCV11.
- CDROM capability has been added to the RQDX3, to allow testing
  with VMS hobbyist images.

1.7 SDS 940 Simulator (not tested)

- Simulates SDS 940, 16K-64K memory, fixed and moving head
  disk, magtape, line printer, console.

1.8 Altair Z80

- Revised from Charles (Dutch) Owen's original by Peter Schorn.
- MITS 8080 with full Z80 simulation.
- 4K and 8K BASIC packages, Prolog package.

1.9 Interdata

The I4 simulator has been withdrawn for major rework.  Look for
a complete 16b/32b Interdata simulator sometime next year.

2. Release Notes

2.1 SCP

SCP now allows replicated registers in unit structures to be
modelled as arrays.  All replicated register declarations have
been replaced by register array declarations.  As a result,
save files from prior revisions will generate errors after
restoring main memory.

2.2 PDP-11

The Unibus map code is in debug.  The map was implemented primarily
to allow source sharing with the VAX, which requires a DMA map.
DMA devices work correctly with the Unibus map disabled.

The RQDX3 simulator has run a complete RSTS/E SYSGEN, with multiple
drives, and booted the completed system from scratch.

2.3 VAX

The VAX simulator will run the boot code up to the >>> prompt.  It
can successfully process a SHOW DEVICE command.  It runs the HCORE
instruction diagnostic.  It can boot the hobbyist CD through SYSBOOT
and through the date/time dialog and restore the hobbyist CD, using
standalone backup.  On the boot of the restored disk, it gets to the
date/time dialog, and then crashes.

2.4 SDS 940

The SDS 940 is untested, awaiting real code.

2.5 GCC Optimization

At -O2 and above, GCC does not correctly compile the simulators which
use setjmp-longjmp (PDP-11, PDP-10, VAX).  A working hypothesis is
that optimized state maintained in registers is being used in the
setjmp processing routine.  On the PDP-11 and PDP-10, all of this
state has been either made global, or volatile, to encourage GCC to
keep the state up to date in memory.  The VAX is still vulnerable.

3. Work list

3.1 SCP

- Better ENABLE/DISABLE.

3.2 PDP-11 RQDX3

Software mapped mode, RCT read simulation, VMS debug.
This commit is contained in:
Bob Supnik
2001-12-26 09:38:00 -08:00
committed by Mark Pizzolato
parent 654937fc88
commit 701f0fe028
145 changed files with 23190 additions and 9807 deletions
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/* h316_defs.h: Honeywell 316/516 simulator definitions
Copyright (c) 1993-2001, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
*/
#include "sim_defs.h" /* simulator defns */
/* Simulator stop codes */
#define STOP_RSRV 1 /* must be 1 */
#define STOP_IODV 2 /* must be 2 */
#define STOP_HALT 3 /* HALT */
#define STOP_IBKPT 4 /* breakpoint */
#define STOP_IND 5 /* indirect loop */
/* Memory */
#define MAXMEMSIZE 32768 /* max memory size */
#define MEMSIZE (cpu_unit.capac) /* actual memory size */
#define X_AMASK (MAXMEMSIZE - 1) /* ext address mask */
#define NX_AMASK ((MAXMEMSIZE / 2) - 1) /* nx address mask */
#define MEM_ADDR_OK(x) (((t_addr) (x)) < MEMSIZE)
/* Architectural constants */
#define SIGN 0100000 /* sign */
#define DMASK 0177777 /* data mask */
#define MMASK (DMASK & ~SIGN) /* magnitude mask */
#define XR M[0]
#define M_CLK 061 /* clock location */
#define M_RSTINT 062 /* restrict int */
#define M_INT 063 /* int location */
/* CPU options */
#define UNIT_V_EXT (UNIT_V_UF + 1) /* extended mem */
#define UNIT_EXT (1 << UNIT_V_EXT)
#define UNIT_V_HSA (UNIT_V_UF + 2) /* high speed arith */
#define UNIT_HSA (1 << UNIT_V_HSA)
/* Instruction format */
#define I_M_OP 077 /* opcode */
#define I_V_OP 10
#define I_GETOP(x) (((x) >> I_V_OP) & I_M_OP)
#define I_M_FNC 017 /* function */
#define I_V_FNC 6
#define I_GETFNC(x) (((x) >> I_V_FNC) & I_M_FNC)
#define IA 0100000 /* indirect address */
#define IDX 0040000 /* indexed */
#define SC 0001000 /* sector */
#define DISP 0000777 /* page displacement */
#define PAGENO 0077000 /* page number */
#define INCLRA (010 << I_V_FNC) /* INA clear A */
#define DEVMASK 0000077 /* device mask */
#define SHFMASK 0000077 /* shift mask */
/* I/O opcodes */
#define ioOCP 0 /* output control */
#define ioSKS 1 /* skip if set */
#define ioINA 2 /* input to A */
#define ioOTA 3 /* output from A */
/* I/O devices */
#define PTR 001 /* paper tape reader */
#define PTP 002 /* paper tape punch */
#define LPT 003 /* line printer */
#define TTY 004 /* console */
#define CDR 005 /* card reader */
#define MT 010 /* mag tape data */
#define KEYS 020 /* keys (CPU) */
#define FHD 022 /* fixed head disk */
#define DMA 024 /* DMA control */
#define DP 025 /* moving head disk */
#define OPT 034 /* SKS/OCP option */
/* Interrupt flags, definitions correspond to SMK bits */
#define INT_V_CLK 0 /* clock */
#define INT_V_MPE 1 /* parity error */
#define INT_V_LPT 2 /* line printer */
#define INT_V_CDR 4 /* card reader */
#define INT_V_TTY 5 /* teletype */
#define INT_V_PTP 6 /* paper tape punch */
#define INT_V_PTR 7 /* paper tape reader */
#define INT_V_FHD 8 /* fixed head disk */
#define INT_V_DP 12 /* moving head disk */
#define INT_V_MT 15 /* mag tape */
#define INT_V_NODEF 16 /* int not deferred */
#define INT_V_ON 17 /* int on */
/* I/O macros */
#define IOT_V_REASON 17
#define IOT_V_SKIP 16
#define IOT_SKIP (1u << IOT_V_SKIP)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */
#define IOBADFNC(x) (((stop_inst) << IOT_V_REASON) | (x))
#define IOSKIP(x) (IOT_SKIP | (x))
#define INT_CLK (1u << INT_V_CLK)
#define INT_MPE (1u << INT_V_MPE)
#define INT_LPT (1u << INT_V_LPT)
#define INT_CDR (1u << INT_V_CDR)
#define INT_TTY (1u << INT_V_TTY)
#define INT_PTP (1u << INT_V_PTP)
#define INT_PTR (1u << INT_V_PTR)
#define INT_FHD (1u << INT_V_FHD)
#define INT_DP (1u << INT_V_DP)
#define INT_MT (1u << INT_V_MT)
#define INT_NODEF (1u << INT_V_NODEF)
#define INT_ON (1u << INT_V_ON)
#define INT_PENDING (INT_ON | INT_NODEF)
#define SET_READY(x) dev_ready = dev_ready | (x)
#define CLR_READY(x) dev_ready = dev_ready & ~(x)
#define TST_READY(x) ((dev_ready & (x)) != 0)
#define CLR_ENABLE(x) dev_enable = dev_enable & ~(x)
#define TST_INTREQ(x) ((dev_ready & dev_enable & (x)) != 0)

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To: Users
From: Bob Supnik
Subj: H316 Simulator Usage
Date: 1-Dec-2001
COPYRIGHT NOTICE
The following copyright notice applies to both the SIMH source and binary:
Original code published in 1993-2001, written by Robert M Supnik
Copyright (c) 1993-2001, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
This memorandum documents Honeywell 316/516 simulator.
1. Simulator Files
The H316 requires the following files:
sim/ sim_defs.h
scp.c
scp_tty.c
sim_rev.c
sim/h316/ h316_defs.h
h316_cpu.c
h316_lp.c
h316_stddev.c
h316_cpu.c
2. H316/H516 Features
The Honeywell 316/516 simulator is configured as follows:
device simulates
name(s)
CPU H316/H516 CPU with 16/32KW memory
PTR 316/516-50 paper tape reader
PTP 316/516-52 paper tape punch
TTY 316/516-33 console terminal
CLK 316/516-12 real time clock
LPT 316/516 line printer
The H316/H516 simulator implements several unique stop conditions:
- decode of an undefined instruction, and STOP_INST is et
- reference to an undefined I/O device, and STOP_DEV is set
- more than INDMAX indirect references are detected during
memory reference address decoding
The H316/H516 loader is not implemented.
2.1 CPU
CPU options include choice of instruction set and memory size.
SET CPU HSA high speed arithmetic instructions
SET CPU NOHSA no high speed arithmetic instructions
SET CPU 4K set memory size = 4K
SET CPU 8K set memory size = 8K
SET CPU 12K set memory size = 12K
SET CPU 16K set memory size = 16K
SET CPU 24K set memory size = 24K
SET CPU 32K set memory size = 32K
If memory size is being reduced, and the memory being truncated contains
non-zero data, the simulator asks for confirmation. Data in the truncated
portion of memory is lost. Initial memory size is 32K.
CPU registers include the visible state of the processor as well as the
control registers for the interrupt system.
name size comments
P 15 program counter
A 16 A register
B 16 B register
X 16 index register
SC 16 shift count
C 1 carry flag
EXT 1 extend flag
PME 1 previous mode extend flag
EXT_OFF 1 extend off pending flag
DP 1 double precision flag
SS1..4 1 sense switches 1..4
ION 1 interrupts enabled
INODEF 1 interrupts not deferred
INTREQ 16 interrupt requests
DEVRDY 16 device ready flags (read only)
DEVENB 16 device interrupt enable flags (read only)
STOP_INST 1 stop on undefined instruction
STOP_DEV 1 stop on undefined device
INDMAX 1 indirect address limit
OLDP 15 PC prior to last JMP, JSB, or interrupt
WRU 8 interrupt character
2.2 Programmed I/O Devices
2.2.1 316/516-50 Paper Tape Reader (PTR)
The paper tape reader (PTR) reads data from a disk file. The POS
register specifies the number of the next data item to be read.
Thus, by changing POS, the user can backspace or advance the reader.
The paper tape reader supports the BOOT command. BOOT PTR copies the
absolute binary loader into memory and starts it running.
The paper tape reader implements these registers:
name size comments
BUF 8 last data item processed
INTREQ 1 device interrupt request
READY 1 device ready
ENABLE 1 device interrupts enabled
POS 31 position in the input or output file
TIME 24 time from I/O initiation to interrupt
STOP_IOE 1 stop on I/O error
Error handling is as follows:
error STOP_IOE processed as
not attached 1 report error and stop
0 out of tape
end of file 1 report error and stop
0 out of tape or paper
OS I/O error x report error and stop
2.2.2 316/516-52 Paper Tape Punch (PTP)
The paper tape punch (PTP) writes data to a disk file. The POS
register specifies the number of the next data item to be written.
Thus, by changing POS, the user can backspace or advance the punch.
The paper tape punch implements these registers:
name size comments
BUF 8 last data item processed
INTREQ 1 device interrupt request
READY 1 device ready
ENABLE 1 device interrupts enabled
POWER 1 device powered up
POS 31 position in the input or output file
TIME 24 time from I/O initiation to interrupt
PWRTIME 24 time from I/O request to power up
STOP_IOE 1 stop on I/O error
Error handling is as follows:
error STOP_IOE processed as
not attached 1 report error and stop
0 out of tape
OS I/O error x report error and stop
2.2.3 316/516-33 Console Teletype (TTY)
The terminal reads from the console keyboard and writes to the
simulator console window. The terminal has one option, UC; when
set, the terminal automatically converts lower case input to upper
case. This is on by default.
The terminal these registers:
name size comments
BUF 8 last data item processed
MODE 1 read/write mode
INTREQ 1 device interrupt request
READY 1 device ready
ENABLE 1 device interrupts enabled
KPOS 31 number of characters input
KTIME 24 keyboard polling interval
TPOS 31 number of characters output
TTIME 24 time from I/O initiation to interrupt
2.2.4 316/516-12 Real Time Clock (CLK)
The real time clock (CLK) implements these registers:
name size comments
INTREQ 1 device interrupt request
READY 1 device ready
ENABLE 1 device interrupts enabled
TIME 24 clock interval
2.2.5 316/5116 Line Printer (LPT)
The line printer (LPT) writes data to a disk file. The POS register
specifies the number of the next data item to be written. Thus,
by changing POS, the user can backspace or advance the printer.
The line printer implements these registers:
name size comments
WDPOS 6 word position in current scan
DRPOS 6 drum position
CRPOS 1 carriage position
XFER 1 transfer ready flag
PRDN 1 print done flag
INTREQ 1 device interrupt request
ENABLE 1 device interrupt enable
SVCST 2 service state
SVCCH 2 service channel
BUF 8 buffer
POS 31 number of characters output
XTIME 24 delay between transfers
ETIME 24 delay at end of scan
PTIME 24 delay for shuttle/line advance
STOP_IOE 1 stop on I/O error
Error handling is as follows:
error STOP_IOE processed as
not attached 1 report error and stop
0 out of paper
OS I/O error x report error and stop
2.3 Symbolic Display and Input
The H316/H516 simulator implements symbolic display and input. Display is
controlled by command line switches:
-a display as ASCII character
-c display as two character string
-m display instruction mnemonics
Input parsing is controlled by the first character typed in or by command
line switches:
' or -a ASCII character
" or -c two character sixbit string
alphabetic instruction mnemonic
numeric octal number
Instruction input uses standard H316/H516 assembler syntax. There are six
instruction classes: memory reference, I/O, control, shift, skip, and
operate.
Memory reference instructions have the format
memref{*} {C/Z} address{,1}
where * signifies indirect, C a current sector reference, Z a sector zero
reference, and 1 indexed. The address is an octal number in the range 0 -
077777; if C or Z is specified, the address is a page offset in the range
0 - 0777. Normally, C is not needed; the simulator figures out from the
address what mode to use. However, when referencing memory outside the CPU
(eg, disks), there is no valid PC, and C must be used to specify current
sector addressing.
I/O instructions have the format
io pulse+device
The pulse+device is an octal number in the range 0 - 01777.
Control and operate instructions consist of a single opcode
opcode
Shift instructions have the format
shift n
where n is an octal number in the range 0-77.
Skip instructions have the format
sub-op sub-op sub-op...
The simulator checks that the combination of sub-opcodes is legal.

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/* h316_lp.c: Honeywell 316/516 line printer
Copyright (c) 1993-2001, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
lpt line printer
*/
#include "h316_defs.h"
#define LPT_WIDTH 120 /* width */
#define LPT_SCAN (LPT_WIDTH / 2) /* words/scan */
#define LPT_DRUM 64 /* drum rows */
#define LPT_SVCSH 01 /* shuttle */
#define LPT_SVCPA 02 /* paper advance */
extern int32 dev_ready, dev_enable;
extern int32 stop_inst;
int32 lpt_wdpos = 0; /* word position */
int32 lpt_drpos = 0; /* drum position */
int32 lpt_crpos = 0; /* carriage position */
int32 lpt_svcst = 0; /* service state */
int32 lpt_svcch = 0; /* service channel */
int32 lpt_xfer = 0; /* transfer flag */
int32 lpt_prdn = 1; /* printing done */
char lpt_buf[LPT_WIDTH + 1] = { 0 }; /* line buffer */
int32 lpt_xtime = 5; /* transfer time */
int32 lpt_etime = 50; /* end of scan time */
int32 lpt_ptime = 5000; /* paper adv time */
int32 lpt_stopioe = 0; /* stop on error */
t_stat lpt_svc (UNIT *uptr);
t_stat lpt_reset (DEVICE *dptr);
/* The Series 16 line printer is an unbuffered Analex shuttle printer.
Because it was unbuffered, the CPU had to scan out an entire line's
worth of characters (60 words) for every character on the print drum
(64 characters). Because it was a shuttle printer, the entire
process must be repeated first for the odd columns and then for the
even columns. After scanning the odd columns, the printer carriage
shuttled right by one column; after scanning the even columns, the
carriage shuttled left. This halved the number of hammers required,
reducing cost but increasing mechanical complexity.
The real printer is very timing dependent. If the CPU misses a
scan, then the wrong characters are printed. If the printer protocol
is violated, then results are unpredictable. The simulated printer
is much more forgiving. Rather than simulating the fixed drum and
hammer timing of the real printer, the simulator is driven by the
program's OTA instructions. If the program misses a time slot, the
simulator will still print the "correct" result. A timing based
simulation would be very hard to do in the absense of accurate
instruction timing.
Printer state is maintained in a set of position and state variables:
lpt_wdpos word count within a line scan (0-59)
lpt_drpos drum position (0-63)
lpt_crpos carriage position (0-1)
lpt_svcst service state (shuttle, paper advance)
lpt_svcch channel for paper advance (0 = no adv)
lpt_xfer transfer ready flag
lpt_prdn printing done flag
LPT data structures
lpt_dev LPT device descriptor
lpt_unit LPT unit descriptor
lpt_mod LPT modifiers
lpt_reg LPT register list
*/
UNIT lpt_unit = { UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE, 0) };
REG lpt_reg[] = {
{ DRDATA (WDPOS, lpt_wdpos, 6) },
{ DRDATA (DRPOS, lpt_drpos, 6) },
{ FLDATA (CRPOS, lpt_crpos, 0) },
{ FLDATA (XFER, lpt_xfer, 0) },
{ FLDATA (PRDN, lpt_prdn, 0) },
{ FLDATA (INTREQ, dev_ready, INT_V_LPT) },
{ FLDATA (ENABLE, dev_enable, INT_V_LPT) },
{ ORDATA (SVCST, lpt_svcst, 2) },
{ ORDATA (SVCCH, lpt_svcch, 2) },
{ BRDATA (BUF, lpt_buf, 8, 8, 120) },
{ DRDATA (POS, lpt_unit.pos, 31), PV_LEFT },
{ DRDATA (XTIME, lpt_xtime, 24), PV_LEFT },
{ DRDATA (ETIME, lpt_etime, 24), PV_LEFT },
{ DRDATA (PTIME, lpt_ptime, 24), PV_LEFT },
{ FLDATA (STOP_IOE, lpt_stopioe, 0) },
{ NULL } };
DEVICE lpt_dev = {
"LPT", &lpt_unit, lpt_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &lpt_reset,
NULL, NULL, NULL };
/* IO routine */
int32 lptio (int32 inst, int32 fnc, int32 dat)
{
int32 chr;
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
switch (fnc) { /* case on fnc */
case 000: case 002: case 004: /* paper adv */
lpt_svcst = lpt_svcst | LPT_SVCPA; /* set state */
lpt_svcch = fnc >> 1; /* save channel */
sim_activate (&lpt_unit, lpt_ptime);
CLR_READY (INT_LPT); /* clear int */
break;
case 007: /* init scan */
lpt_prdn = 0; /* clear pr done */
lpt_wdpos = 0; /* init scan pos */
if (!sim_is_active (&lpt_unit)) lpt_xfer = 1;
CLR_READY (INT_LPT); /* clear int */
break;
default:
return IOBADFNC (dat); }
break;
case ioSKS: /* SKS */
switch (fnc) { /* case on fnc */
case 000: /* if xfer rdy */
if (lpt_xfer) return IOSKIP (dat);
break;
case 002: /* if !alarm */
if (lpt_unit.flags & UNIT_ATT) return IOSKIP (dat);
break;
case 003: /* if odd col */
if (lpt_crpos) return IOSKIP (dat);
break;
case 004: /* if !interrupt */
if (!TST_INTREQ (INT_LPT)) return IOSKIP (dat);
break;
case 011: /* if line printed */
if (lpt_prdn) return IOSKIP (dat);
break;
case 012: /* if !shuttling */
if (!(lpt_svcst & LPT_SVCSH)) return IOSKIP (dat);
break;
case 013:
if (lpt_prdn && !(lpt_svcst & LPT_SVCSH)) return IOSKIP (dat);
break;
case 014: /* if !advancing */
if (!(lpt_svcst & LPT_SVCPA)) return IOSKIP (dat);
break;
case 015:
if (lpt_prdn && !(lpt_svcst & LPT_SVCPA)) return IOSKIP (dat);
break;
case 016:
if (!(lpt_svcst & (LPT_SVCSH | LPT_SVCPA))) return IOSKIP (dat);
break;
case 017:
if (lpt_prdn && !(lpt_svcst & (LPT_SVCSH | LPT_SVCPA)))
return IOSKIP (dat);
break;
default:
return IOBADFNC (dat); }
break;
case ioOTA: /* OTA */
if (fnc) return IOBADFNC (dat); /* only fnc 0 */
if (lpt_xfer) { /* xfer ready? */
lpt_xfer = 0; /* clear xfer */
chr = (dat >> (lpt_crpos? 0: 8)) & 077; /* get 6b char */
if (chr == lpt_drpos) { /* match drum pos? */
if (chr < 040) chr = chr | 0100;
lpt_buf[2 * lpt_wdpos + lpt_crpos] = chr; }
lpt_wdpos++; /* adv scan pos */
if (lpt_wdpos >= LPT_SCAN) { /* end of scan? */
lpt_wdpos = 0; /* reset scan pos */
lpt_drpos++; /* adv drum pos */
if (lpt_drpos >= LPT_DRUM) { /* end of drum? */
lpt_drpos = 0; /* reset drum pos */
lpt_crpos = lpt_crpos ^ 1; /* shuttle */
lpt_svcst = lpt_svcst | LPT_SVCSH;
sim_activate (&lpt_unit, lpt_ptime);
} /* end if shuttle */
else sim_activate (&lpt_unit, lpt_etime);
} /* end if endscan */
else sim_activate (&lpt_unit, lpt_xtime);
return IOSKIP (dat); } /* skip return */
break; } /* end case op */
return dat;
}
/* Unit service */
t_stat lpt_svc (UNIT *uptr)
{
int32 i;
static const char *lpt_cc[] = {
"\r",
"\n",
"\n\f",
"\n" };
if ((lpt_unit.flags & UNIT_ATT) == 0) /* attached? */
return IORETURN (lpt_stopioe, SCPE_UNATT);
lpt_xfer = 1;
if (lpt_svcst & LPT_SVCSH) { /* shuttling */
SET_READY (INT_LPT); /* interrupt */
if (lpt_crpos == 0) lpt_prdn = 1; }
if (lpt_svcst & LPT_SVCPA) { /* paper advance */
SET_READY (INT_LPT); /* interrupt */
for (i = LPT_WIDTH - 1; i >= 0; i++) {
if (lpt_buf[i] != ' ') break; }
lpt_buf[i + 1] = 0;
fputs (lpt_buf, uptr -> fileref); /* output buf */
fputs (lpt_cc[lpt_svcch & 03], uptr -> fileref); /* output eol */
uptr -> pos = ftell (uptr -> fileref); /* update pos */
for (i = 0; i < LPT_WIDTH; i++) lpt_buf[i] = ' '; /* clear buf */
}
lpt_svcst = 0;
return SCPE_OK;
}
/* Reset routine */
t_stat lpt_reset (DEVICE *dptr)
{
int32 i;
lpt_wdpos = lpt_drpos = lpt_crpos = 0; /* clear positions */
lpt_svcst = lpt_svcch = 0; /* idle state */
lpt_xfer = 0; /* not rdy to xfer */
lpt_prdn = 1; /* printing done */
for (i = 0; i < LPT_WIDTH; i++) lpt_buf[i] = ' '; /* clear buffer */
lpt_buf[LPT_WIDTH] = 0;
CLR_READY (INT_LPT); /* clear int, enb */
CLR_ENABLE (INT_LPT);
sim_cancel (&lpt_unit); /* deactivate unit */
return SCPE_OK;
}

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/* h316_stddev.c: Honeywell 316/516 standard devices
Copyright (c) 1993-2001, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
ptr 316/516-50 paper tape reader
ptp 316/516-52 paper tape punch
tty 316/516-33 teleprinter
clk/options 316/516-12 real time clocks/internal options
03-Nov-01 RMS Implemented upper case for console output
29-Nov-01 RMS Added read only unit support
07-Sep-01 RMS Moved function prototypes
*/
#include "h316_defs.h"
#include <ctype.h>
#define UNIT_V_UC (UNIT_V_UF + 1) /* UC only */
#define UNIT_UC (1 << UNIT_V_UC)
extern uint16 M[];
extern int32 PC;
extern int32 stop_inst;
extern int32 C, dp, ext, extoff_pending, sc;
extern int32 dev_ready, dev_enable;
extern UNIT cpu_unit;
int32 ptr_stopioe = 0, ptp_stopioe = 0; /* stop on error */
int32 ptp_power = 0, ptp_ptime; /* punch power, time */
int32 tty_mode = 0, tty_buf = 0; /* tty mode, buf */
int32 clk_tps = 60; /* ticks per second */
t_stat ptr_svc (UNIT *uptr);
t_stat ptr_reset (DEVICE *dptr);
t_stat ptr_boot (int32 unitno);
t_stat ptp_svc (UNIT *uptr);
t_stat ptp_reset (DEVICE *dptr);
t_stat tti_svc (UNIT *uptr);
t_stat tto_svc (UNIT *uptr);
t_stat tty_reset (DEVICE *dptr);
t_stat clk_svc (UNIT *uptr);
t_stat clk_reset (DEVICE *dptr);
/* PTR data structures
ptr_dev PTR device descriptor
ptr_unit PTR unit descriptor
ptr_mod PTR modifiers
ptr_reg PTR register list
*/
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT };
REG ptr_reg[] = {
{ ORDATA (BUF, ptr_unit.buf, 8) },
{ FLDATA (READY, dev_ready, INT_V_PTR) },
{ FLDATA (ENABLE, dev_enable, INT_V_PTR) },
{ DRDATA (POS, ptr_unit.pos, 31), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ NULL } };
DEVICE ptr_dev = {
"PTR", &ptr_unit, ptr_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ptr_reset,
&ptr_boot, NULL, NULL };
/* PTP data structures
ptp_dev PTP device descriptor
ptp_unit PTP unit descriptor
ptp_mod PTP modifiers
ptp_reg PTP register list
*/
UNIT ptp_unit = {
UDATA (&ptp_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
REG ptp_reg[] = {
{ ORDATA (BUF, ptp_unit.buf, 8) },
{ FLDATA (READY, dev_ready, INT_V_PTP) },
{ FLDATA (ENABLE, dev_enable, INT_V_PTP) },
{ FLDATA (POWER, ptp_power, 0) },
{ DRDATA (POS, ptp_unit.pos, 31), PV_LEFT },
{ DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT },
{ DRDATA (PWRTIME, ptp_ptime, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptp_stopioe, 0) },
{ NULL } };
DEVICE ptp_dev = {
"PTP", &ptp_unit, ptp_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ptp_reset,
NULL, NULL, NULL };
/* TTY data structures
tty_dev TTY device descriptor
tty_unit TTY unit descriptor
tty_reg TTY register list
tty_mod TTy modifiers list
*/
#define TTI 0
#define TTO 1
UNIT tty_unit[] = {
{ UDATA (&tti_svc, UNIT_UC, 0), KBD_POLL_WAIT },
{ UDATA (&tto_svc, 0, 0), SERIAL_OUT_WAIT } };
REG tty_reg[] = {
{ ORDATA (BUF, tty_buf, 8) },
{ FLDATA (MODE, tty_mode, 0) },
{ FLDATA (READY, dev_ready, INT_V_TTY) },
{ FLDATA (ENABLE, dev_enable, INT_V_TTY) },
{ DRDATA (KPOS, tty_unit[TTI].pos, 31), PV_LEFT },
{ DRDATA (KTIME, tty_unit[TTI].wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TPOS, tty_unit[TTO].pos, 31), PV_LEFT },
{ DRDATA (TTIME, tty_unit[TTO].wait, 24), REG_NZ + PV_LEFT },
{ FLDATA (UC, tty_unit[TTI].flags, UNIT_V_UC), REG_HRO },
{ NULL } };
MTAB tty_mod[] = {
{ UNIT_UC, 0, "lower case", "LC", NULL },
{ UNIT_UC, UNIT_UC, "upper case", "UC", NULL },
{ 0 } };
DEVICE tty_dev = {
"TTY", tty_unit, tty_reg, tty_mod,
2, 10, 31, 1, 8, 8,
NULL, NULL, &tty_reset,
NULL, NULL, NULL };
/* CLK data structures
clk_dev CLK device descriptor
clk_unit CLK unit descriptor
clk_mod CLK modifiers
clk_reg CLK register list
*/
UNIT clk_unit = {
UDATA (&clk_svc, 0, 0), 16000 };
REG clk_reg[] = {
{ FLDATA (READY, dev_ready, INT_V_CLK) },
{ FLDATA (ENABLE, dev_enable, INT_V_CLK) },
{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS, clk_tps, 8), REG_NZ + PV_LEFT },
{ NULL } };
DEVICE clk_dev = {
"CLK", &clk_unit, clk_reg, NULL,
1, 0, 0, 0, 0, 0,
NULL, NULL, &clk_reset,
NULL, NULL, NULL };
/* Paper tape reader: IO routine */
int32 ptrio (int32 inst, int32 fnc, int32 dat)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 016) return IOBADFNC (dat); /* only fnc 0,1 */
if (fnc) sim_cancel (&ptr_unit); /* fnc 1? stop */
else sim_activate (&ptr_unit, ptr_unit.wait); /* fnc 0? start */
break;
case ioSKS: /* SKS */
if (fnc & 013) return IOBADFNC (dat); /* only fnc 0,4 */
if (((fnc == 0) && TST_READY (INT_PTR)) || /* fnc 0? skip rdy */
((fnc == 4) && !TST_INTREQ (INT_PTR))) /* fnc 4? skip !int */
return IOSKIP (dat);
break;
case ioINA: /* INA */
if (fnc & 007) return IOBADFNC (dat); /* only fnc 0,10 */
if (TST_READY (INT_PTR)) { /* ready? */
CLR_READY (INT_PTR); /* clear ready */
return IOSKIP (ptr_unit.buf | dat); } /* ret buf, skip */
break; } /* end case op */
return dat;
}
/* Unit service */
t_stat ptr_svc (UNIT *uptr)
{
int32 temp;
if ((ptr_unit.flags & UNIT_ATT) == 0) /* attached? */
return IORETURN (ptr_stopioe, SCPE_UNATT);
if ((temp = getc (ptr_unit.fileref)) == EOF) { /* read byte */
if (feof (ptr_unit.fileref)) {
if (ptr_stopioe) printf ("PTR end of file\n");
else return SCPE_OK; }
else perror ("PTR I/O error");
clearerr (ptr_unit.fileref);
return SCPE_IOERR; }
SET_READY (INT_PTR); /* set ready flag */
ptr_unit.buf = temp & 0377; /* get byte */
ptr_unit.pos = ftell (ptr_unit.fileref); /* update pos */
sim_activate (&ptr_unit, ptr_unit.wait); /* reactivate */
return SCPE_OK;
}
/* Reset routine */
t_stat ptr_reset (DEVICE *dptr)
{
CLR_READY (INT_PTR); /* clear ready, enb */
CLR_ENABLE (INT_PTR);
ptr_unit.buf = 0; /* clear buffer */
sim_cancel (&ptr_unit); /* deactivate unit */
return SCPE_OK;
}
/* Paper tape reader bootstrap routine */
#define PBOOT_START 1
#define PBOOT_SIZE (sizeof (pboot) / sizeof (int32))
static const int32 pboot[] = {
0010057, /* STA 57 */
0030001, /* OCP 1 */
0131001, /* READ, INA 1001 */
0002003, /* JMP READ */
0101040, /* SNZ */
0002003, /* JMP READ */
0010000, /* STA 0 */
0131001, /* READ1, INA 1001 */
0002010, /* JMP READ1 */
0041470, /* LGL 8 */
0130001, /* READ2, INA 1 */
0002013, /* JMP READ2 */
0110000, /* STA* 0 */
0024000, /* IRS 0 */
0100040 /* SZE */
};
t_stat ptr_boot (int32 unit)
{
int32 i;
for (i = 0; i < PBOOT_SIZE; i++) /* copy bootstrap */
M[PBOOT_START + i] = pboot[i];
PC = PBOOT_START;
return SCPE_OK;
}
/* Paper tape punch: IO routine */
int32 ptpio (int32 inst, int32 fnc, int32 dat)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 016) return IOBADFNC (dat); /* only fnc 0,1 */
if (fnc) { /* fnc 1? pwr off */
CLR_READY (INT_PTP); /* not ready */
ptp_power = 0; /* turn off power */
sim_cancel (&ptp_unit); } /* stop punch */
else if (ptp_power == 0) /* fnc 0? start */
sim_activate (&ptp_unit, ptp_ptime);
break;
case ioSKS: /* SKS */
if ((fnc & 012) || (fnc == 005)) /* only 0, 1, 4 */
return IOBADFNC (dat);
if (((fnc == 00) && TST_READY (INT_PTP)) || /* fnc 0? skip rdy */
((fnc == 01) /* fnc 1? skip ptp on */
&& (ptp_power || sim_is_active (&ptp_unit))) ||
((fnc == 04) && !TST_INTREQ (INT_PTP))) /* fnc 4? skip !int */
return IOSKIP (dat);
break;
case ioOTA: /* OTA */
if (fnc) return IOBADFNC (dat); /* only fnc 0 */
if (TST_READY (INT_PTP)) { /* if ptp ready */
CLR_READY (INT_PTP); /* clear ready */
ptp_unit.buf = dat & 0377; /* store byte */
sim_activate (&ptp_unit, ptp_unit.wait);
return IOSKIP (dat); } /* skip return */
break; }
return dat;
}
/* Unit service */
t_stat ptp_svc (UNIT *uptr)
{
SET_READY (INT_PTP); /* set flag */
if (ptp_power == 0) { /* power on? */
ptp_power = 1; /* ptp is ready */
return SCPE_OK; }
if ((ptp_unit.flags & UNIT_ATT) == 0) /* attached? */
return IORETURN (ptp_stopioe, SCPE_UNATT);
if (putc (ptp_unit.buf, ptp_unit.fileref) == EOF) { /* output byte */
perror ("PTP I/O error");
clearerr (ptp_unit.fileref);
return SCPE_IOERR; }
ptp_unit.pos = ftell (ptp_unit.fileref); /* update pos */
return SCPE_OK;
}
/* Reset routine */
t_stat ptp_reset (DEVICE *dptr)
{
CLR_READY (INT_PTP); /* clear ready, enb */
CLR_ENABLE (INT_PTP);
ptp_power = 0; /* power off */
ptp_unit.buf = 0; /* clear buffer */
sim_cancel (&ptp_unit); /* deactivate unit */
return SCPE_OK;
}
/* Terminal: IO routine */
int32 ttyio (int32 inst, int32 fnc, int32 dat)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 016) return IOBADFNC (dat); /* only fnc 0,1 */
if (fnc && (tty_mode == 0)) { /* input to output? */
if (!sim_is_active (&tty_unit[TTO])) SET_READY (INT_TTY);
tty_mode = 1; } /* mode is output */
else if ((fnc == 0) && tty_mode) { /* output to input? */
CLR_READY (INT_TTY); /* clear ready */
tty_mode = 0; } /* mode is input */
break;
case ioSKS: /* SKS */
if (fnc & 012) return IOBADFNC (dat); /* fnc 0,1,4,5 */
if (((fnc == 0) && TST_READY (INT_TTY)) || /* fnc 0? skip rdy */
((fnc == 1) && /* fnc 1? skip !busy */
tty_mode && !sim_is_active (&tty_unit[TTO])) ||
((fnc == 4) && !TST_INTREQ (INT_TTY)) || /* fnc 4? skip !int */
((fnc == 5) && /* fnc 5? skip !xoff */
!tty_mode && ((tty_buf & 0177) == 023)))
return IOSKIP (dat);
break;
case ioINA: /* INA */
if (fnc & 005) return IOBADFNC (dat); /* only 0,2,10,12 */
if (TST_READY (INT_TTY)) { /* ready? */
if (tty_mode == 0) CLR_READY (INT_TTY); /* inp? clear rdy */
return IOSKIP (dat |
(tty_buf & ((fnc & 002)? 077: 0377))); }
break;
case ioOTA:
if (fnc & 015) return IOBADFNC (dat); /* only 0,2 */
if (TST_READY (INT_TTY)) { /* ready? */
tty_buf = dat & 0377; /* store char */
if (fnc & 002) { /* binary mode? */
tty_buf = tty_buf | 0100; /* set ch 7 */
if (tty_buf & 040) tty_buf = tty_buf & 0277; }
if (tty_mode) {
sim_activate (&tty_unit[TTO], tty_unit[TTO].wait);
CLR_READY (INT_TTY); }
return IOSKIP (dat); }
break; } /* end case op */
return dat;
}
/* Unit service routines */
t_stat tti_svc (UNIT *uptr)
{
int32 temp;
sim_activate (&tty_unit[TTI], tty_unit[TTI].wait); /* continue poll */
if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp; /* no char or error? */
temp = temp & 0177;
if ((tty_unit[TTI].flags & UNIT_UC) && islower (temp)) /* force upper case? */
temp = toupper (temp);
if (tty_mode == 0) { /* input mode? */
tty_buf = temp | 0200; /* put char in buf */
tty_unit[TTI].pos = tty_unit[TTI].pos + 1;
SET_READY (INT_TTY); /* set flag */
sim_putchar (temp); } /* echo */
return SCPE_OK;
}
t_stat tto_svc (UNIT *uptr)
{
int32 ch, temp;
SET_READY (INT_TTY); /* set done flag */
ch = tty_buf & 0177; /* get char */
if ((tty_unit[TTO].flags & UNIT_UC) && islower (ch)) /* force upper case? */
ch = toupper (ch);
if ((temp = sim_putchar (ch)) != SCPE_OK) return temp; /* output char */
tty_unit[TTO].pos = tty_unit[TTO].pos + 1;
return SCPE_OK;
}
/* Reset routine */
t_stat tty_reset (DEVICE *dptr)
{
CLR_READY (INT_TTY); /* clear ready, enb */
CLR_ENABLE (INT_TTY);
tty_mode = 0; /* mode = input */
tty_buf = 0;
sim_activate (&tty_unit[TTI], tty_unit[TTI].wait); /* activate poll */
sim_cancel (&tty_unit[TTO]); /* cancel output */
return SCPE_OK;
}
/* Clock/options: IO routine */
int32 clkio (int32 inst, int32 fnc, int32 dat)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 015) return IOBADFNC (dat); /* only fnc 0,2 */
CLR_READY (INT_CLK); /* reset ready */
if (fnc) sim_cancel (&clk_unit); /* fnc = 2? stop */
else { if (!sim_is_active (&clk_unit)) /* fnc = 0? start */
sim_activate (&clk_unit, /* activate */
sim_rtc_init (clk_unit.wait)); } /* init calibr */
break;
case ioSKS: /* SKS */
if (fnc == 0) { /* clock skip !int */
if (!TST_INTREQ (INT_CLK)) return IOSKIP (dat); }
else if ((fnc & 007) == 002) { /* mem parity? */
if (((fnc == 002) && !TST_READY (INT_MPE)) ||
((fnc == 012) && TST_READY (INT_MPE)))
return IOSKIP (dat); }
else return IOBADFNC (dat); /* invalid fnc */
break;
case ioOTA: /* OTA */
if (fnc == 000) dev_enable = dat; /* SMK */
else if (fnc == 010) { /* OTK */
C = (dat >> 15) & 1; /* set C */
if (cpu_unit.flags & UNIT_HSA) /* HSA included? */
dp = (dat >> 14) & 1; /* set dp */
if (cpu_unit.flags & UNIT_EXT) { /* ext opt? */
if (dat & 020000) { /* ext set? */
ext = 1; /* yes, set */
extoff_pending = 0; }
else extoff_pending = 1; } /* no, clr later */
sc = dat & 037; } /* set sc */
else return IOBADFNC (dat);
break; }
return dat;
}
/* Unit service */
t_stat clk_svc (UNIT *uptr)
{
M[M_CLK] = M[M_CLK + 1] & DMASK; /* increment mem ctr */
if (M[M_CLK] == 0) SET_READY (INT_CLK); /* = 0? set flag */
sim_activate (&clk_unit, sim_rtc_calb (clk_tps)); /* reactivate */
return SCPE_OK;
}
/* Reset routine */
t_stat clk_reset (DEVICE *dptr)
{
CLR_READY (INT_CLK); /* clear ready, enb */
CLR_ENABLE (INT_CLK);
sim_cancel (&clk_unit); /* deactivate unit */
return SCPE_OK;
}

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/* h316_sys.c: Honeywell 316/516 simulator interface
Copyright (c) 1993-2001, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
17-Sep-01 RMS Removed multiconsole support
*/
#include "h316_defs.h"
#include <ctype.h>
extern DEVICE cpu_dev;
extern UNIT cpu_unit;
extern DEVICE ptr_dev, ptp_dev;
extern DEVICE tty_dev, lpt_dev;
extern DEVICE clk_dev;
extern REG cpu_reg[];
extern uint16 M[];
extern int32 sim_switches;
/* SCP data structures and interface routines
sim_name simulator name string
sim_PC pointer to saved PC register descriptor
sim_emax maximum number of words for examine/deposit
sim_devices array of pointers to simulated devices
sim_stop_messages array of pointers to stop messages
sim_load binary loader
*/
char sim_name[] = "H316";
REG *sim_PC = &cpu_reg[0];
int32 sim_emax = 1;
DEVICE *sim_devices[] = { &cpu_dev,
&ptr_dev, &ptp_dev,
&tty_dev, &lpt_dev,
&clk_dev,
NULL };
const char *sim_stop_messages[] = {
"Unknown error",
"Unimplemented instruction",
"Unimplemented I/O device",
"HALT instruction",
"Breakpoint",
"Indirect address loop" };
/* Binary loader
Tbs.
*/
t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
return SCPE_FMT;
}
/* Symbol tables */
#define I_V_FL 16 /* flag start */
#define I_M_FL 07 /* flag mask */
#define I_V_NPN 0 /* no operand */
#define I_V_MRF 1 /* mem ref */
#define I_V_MRX 2 /* mem ref, no idx */
#define I_V_IOT 3 /* I/O */
#define I_V_SHF 4 /* shift */
#define I_V_SK0 5 /* skip 0 */
#define I_V_SK1 6 /* skip 1 */
#define I_NPN (I_V_NPN << I_V_FL)
#define I_MRF (I_V_MRF << I_V_FL)
#define I_MRX (I_V_MRX << I_V_FL)
#define I_IOT (I_V_IOT << I_V_FL)
#define I_SHF (I_V_SHF << I_V_FL)
#define I_SK0 (I_V_SK0 << I_V_FL)
#define I_SK1 (I_V_SK1 << I_V_FL)
static const int32 masks[] = {
0177777, 0136000, 0176000, 0176000,
0177700, 0177000, 0177000 };
static const char *opcode[] = {
"HLT", "SGL", "DBL",
"DXA", "EXA", "RMP",
"SCA", "INK", "NRM",
"IAB", "ENB", "INH", "ERM",
"CHS", "CRA", "SSP",
"RCB", "CSA", "CMA",
"TCA", "SSM", "SCB",
"CAR", "CAL", "ICL",
"AOA", "ACA", "ICR", "ICA",
"NOP", "SKP", "SSR", "SSS",
"JMP", "JMP*",
"LDA", "LDA*", "ANA", "ANA*",
"STA", "STA*", "ERA", "ERA*",
"ADD", "ADD*", "SUB", "SUB*",
"JST", "JST*", "CAS", "CAS*",
"IRS", "IRS*", "IMA", "IMA*",
"MPY", "MPY*", "DIV", "DIV*",
"STX", "STX*", "LDX", "LDX*",
"LRL", "LRS", "LRR",
"LGR", "ARS", "ARR",
"LLL", "LLS", "LLR",
"LGL", "ALS", "ALR",
"OCP", "SKS", "INA", "OTA",
"SMK",
"SPL", "SPN", "SLZ", /* encode only */
"SZE", "SR1", "SR2",
"SR3", "SR4", "SRC",
"SMI", "SPS", "SLN",
"SNZ", "SS1", "SS2",
"SS3", "SS4", "SSC",
NULL, NULL, /* decode only */
NULL };
static const int32 opc_val[] = {
0000000+I_NPN, 0000005+I_NPN, 0000007+I_NPN,
0000011+I_NPN, 0000013+I_NPN, 0000021+I_NPN,
0000041+I_NPN, 0000043+I_NPN, 0000101+I_NPN,
0000201+I_NPN, 0000401+I_NPN, 0001001+I_NPN, 0001401+I_NPN,
0140024+I_NPN, 0140040+I_NPN, 0140100+I_NPN,
0140200+I_NPN, 0140320+I_NPN, 0140401+I_NPN,
0140407+I_NPN, 0140500+I_NPN, 0140600+I_NPN,
0141044+I_NPN, 0141050+I_NPN, 0141140+I_NPN,
0141206+I_NPN, 0141216+I_NPN, 0141240+I_NPN, 0141340+I_NPN,
0101000+I_NPN, 0100000+I_NPN, 0100036+I_NPN, 0101036+I_NPN,
0002000+I_MRF, 0102000+I_MRF,
0004000+I_MRF, 0104000+I_MRF, 0006000+I_MRF, 0106000+I_MRF,
0010000+I_MRF, 0110000+I_MRF, 0012000+I_MRF, 0112000+I_MRF,
0014000+I_MRF, 0114000+I_MRF, 0016000+I_MRF, 0116000+I_MRF,
0020000+I_MRF, 0120000+I_MRF, 0022000+I_MRF, 0122000+I_MRF,
0024000+I_MRF, 0124000+I_MRF, 0026000+I_MRF, 0126000+I_MRF,
0034000+I_MRF, 0134000+I_MRF, 0036000+I_MRF, 0136000+I_MRF,
0032000+I_MRX, 0132000+I_MRX, 0072000+I_MRX, 0172000+I_MRX,
0040000+I_SHF, 0040100+I_SHF, 0040200+I_SHF,
0040400+I_SHF, 0040500+I_SHF, 0040600+I_SHF,
0041000+I_SHF, 0041100+I_SHF, 0041200+I_SHF,
0041400+I_SHF, 0041500+I_SHF, 0041600+I_SHF,
0030000+I_IOT, 0070000+I_IOT, 0130000+I_IOT, 0170000+I_IOT,
0170000+I_IOT,
0100400+I_SK0, 0100200+I_SK0, 0100100+I_SK0, /* encode only */
0100040+I_SK0, 0100020+I_SK0, 0100010+I_SK0,
0100004+I_SK0, 0100002+I_SK0, 0100001+I_SK0,
0101400+I_SK1, 0101200+I_SK1, 0101100+I_SK1,
0101040+I_SK1, 0101020+I_SK1, 0101010+I_SK1,
0101004+I_SK1, 0101002+I_SK1, 0101001+I_SK1,
0100000+I_SK0, 0101000+I_SK1, /* decode only */
-1 };
/* Operate decode
Inputs:
*of = output stream
inst = mask bits
class = instruction class code
sp = space needed?
Outputs:
status = space needed
*/
int32 fprint_opr (FILE *of, int32 inst, int32 class, int32 sp)
{
int32 i, j;
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
if ((j == class) && (opc_val[i] & inst)) { /* same class? */
inst = inst & ~opc_val[i]; /* mask bit set? */
fprintf (of, (sp? " %s": "%s"), opcode[i]);
sp = 1; } }
return sp;
}
/* Symbolic decode
Inputs:
*of = output stream
addr = current PC
*val = pointer to data
*uptr = pointer to unit
sw = switches
Outputs:
return = status code
*/
#define FMTASC(x) ((x) < 040)? "<%03o>": "%c", (x)
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw)
{
int32 cflag, i, j, inst, disp;
cflag = (uptr == NULL) || (uptr == &cpu_unit);
inst = val[0];
if (sw & SWMASK ('A')) { /* ASCII? */
if (inst > 0377) return SCPE_ARG;
fprintf (of, FMTASC (inst & 0177));
return SCPE_OK; }
if (sw & SWMASK ('C')) { /* characters? */
fprintf (of, FMTASC ((inst >> 8) & 0177));
fprintf (of, FMTASC (inst & 0177));
return SCPE_OK; }
if (!(sw & SWMASK ('M'))) return SCPE_ARG;
/* Instruction decode */
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
if ((opc_val[i] & DMASK) == (inst & masks[j])) { /* match? */
switch (j) { /* case on class */
case I_V_NPN: /* no operands */
fprintf (of, "%s", opcode[i]); /* opcode */
break;
case I_V_MRF: case I_V_MRX: /* mem ref */
disp = inst & DISP; /* displacement */
fprintf (of, "%s ", opcode[i]); /* opcode */
if (inst & SC) { /* current sector? */
if (cflag) fprintf (of, "%-o", (addr & PAGENO) | disp);
else fprintf (of, "C %-o", disp); }
else fprintf (of, "%-o", disp); /* sector zero */
if ((j == I_V_MRF) && (inst & IDX)) fprintf (of, ",1");
break;
case I_V_IOT: /* I/O */
disp = inst & 01777; /* pulse+dev */
fprintf (of, "%s %o", opcode[i], disp);
break;
case I_V_SHF: /* shift */
disp = -inst & SHFMASK; /* shift count */
fprintf (of, "%s %o", opcode[i], disp);
break;
case I_V_SK0: case I_V_SK1: /* skips */
fprint_opr (of, inst & 0777, j, 0); /* print skips */
break; } /* end case */
return SCPE_OK; } /* end if */
} /* end for */
return SCPE_ARG;
}
/* Symbolic input
Inputs:
*cptr = pointer to input string
addr = current PC
*uptr = pointer to unit
*val = pointer to output values
sw = switches
Outputs:
status = error status
*/
t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
{
int32 cflag, d, i, j, k;
t_stat r;
char gbuf[CBUFSIZE];
cflag = (uptr == NULL) || (uptr == &cpu_unit);
while (isspace (*cptr)) cptr++; /* absorb spaces */
if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
val[0] = (t_value) cptr[0] & 0177;
return SCPE_OK; }
if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* char string? */
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
val[0] = (((t_value) cptr[0] & 0177) << 8) |
((t_value) cptr[1] & 0177);
return SCPE_OK; }
/* Instruction parse */
cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
if (opcode[i] == NULL) return SCPE_ARG;
val[0] = opc_val[i] & DMASK; /* get value */
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
switch (j) { /* case on class */
case I_V_NPN: /* no operand */
break;
case I_V_IOT: /* IOT */
cptr = get_glyph (cptr, gbuf, 0); /* get pulse+dev */
d = get_uint (gbuf, 8, 01777, &r);
if (r != SCPE_OK) return SCPE_ARG;
val[0] = val[0] | d;
break;
case I_V_SHF: /* shift */
cptr = get_glyph (cptr, gbuf, 0); /* get shift count */
d = get_uint (gbuf, 8, SHFMASK, &r);
if (r != SCPE_OK) return SCPE_ARG;
val[0] = val[0] | (-d & SHFMASK); /* store 2's comp */
break;
case I_V_MRF: case I_V_MRX: /* mem ref */
cptr = get_glyph (cptr, gbuf, ','); /* get next field */
if (k = (strcmp (gbuf, "C") == 0)) { /* C specified? */
val[0] = val[0] | SC;
cptr = get_glyph (cptr, gbuf, 0); }
else if (k = (strcmp (gbuf, "Z") == 0)) { /* Z specified? */
cptr = get_glyph (cptr, gbuf, ','); }
d = get_uint (gbuf, 8, X_AMASK, &r); /* construe as addr */
if (r != SCPE_OK) return SCPE_ARG;
if (d <= DISP) val[0] = val[0] | d; /* fits? */
else if (cflag && !k && (((addr ^ d) & PAGENO) == 0))
val[0] = val[0] | (d & DISP) | SC;
else return SCPE_ARG;
if ((j == I_V_MRX) || (*cptr == 0)) break; /* indexed? */
cptr = get_glyph (cptr, gbuf, 0);
d = get_uint (gbuf, 8, 1, &r); /* get tag */
if (r != SCPE_OK) return SCPE_ARG;
if (d) val[0] = val[0] | IDX; /* or in index */
break;
case I_V_SK0: case I_V_SK1: /* skips */
for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
cptr = get_glyph (cptr, gbuf, 0)) {
for (i = 0; (opcode[i] != NULL) &&
(strcmp (opcode[i], gbuf) != 0) ; i++) ;
k = opc_val[i] & DMASK;
if ((opcode[i] == NULL) || (((k ^ val[0]) & 0177000) != 0))
return SCPE_ARG;
val[0] = val[0] | k; }
break; } /* end case */
if (*cptr != 0) return SCPE_ARG; /* junk at end? */
return SCPE_OK;
}