github.com/simh.simh
1
0
Fork 0
mirror of https://github.com/simh/simh.git synced 2026-02-18 05:24:41 +00:00
Code Releases Activity

Notes For V2.8

Browse Source 
1. New Features

1.1 Directory and documentation

- Only common files (SCP and libraries) are in the top level
  directory.  Individual simulator files are in their individual
  directories.
- simh_doc.txt has been split up.  simh_doc.txt now documents
  only SCP.  The individual simulators are documented in separate
  text files in their own directories.
- mingw_build.bat is a batch file for the MINGW/gcc environment
  that will build all the simulators, assuming the root directory
  structure is at c:\sim.
- Makefile is a UNIX make file for the gcc environment that will
  build all the simulators, assuming the root directory is at
  c:\sim.

1.2 SCP

- DO <file name> executes the SCP commands in the specified file.
- Replicated registers in unit structures can now be declared as
  arrays for examine, modify, save, and restore.  Most replicated
  unit registers (for example, mag tape position registers) have
  been changed to arrays.
- The ADD/REMOVE commands have been replaced by SET unit ONLINE
  and SET unit OFFLINE, respectively.
- Register names that are unique within an entire simulator do
  not have to be prefaced with the device name.
- The ATTACH command can attach files read only, either under
  user option (-r), or because the attached file is ready only.
- The SET/SHOW capabilities have been extended.  New forms include:

	SET <dev> param{=value}{ param ...}
	SET <unit> param{=value}{ param ...}
	SHOW <dev> {param param ...}
	SHOW <unit> {param param ...}

- Multiple breakpoints have been implemented.  Breakpoints are
  set/cleared/displayed by:

	BREAK addr_list{[count]}
	NOBREAK addr_list
	SHOW BREAK addr_list

1.3 PDP-11 simulator

- Unibus map implemented, with 22b RP controller (URH70) or 18b
  RP controller (URH11) (in debug).
- All DMA peripherals rewritten to use map.
- Many peripherals modified for source sharing with VAX.
- RQDX3 implemented.
- Bugs fixed in RK11 and RL11 write check.

1.4 PDP-10 simulator

- ITS 1-proceed implemented.
- Bugs fixed in ITS PC sampling and LPMR

1.5 18b PDP simulator

- Interrupts split out to multiple levels to allow easier
  expansion.

1.5 IBM System 3 Simulator

- Written by Charles (Dutch) Owen.

1.6 VAX Simulator (in debug)

- Simulates MicroVAX 3800 (KA655) with 16MB-64MB memory, RQDX3,
  RLV12, TSV11, DZV11, LPV11, PCV11.
- CDROM capability has been added to the RQDX3, to allow testing
  with VMS hobbyist images.

1.7 SDS 940 Simulator (not tested)

- Simulates SDS 940, 16K-64K memory, fixed and moving head
  disk, magtape, line printer, console.

1.8 Altair Z80

- Revised from Charles (Dutch) Owen's original by Peter Schorn.
- MITS 8080 with full Z80 simulation.
- 4K and 8K BASIC packages, Prolog package.

1.9 Interdata

The I4 simulator has been withdrawn for major rework.  Look for
a complete 16b/32b Interdata simulator sometime next year.

2. Release Notes

2.1 SCP

SCP now allows replicated registers in unit structures to be
modelled as arrays.  All replicated register declarations have
been replaced by register array declarations.  As a result,
save files from prior revisions will generate errors after
restoring main memory.

2.2 PDP-11

The Unibus map code is in debug.  The map was implemented primarily
to allow source sharing with the VAX, which requires a DMA map.
DMA devices work correctly with the Unibus map disabled.

The RQDX3 simulator has run a complete RSTS/E SYSGEN, with multiple
drives, and booted the completed system from scratch.

2.3 VAX

The VAX simulator will run the boot code up to the >>> prompt.  It
can successfully process a SHOW DEVICE command.  It runs the HCORE
instruction diagnostic.  It can boot the hobbyist CD through SYSBOOT
and through the date/time dialog and restore the hobbyist CD, using
standalone backup.  On the boot of the restored disk, it gets to the
date/time dialog, and then crashes.

2.4 SDS 940

The SDS 940 is untested, awaiting real code.

2.5 GCC Optimization

At -O2 and above, GCC does not correctly compile the simulators which
use setjmp-longjmp (PDP-11, PDP-10, VAX).  A working hypothesis is
that optimized state maintained in registers is being used in the
setjmp processing routine.  On the PDP-11 and PDP-10, all of this
state has been either made global, or volatile, to encourage GCC to
keep the state up to date in memory.  The VAX is still vulnerable.

3. Work list

3.1 SCP

- Better ENABLE/DISABLE.

3.2 PDP-11 RQDX3

Software mapped mode, RCT read simulation, VMS debug.
This commit is contained in:
Bob Supnik
2001-12-26 09:38:00 -08:00
committed by Mark Pizzolato
parent 654937fc88
commit 701f0fe028
145 changed files with 23190 additions and 9807 deletions
Download Patch File Download Diff File Expand all files Collapse all files

282
I1401/i1401_cd.c Normal file
View File

@@ -0,0 +1,282 @@
/* i1401_cd.c: IBM 1402 card reader/punch
Copyright (c) 1993-2001, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
cdr card reader
cdp card punch
stack stackers (5 units)
0 normal
1 1
2 2/8
3 unused
4 4
Cards are represented as ASCII text streams terminated by newlines.
This allows cards to be created and edited as normal files.
29-Nov-01 RMS Added read only unit support
13-Apr-01 RMS Revised for register arrays
*/
#include "i1401_defs.h"
#include <ctype.h>
extern uint8 M[];
extern int32 ind[64], ssa, iochk;
extern char bcd_to_ascii[64];
extern char ascii_to_bcd[128];
int32 s1sel, s2sel, s4sel, s8sel;
char rbuf[CBUFSIZE]; /* > CDR_WIDTH */
t_stat cdr_svc (UNIT *uptr);
t_stat cdr_boot (int32 unitno);
t_stat cdr_attach (UNIT *uptr, char *cptr);
t_stat cd_reset (DEVICE *dptr);
/* Card reader data structures
cdr_dev CDR descriptor
cdr_unit CDR unit descriptor
cdr_reg CDR register list
*/
UNIT cdr_unit = {
UDATA (&cdr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0), 100 };
REG cdr_reg[] = {
{ FLDATA (LAST, ind[IN_LST], 0) },
{ FLDATA (ERR, ind[IN_READ], 0) },
{ FLDATA (S1, s1sel, 0) },
{ FLDATA (S2, s2sel, 0) },
{ DRDATA (POS, cdr_unit.pos, 31), PV_LEFT },
{ DRDATA (TIME, cdr_unit.wait, 24), PV_LEFT },
{ BRDATA (BUF, rbuf, 8, 8, CDR_WIDTH) },
{ NULL } };
DEVICE cdr_dev = {
"CDR", &cdr_unit, cdr_reg, NULL,
1, 10, 31, 1, 8, 7,
NULL, NULL, &cd_reset,
&cdr_boot, &cdr_attach, NULL };
/* CDP data structures
cdp_dev CDP device descriptor
cdp_unit CDP unit descriptor
cdp_reg CDP register list
*/
UNIT cdp_unit = {
UDATA (NULL, UNIT_SEQ+UNIT_ATTABLE, 0) };
REG cdp_reg[] = {
{ FLDATA (ERR, ind[IN_PNCH], 0) },
{ FLDATA (S4, s4sel, 0) },
{ FLDATA (S8, s8sel, 0) },
{ DRDATA (POS, cdp_unit.pos, 31), PV_LEFT },
{ NULL } };
DEVICE cdp_dev = {
"CDP", &cdp_unit, cdp_reg, NULL,
1, 10, 31, 1, 8, 7,
NULL, NULL, &cd_reset,
NULL, NULL, NULL };
/* Stacker data structures
stack_dev STACK device descriptor
stack_unit STACK unit descriptors
stack_reg STACK register list
*/
UNIT stack_unit[] = {
{ UDATA (NULL, UNIT_SEQ+UNIT_ATTABLE, 0) },
{ UDATA (NULL, UNIT_SEQ+UNIT_ATTABLE, 0) },
{ UDATA (NULL, UNIT_SEQ+UNIT_ATTABLE, 0) },
{ UDATA (NULL, UNIT_DIS, 0) }, /* unused */
{ UDATA (NULL, UNIT_SEQ+UNIT_ATTABLE, 0) } };
REG stack_reg[] = {
{ DRDATA (POS0, stack_unit[0].pos, 31), PV_LEFT },
{ DRDATA (POS1, stack_unit[1].pos, 31), PV_LEFT },
{ DRDATA (POS28, stack_unit[2].pos, 31), PV_LEFT },
{ DRDATA (POS4, stack_unit[4].pos, 31), PV_LEFT },
{ NULL } };
DEVICE stack_dev = {
"STKR", stack_unit, stack_reg, NULL,
5, 10, 31, 1, 8, 7,
NULL, NULL, &cd_reset,
NULL, NULL, NULL };
/* Card read routine
Modifiers have been checked by the caller
No modifiers are recognized (column binary is not implemented)
*/
t_stat read_card (int32 ilnt, int32 mod)
{
int32 i;
t_stat r;
if (sim_is_active (&cdr_unit)) { /* busy? */
sim_cancel (&cdr_unit); /* cancel */
if (r = cdr_svc (&cdr_unit)) return r; } /* process */
if ((cdr_unit.flags & UNIT_ATT) == 0) return SCPE_UNATT; /* attached? */
ind[IN_READ] = ind[IN_LST] = s1sel = s2sel = 0; /* default stacker */
for (i = 0; i < CBUFSIZE; i++) rbuf[i] = 0; /* clear buffer */
fgets (rbuf, CBUFSIZE, cdr_unit.fileref); /* read card */
if (feof (cdr_unit.fileref)) return STOP_NOCD; /* eof? */
if (ferror (cdr_unit.fileref)) { /* error? */
perror ("Card reader I/O error");
clearerr (cdr_unit.fileref);
if (iochk) return SCPE_IOERR;
ind[IN_READ] = 1;
return SCPE_OK; }
cdr_unit.pos = ftell (cdr_unit.fileref); /* update position */
if (ssa) { /* if last cd on */
i = getc (cdr_unit.fileref); /* see if more */
if (feof (cdr_unit.fileref)) ind[IN_LST] = 1; /* eof? set flag */
fseek (cdr_unit.fileref, cdr_unit.pos, SEEK_SET); }
for (i = 0; i < CDR_WIDTH; i++) { /* cvt to BCD */
rbuf[i] = ascii_to_bcd[rbuf[i]];
M[CDR_BUF + i] = (M[CDR_BUF + i] & WM) | rbuf[i]; }
M[CDR_BUF - 1] = 060; /* mem mark */
sim_activate (&cdr_unit, cdr_unit.wait); /* activate */
return SCPE_OK;
}
/* Card reader service. If a stacker select is active, copy to the
selected stacker. Otherwise, copy to the normal stacker. If the
unit is unattached, simply exit.
*/
t_stat cdr_svc (UNIT *uptr)
{
int32 i;
if (s1sel) uptr = &stack_unit[1]; /* stacker 1? */
else if (s2sel) uptr = &stack_unit[2]; /* stacker 2? */
else uptr = &stack_unit[0]; /* then default */
if ((uptr -> flags & UNIT_ATT) == 0) return SCPE_OK; /* attached? */
for (i = 0; i < CDR_WIDTH; i++) rbuf[i] = bcd_to_ascii[rbuf[i]];
for (i = CDR_WIDTH - 1; (i >= 0) && (rbuf[i] == ' '); i--) rbuf[i] = 0;
rbuf[CDR_WIDTH] = 0; /* null at end */
fputs (rbuf, uptr -> fileref); /* write card */
fputc ('\n', uptr -> fileref); /* plus new line */
if (ferror (uptr -> fileref)) { /* error? */
perror ("Card stacker I/O error");
clearerr (uptr -> fileref);
if (iochk) return SCPE_IOERR; }
uptr -> pos = ftell (uptr -> fileref); /* update position */
return SCPE_OK;
}
/* Card punch routine
Modifiers have been checked by the caller
No modifiers are recognized (column binary is not implemented)
*/
t_stat punch_card (int32 ilnt, int32 mod)
{
int32 i;
static char pbuf[CDP_WIDTH + 1]; /* + null */
UNIT *uptr;
if (s8sel) uptr = &stack_unit[2]; /* stack 8? */
else if (s4sel) uptr = &stack_unit[4]; /* stack 4? */
else uptr = &cdp_unit; /* normal output */
if ((uptr -> flags & UNIT_ATT) == 0) return SCPE_UNATT; /* attached? */
ind[IN_PNCH] = s4sel = s8sel = 0; /* clear flags */
M[CDP_BUF - 1] = 012; /* set prev loc */
for (i = 0; i < CDP_WIDTH; i++) pbuf[i] = bcd_to_ascii[M[CDP_BUF + i] & CHAR];
for (i = CDP_WIDTH - 1; (i >= 0) && (pbuf[i] == ' '); i--) pbuf[i] = 0;
pbuf[CDP_WIDTH] = 0; /* trailing null */
fputs (pbuf, uptr -> fileref); /* output card */
fputc ('\n', uptr -> fileref); /* plus new line */
if (ferror (uptr -> fileref)) { /* error? */
perror ("Card punch I/O error");
clearerr (uptr -> fileref);
if (iochk) return SCPE_IOERR;
ind[IN_PNCH] = 1; }
uptr -> pos = ftell (uptr -> fileref); /* update position */
return SCPE_OK;
}
/* Select stack routine
Modifiers have been checked by the caller
Modifiers are 1, 2, 4, 8 for the respective stack
*/
t_stat select_stack (int32 ilnt, int32 mod)
{
if (mod == 1) s1sel = 1;
else if (mod == 2) s2sel = 1;
else if (mod == 4) s4sel = 1;
else if (mod == 8) s8sel = 1;
return SCPE_OK;
}
/* Card reader/punch reset */
t_stat cd_reset (DEVICE *dptr)
{
ind[IN_LST] = ind[IN_READ] = ind[IN_PNCH] = 0; /* clear indicators */
s1sel = s2sel = s4sel = s8sel = 0; /* clear stacker sel */
sim_cancel (&cdr_unit); /* clear reader event */
return SCPE_OK;
}
/* Card reader attach */
t_stat cdr_attach (UNIT *uptr, char *cptr)
{
ind[IN_LST] = ind[IN_READ] = 0; /* clear last card */
return attach_unit (uptr, cptr);
}
/* Bootstrap routine */
#define BOOT_START 100
#define BOOT_LEN (sizeof (boot_rom) / sizeof (unsigned char))
static const unsigned char boot_rom[] = {
OP_R + WM, /* R */
OP_SWM + WM, BCD_ZERO, BCD_ZERO, BCD_ONE, /* SWM 001 */
OP_CS + WM, BCD_ZERO, BCD_ZERO, BCD_ONE, /* CS 001 111 */
BCD_ONE, BCD_ONE, BCD_ONE };
t_stat cdr_boot (int32 unitno)
{
int32 i;
extern int32 saved_IS;
for (i = 0; i < CDR_WIDTH; i++) M[CDR_BUF + i] = 0; /* clear buffer */
for (i = 0; i < BOOT_LEN; i++) M[BOOT_START + i] = boot_rom[i];
saved_IS = BOOT_START;
return SCPE_OK;
}

1097
I1401/i1401_cpu.c Normal file
View File

File diff suppressed because it is too large Load Diff

263
I1401/i1401_defs.h Normal file
View File

@@ -0,0 +1,263 @@
/* i1401_defs.h: IBM 1401 simulator definitions
Copyright (c) 1993-2001, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
14-Apr-99 RMS Converted t_addr to unsigned
This simulator is based on the 1401 simulator written by Len Fehskens
with assistance from Sarah Lee Harris and Bob Supnik. This one's for
you, Len. I am grateful to Paul Pierce and Charles Owen for their help
in answering questions, gathering source material, and debugging.
*/
#include "sim_defs.h"
/* Simulator stop codes */
#define STOP_NXI 1 /* unimpl instr */
#define STOP_NXM 2 /* non-exist mem */
#define STOP_NXD 3 /* non-exist dev */
#define STOP_NOWM 4 /* no WM under op */
#define STOP_INVA 5 /* invalid A addr */
#define STOP_INVB 6 /* invalid B addr */
#define STOP_INVL 7 /* invalid length */
#define STOP_INVM 8 /* invalid modifier */
#define STOP_INVBR 9 /* invalid branch */
#define STOP_IBKPT 10 /* breakpoint */
#define STOP_HALT 11 /* halt */
#define STOP_INVMTU 12 /* invalid MT unit */
#define STOP_MTZ 13 /* MT zero lnt rec */
#define STOP_MTL 14 /* MT write lock */
#define STOP_CCT 15 /* inv CCT channel */
#define STOP_NOCD 16 /* no cards left */
#define STOP_WRAP 17 /* AS, BS mem wrap */
#define STOP_MCE1 18 /* MCE short A field */
#define STOP_MCE2 19 /* MCE short B field */
#define STOP_MCE3 20 /* MCE hanging $ */
#define STOP_IOC 21 /* I/O check */
/* Memory and devices */
#define MAXMEMSIZE 16000 /* max memory */
#define MEMSIZE (cpu_unit.capac) /* current memory */
#define CDR_BUF 1 /* card rdr buffer */
#define CDR_WIDTH 80 /* card rdr width */
#define CDP_BUF 101 /* card punch buffer */
#define CDP_WIDTH 80 /* card punch width */
#define LPT_BUF 201 /* line print buffer */
#define LPT_WIDTH 132 /* line print width */
#define CCT_LNT 132 /* car ctrl length */
#define INQ_WIDTH 80 /* inq term width */
#define ADDR_ERR(x) (((t_addr) (x)) >= MEMSIZE)
/* Binary address format
<14:0> address, with index added in
<23:16> index register memory address
<25:24> address error bits
*/
#define ADDRMASK 037777 /* addr mask */
#define INDEXMASK 077777 /* addr + index mask */
#define V_INDEX 16
#define M_INDEX 0177
#define V_ADDRERR 24
#define BA (1 << V_ADDRERR) /* bad addr digit */
#define X1 (87 << V_INDEX) /* index reg 1 */
#define X2 (92 << V_INDEX) /* index reg 2 */
#define X3 (97 << V_INDEX) /* index reg 3 */
/* CPU instruction control flags. The flag definitions must be harmonized
with the UNIT flag definitions used by the simulator. */
/* Lengths */
#define L1 0001 /* 1: op */
#define L2 0002 /* 2: op d */
#define L4 0004 /* 4: op aaa */
#define L5 0010 /* 5: op aaa d */
#define L7 0020 /* 7: op aaa bbb */
#define L8 0040 /* 8: op aaa bbb d */
/* CPU options, stored in cpu_unit.flags */
#define MDV (1 << (UNIT_V_UF + 0)) /* multiply/divide */
#define MR (1 << (UNIT_V_UF + 1)) /* move record */
#define XSA (1 << (UNIT_V_UF + 2)) /* index, store addr */
#define EPE (1 << (UNIT_V_UF + 3)) /* expanded edit */
#define MA (1 << (UNIT_V_UF + 4)) /* modify address */
#define BBE (1 << (UNIT_V_UF + 5)) /* br bit equal */
#define HLE (1 << (UNIT_V_UF + 6)) /* high/low/equal */
#define UNIT_MSIZE (1 << (UNIT_V_UF + 7)) /* fake flag */
#define ALLOPT (MDV + MR + XSA + EPE + MA + BBE + HLE)
#define STDOPT (MR + XSA + EPE + MA + BBE + HLE)
/* Fetch control */
#define AREQ (1 << (UNIT_V_UF + 8)) /* validate A */
#define BREQ (1 << (UNIT_V_UF + 9)) /* validate B */
#define MLS (1 << (UNIT_V_UF + 10)) /* move load store */
#define NOWM (1 << (UNIT_V_UF + 11)) /* no WM at end */
#define HNOP (1 << (UNIT_V_UF + 12)) /* halt or nop */
#define IO (1 << (UNIT_V_UF + 13)) /* IO */
#define UNIT_BCD (1 << (UNIT_V_UF + 14)) /* BCD strings */
#if (UNIT_V_UF < 6) || ((UNIT_V_UF + 14) > 31)
Definition error: flags overlap
#endif
/* BCD memory character format */
#define WM 0100 /* word mark */
#define ZONE 0060 /* zone */
#define BBIT 0040 /* 1 in valid sign */
#define ABIT 0020 /* sign (1 = +) */
#define DIGIT 0017 /* digit */
#define CHAR 0077 /* character */
#define V_WM 6
#define V_ZONE 4
#define V_DIGIT 0
/* Interesting BCD characters */
#define BCD_BLANK 000
#define BCD_ONE 001
#define BCD_TWO 002
#define BCD_THREE 003
#define BCD_FOUR 004
#define BCD_FIVE 005
#define BCD_SIX 006
#define BCD_SEVEN 007
#define BCD_EIGHT 010
#define BCD_NINE 011
#define BCD_ZERO 012
#define BCD_ALT 020
#define BCD_S 022
#define BCD_U 024
#define BCD_W 026
#define BCD_RECMRK 032
#define BCD_COMMA 033
#define BCD_PERCNT 034
#define BCD_WM 035
#define BCD_BS 036
#define BCD_TS 037
#define BCD_MINUS 040
#define BCD_M 044
#define BCD_R 051
#define BCD_DOLLAR 053
#define BCD_ASTER 054
#define BCD_AMPER 060
#define BCD_B 062
#define BCD_C 063
#define BCD_E 065
#define BCD_DECIMAL 073
#define BCD_SQUARE 074
#define BCD_GRPMRK 077
/* Opcodes */
#define OP_R 001 /* read */
#define OP_W 002 /* write */
#define OP_WR 003 /* write and read */
#define OP_P 004 /* punch */
#define OP_RP 005 /* read and punch */
#define OP_WP 006 /* write and punch */
#define OP_WRP 007 /* write read punch */
#define OP_RF 010 /* reader feed */
#define OP_PF 011 /* punch feed */
#define OP_MA 013 /* modify address */
#define OP_MUL 014 /* multiply */
#define OP_CS 021 /* clear storage */
#define OP_S 022 /* subtract */
#define OP_MTF 024 /* magtape function */
#define OP_BWZ 025 /* branch wm or zone */
#define OP_BBE 026 /* branch bit equal */
#define OP_MZ 030 /* move zone */
#define OP_MSZ 031 /* move suppr zeroes */
#define OP_SWM 033 /* set word mark */
#define OP_DIV 034 /* divide */
#define OP_SS 042 /* select stacker */
#define OP_LCA 043 /* load characters */
#define OP_MCW 044 /* move characters */
#define OP_NOP 045 /* no op */
#define OP_MCM 047 /* move to rec/grp mk */
#define OP_SAR 050 /* store A register */
#define OP_ZS 052 /* zero and subtract */
#define OP_A 061 /* add */
#define OP_B 062 /* branch */
#define OP_C 063 /* compare */
#define OP_MN 064 /* move numeric */
#define OP_MCE 065 /* move char and edit */
#define OP_CC 066 /* carriage control */
#define OP_SBR 070 /* store B register */
#define OP_ZA 072 /* zero and add */
#define OP_H 073 /* halt */
#define OP_CWM 074 /* clear word mark */
/* I/O addresses */
#define IO_INQ 023 /* inquiry terminal */
#define IO_MT 024 /* magtape */
#define IO_MTB 062 /* binary magtape */
#define IO_DP 066 /* 1311 diskpack */
/* I/O modes */
#define MD_NORM 0 /* normal (move) */
#define MD_WM 1 /* word mark (load) */
#define MD_BIN 2 /* binary */
/* Indicator characters */
#define IN_UNC 000 /* unconditional */
#define IN_CC9 011 /* carr ctrl chan 9 */
#define IN_CC12 014 /* carr ctrl chan 12 */
#define IN_UNQ 021 /* unequal */
#define IN_EQU 022 /* equal */
#define IN_LOW 023 /* low */
#define IN_HGH 024 /* high */
#define IN_PAR 025 /* parity check */
#define IN_LNG 026 /* wrong lnt record */
#define IN_UNA 027 /* unequal addr cmp */
#define IN_DSK 030 /* disk error */
#define IN_OVF 031 /* overflow */
#define IN_LPT 032 /* printer error */
#define IN_PRO 034 /* process check */
#define IN_END 042 /* end indicator */
#define IN_TAP 043 /* tape error */
#define IN_ACC 045 /* access error */
#define IN_BSY 047 /* printer busy */
#define IN_INR 050 /* inquiry request */
#define IN_PCB 051 /* printer carr busy */
#define IN_PNCH 052 /* punch error */
#define IN_INC 054 /* inquiry clear */
#define IN_LST 061 /* last card */
#define IN_SSB 062 /* sense switch B */
#define IN_SSC 063 /* sense switch C */
#define IN_SSD 064 /* sense switch D */
#define IN_SSE 065 /* sense switch E */
#define IN_SSF 066 /* sense switch F */
#define IN_SSG 067 /* sense switch G */
#define IN_READ 072 /* reader error */

428
I1401/i1401_doc.txt Normal file
View File

@@ -0,0 +1,428 @@
To: Users
From: Bob Supnik
Subj: IBM 1401 Simulator Usage
Date: 1-Dec-01
COPYRIGHT NOTICE
The following copyright notice applies to both the SIMH source and binary:
Original code published in 1993-2001, written by Robert M Supnik
Copyright (c) 1993-2001, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
This memorandum documents the IBM 1401 simulator.
1. Simulator Files
sim/ sim_defs.h
scp.c
scp_tty.c
sim_rev.c
sim/i1401/ i1401_defs.h
i1401_cpu.c
i1401_iq.c
i1401_lp.c
i1401_mt.c
i1401_sys.c
2. IBM 1401 Features
The IBM 1401 simulator is configured as follows:
device simulates
name(s)
CPU IBM 1401 CPU with 16K of memory
CDR,CDP IBM 1402 card reader/punch
LPT IBM 1403 line printer
INQ IBM 1407 inquiry terminal
MT IBM 729 7-track magnetic tape controller with six drives
The IBM 1401 simulator implements many unique stop conditions. On almost
any kind of error the simulator stops:
unimplemented opcode
reference to non-existent memory
reference to non-existent device
no word mark under opcode
invalid A address
invalid B address
invalid instruction length
invalid modifier character
invalid branch address
invalid magtape unit number
invalid magtape record length
write to locked magtape drive
skip to unpunched carriage control tape channel
card reader hopper empty
address register wrap-around
single character A field in MCE
single character B field in MCE
hanging $ in MCE with EPE enabled
I/O check with I/O stop switch set
The LOAD and DUMP commands are not implemented.
2.1 CPU
The CPU options include a number of special features and the size of main
memory. Note that the Modify Address special feature is always included
when memory size is greater than 4K.
SET CPU XSA enable advanced programming special feature
SET CPU NOXSA disable advanced programming
SET CPU HLE enable high/low/equal special feature
SET CPU NOHLE disable high/low/equal
SET CPU BBE enable branch on bit equal special feature
SET CPU NOBBE disable branch on bit equal
SET CPU MR enable move record special feature
SET CPU NOMR disable move record
SET CPU EPE enable extended print edit special feature
SET CPU NOEPE disable extended print edit
SET CPU 4K set memory size = 4K
SET CPU 8K set memory size = 8K
SET CPU 12K set memory size = 12K
SET CPU 16K set memory size = 16K
If memory size is being reduced, and the memory being truncated contains
non-zero data, the simulator asks for confirmation. Data in the truncated
portion of memory is lost. Initially, memory size is 16K, and all special
features are enabled.
Memory is implemented as 7 bit BCD characters, as follows:
6 5 4 3 2 1 0
word B bit A bit 8 4 2 1
mark <-- zone --> <-------- digit -------->
In BCD, the decimal digits 0-9 are (octal) values 012, 001, 002, 003, 004,
005, 006, 007, 010, 011, respectively. Signs are encoded in the zone bits,
with 00, 01, and 11 being positive, and 10 being negative.
CPU registers include the visible state of the processor. The 1401 has no
interrupt system.
name size comments
IS 14 instruction storage address register (PC)
AS 14 A storage address register
BS 14 B storage address register
ASERR 1 AS invalid flag
BSERR 1 BS invalid flag
SSA 1 sense switch A
SSB 1 sense switch B
SSC 1 sense switch C
SSD 1 sense switch D
SSE 1 sense switch E
SSF 1 sense switch F
SSG 1 sense switch G
EQU 1 equal compare indicator
UNEQ 1 unequal compare indicator
HIGH 1 high compare indicator
LOW 1 low compare indicator
OVF 1 overflow indicator
IOCHK 1 I/O check switch
PRCHK 1 process check switch
OLDIS 1 IS prior to last branch
WRU 8 interrupt character
2.2 1402 Card Reader/Punch (CDR, CDP, STKR)
The IBM 1402 card/reader punch is simulated as three independent devices:
the card reader (CDR), the card punch (CDP), and the reader and punch
stackers (STKR). STRK units 0, 1, 2, and 4 correspond to the reader
normal stacker, reader stacker 1, shared stacker 2/8, and punch stacker
4, respectively.
The card reader supports the BOOT command. BOOT CDR reads a card image
into locations 1-80, sets a word mark under location 1, clears storage,
and then transfers control to location 1.
The card reader reads data from disk files, while the punch and stackers
write data to disk files. Cards are simulated as ASCII text lines with
terminating newlines; column binary is not supported. For each unit,
the POS register specifies the number of the next data item to be read or
written. Thus, by changing POS, the user can backspace or advance these
devices.
The reader/punch registers are:
device name size comments
CDR LAST 1 last card indicator
ERR 1 error indicator
S1 1 stacker 1 select flag
S2 1 stacker 2 select flag
POS 31 position
TIME 24 delay window for stacker select
BUF[0:79] 8 reader buffer
CDP ERR 1 error indicator
S4 1 stacker 4 select flag
S8 1 stacker 8 select flag
STKR POS0 31 position, normal reader stack
POS1 31 position, reader stacker 1
POS2 31 position, shared stacker 2/8
POS4 31 position, punch stacker 4
Error handling is as follows:
device error processed as
reader end of file if SSA set, set LAST indicator
on next Read, report error and stop
reader,punch not attached report error and stop
OS I/O error print error message
if IOCHK set, report error and stop
otherwise, set ERR indicator
stacker not attached ignored
OS I/O error print error message
if IOCHK set, report error and stop
2.3 1403 Line Printer (LPT)
The IBM 1403 line printer (LPT) writes its data, converted to ASCII, to
a disk file. The line printer supports three different print character
sets or "chains":
SET LPT PCF full 64 character chain
SET LPT PCA 48 character business chain
SET LPT PCH 48 character FORTRAN chain
In addition, the line printer can be programmed with a carriage control
tape. The LOAD command loads a new carriage control tape:
LOAD <file> load carriage control tape file
The format of a carriage control tape consists of multiple lines. Each
line contains an optional repeat count, enclosed in parentheses, optionally
followed by a series of column numbers separated by commas. Column numbers
must be between 1 and 12; a column number of zero denotes top of form. The
following are all legal carriage control specifications:
<blank line> no punch
(5) 5 lines with no punches
1,5,7,8 columns 1, 5, 7, 8 punched
(10)2 10 lines with column 2 punched
1,0 column 1 punched; top of form
The default form is 66 lines long, with column 1 and the top of form mark
on line 1, and the rest blank.
The line printer registers are:
name size comments
LINES 8 number of newlines after next print
LFLAG 1 carriage control flag (1 = skip, 0 = space)
CCTP 8 carriage control tape pointer
CCTL 8 carriage control tape length (read only)
ERR 1 error indicator
POS 31 position
CCT[0:131] 32 carriage control tape array
Error handling is as follows:
error processed as
not attached report error and stop
OS I/O error print error message
if IOCHK set, report error and stop
otherwise, set ERR indicator
2.4 1407 Inquiry Terminal (INQ)
The IBM 1407 inquiry terminal (INQ) is a half-duplex console. It polls
the console keyboard periodically for inquiry requests. The inquiry
terminal registers are:
name size comments
INQC 7 inquiry request character (initially ESC)
INR 1 inquiry request indicator
INC 1 inquiry cleared indicator
TIME 24 polling interval
When the 1401 CPU requests input from the keyboard, the message [Enter]
is printed out, followed by a new line. The CPU hangs waiting for input
until either the return/enter key is pressed, or the inquiry request
character is typed in. The latter cancels the type-in and sets INC.
The inquiry terminal has no errors.
2.5 729 Magnetic Tape (MT)
The magnetic tape controller supports six drives, numbered 1 through 6.
Magnetic tape options include the ability to make units write enabled or
or write locked.
SET MTn LOCKED set unit n write locked
SET MTn ENABLED set unit n write enabled
Units can also be REMOVEd or ADDed to the configuration. The magnetic
tape simulator supports the BOOT command. BOOT MT reads the first
record off tape, starting at location 1, and then branches to it.
The magnetic tape controller implements these registers:
name size comments
END 1 end of file indicator
ERR 1 error indicator
PAR 1 parity error indicator
POS1..6 31 position, drives 1..6
Error handling is as follows:
error processed as
not attached report error and stop
end of file (read or space) end of physical tape
(write) ignored
OS I/O error print error message
if IOCHK set, report error and stop
otherwise, set ERR indicator
2.6 Symbolic Display and Input
The IBM 1401 simulator implements symbolic display and input. Display is
controlled by command line switches:
-c display as single character
(BCD for CPU and MT, ASCII for others)
-s display as wordmark terminated BCD string
(CPU only)
-m display instruction mnemonics
(CPU only)
In a CPU character display, word marks are denoted by ~.
Input parsing is controlled by the first character typed in or by command
line switches:
' or " or -c or -s characters (BCD for CPU and MT, ASCII
for others)
alphabetic instruction mnemonic
numeric octal number
Instruction input is free format, with spaces separating fields. There
are six instruction formats: 1, 2, 4, 5, 7, and 8 characters:
1 character opcode
2 character opcode 'modifier
4 character opcode address
5 character opcode address 'modifier
7 character opcode address address
8 character opcode address address 'modifier
Addresses are always decimal, except for special I/O addresses in the A
field, which may be specified as %xy, where x denotes the device and y
the unit number.
For the CPU, string input may encompass multiple characters. A word mark
is denoted by ~ and must precede the character to be marked. All other
devices can only accept single character input, without word marks.
2.7 Character Sets
The IBM 1401 used a 6b character code called BCD (binary coded decimal).
Some of the characters have no equivalent in ASCII and require different
representations:
BCD ASCII IBM 1401 print
code representation character chains
00 space
01 1
02 2
03 3
04 4
05 5
06 6
07 7
10 8
11 9
12 0
13 # = in H chain
14 @ ' in H chain
15 : blank in A, H chains
16 > blank in A, H chains
17 ( tape mark blank in A, H chains
20 ^ alternate blank blank in A, H chains
21 /
22 S
23 T
24 U
25 V
26 W
27 X
30 Y
31 Z
32 ' record mark
33 ,
34 % ( in H chain
35 = word mark blank in A, H chains
36 \ blank in A, H chains
37 + blank in A, H chains
40 -
41 J
42 K
43 L
44 M
45 N
46 O
47 P
50 Q
51 R
52 !
53 $
54 *
55 ] blank in A, H chains
56 ; blank in A, H chains
57 _ delta blank in A, H chains
60 &
61 A
62 B
63 C
64 D
65 E
66 F
67 G
70 H
71 I
72 ?
73 .
74 ) lozenge
75 [ blank in A, H chains
76 < blank in A, H chains
77 " group mark blank in A, H chains

150
I1401/i1401_iq.c Normal file
View File

@@ -0,0 +1,150 @@
/* i1401_iq.c: IBM 1407 inquiry terminal
Copyright (c) 1993-2001, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
inq 1407 inquiry terminal
07-Sep-01 RMS Moved function prototypes
14-Apr-99 RMS Changed t_addr to unsigned
*/
#include "i1401_defs.h"
#include <ctype.h>
extern volatile int32 stop_cpu;
extern uint8 M[];
extern int32 BS, iochk, ind[64];
extern char ascii_to_bcd[128], bcd_to_ascii[64];
extern UNIT cpu_unit;
int32 inq_char = 033; /* request inq */
t_stat inq_svc (UNIT *uptr);
t_stat inq_reset (DEVICE *dptr);
void puts_tty (char *cptr);
/* INQ data structures
inq_dev INQ device descriptor
inq_unit INQ unit descriptor
inq_reg INQ register list
*/
UNIT inq_unit = { UDATA (&inq_svc, 0, 0), KBD_POLL_WAIT };
REG inq_reg[] = {
{ ORDATA (INQC, inq_char, 7) },
{ FLDATA (INR, ind[IN_INR], 0) },
{ FLDATA (INC, ind[IN_INC], 0) },
{ DRDATA (TIME, inq_unit.wait, 24), REG_NZ + PV_LEFT },
{ NULL } };
DEVICE inq_dev = {
"INQ", &inq_unit, inq_reg, NULL,
1, 10, 31, 1, 8, 7,
NULL, NULL, &inq_reset,
NULL, NULL, NULL };
/* Terminal I/O
Modifiers have not been checked; legal modifiers are R and W
*/
t_stat inq_io (int32 flag, int32 mod)
{
int32 i, t, wm_seen = 0;
ind[IN_INC] = 0; /* clear inq clear */
switch (mod) { /* case on mod */
case BCD_R: /* input */
/* if (ind[IN_INR] == 0) return SCPE_OK; /* return if no req */
ind[IN_INR] = 0; /* clear req */
puts_tty ("[Enter]\r\n"); /* prompt */
for (i = 0; M[BS] != (BCD_GRPMRK + WM); i++) { /* until GM + WM */
while ((t = sim_poll_kbd ()) == SCPE_OK)
if (stop_cpu) return SCPE_STOP; /* interrupt? */
if (t < SCPE_KFLAG) return t; /* if not char, err */
t = t & 0177;
if ((t == '\r') || (t == '\n')) break;
if (t == inq_char) { /* cancel? */
ind[IN_INC] = 1; /* set indicator */
puts_tty ("\r\n[Canceled]\r\n");
return SCPE_OK; }
if (i && ((i % INQ_WIDTH) == 0)) puts_tty ("\r\n");
sim_putchar (t); /* echo */
if (flag == MD_WM) { /* word mark mode? */
if ((t == '~') && (wm_seen == 0)) wm_seen = WM;
else { M[BS] = wm_seen | ascii_to_bcd[t];
wm_seen = 0; } }
else M[BS] = (M[BS] & WM) | ascii_to_bcd[t];
if (!wm_seen) BS++;
if (ADDR_ERR (BS)) {
BS = BA | (BS % MAXMEMSIZE);
return STOP_NXM; } }
puts_tty ("\r\n");
M[BS++] = BCD_GRPMRK + WM;
return SCPE_OK;
case BCD_W: /* output */
for (i = 0; (t = M[BS++]) != (BCD_GRPMRK + WM); i++) {
if ((flag == MD_WM) && (t & WM)) {
if (i && ((i % INQ_WIDTH) == 0)) puts_tty ("\r\n");
sim_putchar ('~'); }
if (i && ((i % INQ_WIDTH) == 0)) puts_tty ("\r\n");
sim_putchar (bcd_to_ascii[t & CHAR]);
if (ADDR_ERR (BS)) {
BS = BA | (BS % MAXMEMSIZE);
return STOP_NXM; } }
puts_tty ("\r\n");
return SCPE_OK;
default:
return STOP_INVM; } /* invalid mod */
}
/* Unit service - polls for WRU or inquiry request */
t_stat inq_svc (UNIT *uptr)
{
int32 temp;
sim_activate (&inq_unit, inq_unit.wait); /* continue poll */
if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp; /* no char or error? */
if ((temp & 0177) == inq_char) ind[IN_INR] = 1; /* set indicator */
return SCPE_OK;
}
/* Output multiple characters */
void puts_tty (char *cptr)
{
if (cptr == NULL) return;
while (*cptr != 0) sim_putchar (*cptr++);
return;
}
/* Reset routine */
t_stat inq_reset (DEVICE *dptr)
{
ind[IN_INR] = ind[IN_INC] = 0; /* clear indicators */
sim_activate (&inq_unit, inq_unit.wait); /* activate poll */
return SCPE_OK;
}

228
I1401/i1401_lp.c Normal file
View File

@@ -0,0 +1,228 @@
/* i1401_lp.c: IBM 1403 line printer simulator
Copyright (c) 1993-2001, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
lpt 1403 line printer
13-Apr-01 RMS Revised for register arrays
*/
#include "i1401_defs.h"
extern uint8 M[];
extern char bcd_to_ascii[64];
extern int32 iochk, ind[64];
int32 cct[CCT_LNT] = { 03 };
int32 cctlnt = 66, cctptr = 0, lines = 0, lflag = 0;
t_stat lpt_reset (DEVICE *dptr);
t_stat lpt_attach (UNIT *uptr, char *cptr);
t_stat space (int32 lines, int32 lflag);
char bcd_to_pca[64] = {
' ', '1', '2', '3', '4', '5', '6', '7',
'8', '9', '0', '#', '@', ' ', ' ', ' ',
' ', '/', 'S', 'T', 'U', 'V', 'W', 'X',
'Y', 'Z', ' ', ',', '%', ' ', ' ', ' ',
'-', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
'Q', 'R', '-', '$', '*', ' ', ' ', ' ',
'&', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', '&', '.', ')', ' ', ' ', ' ' };
char bcd_to_pch[64] = {
' ', '1', '2', '3', '4', '5', '6', '7',
'8', '9', '0', '=', '\'', ' ', ' ', ' ',
' ', '/', 'S', 'T', 'U', 'V', 'W', 'X',
'Y', 'Z', ' ', ',', '(', ' ', ' ', ' ',
'-', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
'Q', 'R', '-', '$', '*', ' ', ' ', ' ',
'&', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', '&', '.', ')', ' ', ' ', ' ' };
char *pch_table[4] = {
bcd_to_ascii, bcd_to_pca, bcd_to_pch, bcd_to_ascii };
#define UNIT_V_PCHAIN (UNIT_V_UF + 0)
#define UNIT_M_PCHAIN 03
#define M_PCF 00 /* full */
#define M_PCA 01 /* business */
#define M_PCH 02 /* Fortran */
#define UNIT_PCHAIN (UNIT_M_PCHAIN << UNIT_V_PCHAIN)
#define PCF (M_PCF << UNIT_V_PCHAIN)
#define PCA (M_PCA << UNIT_V_PCHAIN)
#define PCH (M_PCH << UNIT_V_PCHAIN)
#define GET_PCHAIN(x) (((x) >> UNIT_V_PCHAIN) & UNIT_M_PCHAIN)
#define CHP(ch,val) ((val) & (1 << (ch)))
/* LPT data structures
lpt_dev LPT device descriptor
lpt_unit LPT unit descriptor
lpt_reg LPT register list
*/
UNIT lpt_unit = {
UDATA (NULL, UNIT_SEQ+UNIT_ATTABLE, 0) };
REG lpt_reg[] = {
{ FLDATA (ERR, ind[IN_LPT], 0) },
{ DRDATA (POS, lpt_unit.pos, 31), PV_LEFT },
{ BRDATA (CCT, cct, 8, 32, CCT_LNT) },
{ DRDATA (LINES, lines, 8), PV_LEFT },
{ DRDATA (CCTP, cctptr, 8), PV_LEFT },
{ DRDATA (CCTL, cctlnt, 8), REG_RO + PV_LEFT },
{ GRDATA (CHAIN, lpt_unit.flags, 10, 2, UNIT_V_PCHAIN), REG_HRO },
{ NULL } };
MTAB lpt_mod[] = {
{ UNIT_PCHAIN, PCF, "F chain", "PCF", NULL },
{ UNIT_PCHAIN, PCA, "A chain", "PCA", NULL },
{ UNIT_PCHAIN, PCH, "H chain", "PCH", NULL },
{ 0 } };
DEVICE lpt_dev = {
"LPT", &lpt_unit, lpt_reg, lpt_mod,
1, 10, 31, 1, 8, 7,
NULL, NULL, &lpt_reset,
NULL, &lpt_attach, NULL };
/* Print routine
Modifiers have been checked by the caller
SQUARE = word mark mode
S = suppress automatic newline
*/
t_stat write_line (int32 ilnt, int32 mod)
{
int32 i, t, wm, sup;
char *pch;
static char lbuf[LPT_WIDTH + 1]; /* + null */
if ((lpt_unit.flags & UNIT_ATT) == 0) return SCPE_UNATT; /* attached? */
wm = ((ilnt == 2) || (ilnt == 5)) && (mod == BCD_SQUARE);
sup = ((ilnt == 2) || (ilnt == 5)) && (mod == BCD_S);
ind[IN_LPT] = 0; /* clear error */
pch = pch_table[GET_PCHAIN (lpt_unit.flags)]; /* get print chain */
for (i = 0; i < LPT_WIDTH; i++) { /* convert print buf */
t = M[LPT_BUF + i];
if (wm) lbuf[i] = (t & WM)? '1': ' '; /* wmarks -> 1 or sp */
else lbuf[i] = pch[t & CHAR]; } /* normal */
M[LPT_BUF + 1] = 0; /* trailing null */
for (i = LPT_WIDTH - 1; (i >= 0) && (lbuf[i] == ' '); i--) lbuf[i] = 0;
fputs (lbuf, lpt_unit.fileref); /* write line */
if (lines) space (lines, lflag); /* cc action? do it */
else if (sup == 0) space (1, FALSE); /* default? 1 line */
else { fputc ('\r', lpt_unit.fileref); /* sup -> overprint */
lpt_unit.pos = ftell (lpt_unit.fileref); } /* update position */
lines = lflag = 0; /* clear cc action */
if (ferror (lpt_unit.fileref)) { /* error? */
perror ("Line printer I/O error");
clearerr (lpt_unit.fileref);
if (iochk) return SCPE_IOERR;
ind[IN_LPT] = 1; }
return SCPE_OK;
}
/* Carriage control routine
The modifier has not been checked, its format is
<5:4> = 00, skip to channel now
= 01, space lines after
= 10, space lines now
= 11, skip to channel after
<3:0> = number of lines or channel number
*/
t_stat carriage_control (int32 mod)
{
int32 i, action;
action = (mod & ZONE) >> V_ZONE; /* get mod type */
mod = mod & DIGIT; /* isolate value */
switch (action) {
case 0: /* to channel now */
if ((mod == 0) || (mod > 12) || CHP (mod, cct[cctptr])) return SCPE_OK;
for (i = 1; i < cctlnt + 1; i++) { /* sweep thru cct */
if (CHP (mod, cct[(cctptr + i) % cctlnt]))
return space (i, TRUE); }
return STOP_CCT; /* runaway channel */
case 1: /* space after */
if (mod <= 3) {
lines = mod; /* save # lines */
lflag = FALSE; /* flag spacing */
ind[IN_CC9] = ind[IN_CC12] = 0; }
return SCPE_OK;
case 2: /* space now */
if (mod <= 3) return space (mod, FALSE);
return SCPE_OK;
case 3: /* to channel after */
if ((mod == 0) || (mod > 12)) return SCPE_OK; /* check channel */
ind[IN_CC9] = ind[IN_CC12] = 0;
for (i = 1; i < cctlnt + 1; i++) { /* sweep thru cct */
if (CHP (mod, cct[(cctptr + i) % cctlnt])) {
lines = i; /* save # lines */
lflag = TRUE; /* flag skipping */
return SCPE_OK; } }
return STOP_CCT; } /* runaway channel */
return SCPE_OK;
}
/* Space routine - space or skip n lines
Inputs:
count = number of lines to space or skip
sflag = skip (TRUE) or space (FALSE)
*/
t_stat space (int32 count, int32 sflag)
{
int32 i;
if ((lpt_unit.flags & UNIT_ATT) == 0) return SCPE_UNATT;
cctptr = (cctptr + count) % cctlnt; /* adv cct, mod lnt */
if (sflag && CHP (0, cct[cctptr])) /* skip, top of form? */
fputs ("\n\f", lpt_unit.fileref); /* nl, ff */
else { for (i = 0; i < count; i++) fputc ('\n', lpt_unit.fileref); }
lpt_unit.pos = ftell (lpt_unit.fileref); /* update position */
ind[IN_CC9] = CHP (9, cct[cctptr]) != 0; /* set indicators */
ind[IN_CC12] = CHP (12, cct[cctptr]) != 0;
return SCPE_OK;
}
/* Reset routine */
t_stat lpt_reset (DEVICE *dptr)
{
cctptr = 0; /* clear cct ptr */
lines = lflag = 0; /* no cc action */
ind[IN_LPT] = 0;
return SCPE_OK;
}
/* Attach routine */
t_stat lpt_attach (UNIT *uptr, char *cptr)
{
cctptr = 0; /* clear cct ptr */
lines = 0; /* no cc action */
ind[IN_LPT] = 0;
return attach_unit (uptr, cptr);
}

303
I1401/i1401_mt.c Normal file
View File

@@ -0,0 +1,303 @@
/* i1401_mt.c: IBM 1401 magnetic tape simulator
Copyright (c) 1993-2001, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
mt 7-track magtape
29-Nov-01 RMS Added read only unit support
18-Apr-01 RMS Changed to rewind tape before boot
07-Dec-00 RMS Widened display width from 6 to 8 bits to see record lnt
CEO Added tape bootstrap
14-Apr-99 RMS Changed t_addr to unsigned
04-Oct-98 RMS V2.4 magtape format
Magnetic tapes are represented as a series of variable 16b records
of the form:
32b byte count
byte 0
byte 1
:
byte n-2
byte n-1
32b byte count
If the byte count is odd, the record is padded with an extra byte
of junk. File marks are represented by a byte count of 0.
*/
#include "i1401_defs.h"
#define MT_NUMDR 7 /* #drives */
#define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */
#define UNIT_WLK (1 << UNIT_V_WLK)
#define UNIT_W_UF 2 /* #save flags */
#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */
extern uint8 M[]; /* memory */
extern int32 ind[64];
extern int32 BS, iochk;
extern UNIT cpu_unit;
unsigned int8 dbuf[MAXMEMSIZE * 2]; /* tape buffer */
t_stat mt_reset (DEVICE *dptr);
t_stat mt_boot (int32 unitno);
UNIT *get_unit (int32 unit);
/* MT data structures
mt_dev MT device descriptor
mt_unit MT unit list
mt_reg MT register list
mt_mod MT modifier list
*/
UNIT mt_unit[] = {
{ UDATA (NULL, UNIT_DIS, 0) }, /* doesn't exist */
{ UDATA (NULL, UNIT_DISABLE + UNIT_ATTABLE +
UNIT_ROABLE + UNIT_BCD, 0) },
{ UDATA (NULL, UNIT_DISABLE + UNIT_ATTABLE +
UNIT_ROABLE + UNIT_BCD, 0) },
{ UDATA (NULL, UNIT_DISABLE + UNIT_ATTABLE +
UNIT_ROABLE + UNIT_BCD, 0) },
{ UDATA (NULL, UNIT_DISABLE + UNIT_ATTABLE +
UNIT_ROABLE + UNIT_BCD, 0) },
{ UDATA (NULL, UNIT_DISABLE + UNIT_ATTABLE +
UNIT_ROABLE + UNIT_BCD, 0) },
{ UDATA (NULL, UNIT_DISABLE + UNIT_ATTABLE +
UNIT_ROABLE + UNIT_BCD, 0) } };
REG mt_reg[] = {
{ FLDATA (END, ind[IN_END], 0) },
{ FLDATA (ERR, ind[IN_TAP], 0) },
{ FLDATA (PAR, ind[IN_PAR], 0) },
{ DRDATA (POS1, mt_unit[1].pos, 31), PV_LEFT + REG_RO },
{ DRDATA (POS2, mt_unit[2].pos, 31), PV_LEFT + REG_RO },
{ DRDATA (POS3, mt_unit[3].pos, 31), PV_LEFT + REG_RO },
{ DRDATA (POS4, mt_unit[4].pos, 31), PV_LEFT + REG_RO },
{ DRDATA (POS5, mt_unit[5].pos, 31), PV_LEFT + REG_RO },
{ DRDATA (POS6, mt_unit[6].pos, 31), PV_LEFT + REG_RO },
{ GRDATA (FLG1, mt_unit[1].flags, 8, UNIT_W_UF, UNIT_V_UF - 1),
REG_HRO },
{ GRDATA (FLG2, mt_unit[2].flags, 8, UNIT_W_UF, UNIT_V_UF - 1),
REG_HRO },
{ GRDATA (FLG3, mt_unit[3].flags, 8, UNIT_W_UF, UNIT_V_UF - 1),
REG_HRO },
{ GRDATA (FLG4, mt_unit[4].flags, 8, UNIT_W_UF, UNIT_V_UF - 1),
REG_HRO },
{ GRDATA (FLG5, mt_unit[5].flags, 8, UNIT_W_UF, UNIT_V_UF - 1),
REG_HRO },
{ GRDATA (FLG6, mt_unit[6].flags, 8, UNIT_W_UF, UNIT_V_UF - 1),
REG_HRO },
{ NULL } };
MTAB mt_mod[] = {
{ UNIT_WLK, 0, "write enabled", "ENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ 0 } };
DEVICE mt_dev = {
"MT", mt_unit, mt_reg, mt_mod,
MT_NUMDR, 10, 31, 1, 8, 8,
NULL, NULL, &mt_reset,
&mt_boot, NULL, NULL };
/* Function routine
Inputs:
unit = unit character
mod = modifier character
Outputs:
status = status
*/
t_stat mt_func (int32 unit, int32 mod)
{
int32 err;
t_mtrlnt tbc;
UNIT *uptr;
static t_mtrlnt bceof = { 0 };
if ((uptr = get_unit (unit)) == NULL) return STOP_INVMTU; /* valid unit? */
if ((uptr -> flags & UNIT_ATT) == 0) return SCPE_UNATT; /* attached? */
switch (mod) { /* case on modifier */
case BCD_B: /* backspace */
ind[IN_END] = 0; /* clear end of reel */
if (uptr -> pos == 0) return SCPE_OK; /* at bot? */
fseek (uptr -> fileref, uptr -> pos - sizeof (t_mtrlnt),
SEEK_SET);
fxread (&tbc, sizeof (t_mtrlnt), 1, uptr -> fileref);
if ((err = ferror (uptr -> fileref)) ||
(feof (uptr -> fileref))) break;
if (tbc == 0) /* file mark? */
uptr -> pos = uptr -> pos - sizeof (t_mtrlnt);
else uptr -> pos = uptr -> pos - ((MTRL (tbc) + 1) & ~1) -
(2 * sizeof (t_mtrlnt));
break; /* end case */
case BCD_E: /* erase = nop */
if (uptr -> flags & UNIT_WPRT) return STOP_MTL;
return SCPE_OK;
case BCD_M: /* write tapemark */
if (uptr -> flags & UNIT_WPRT) return STOP_MTL;
fseek (uptr -> fileref, uptr -> pos, SEEK_SET);
fxwrite (&bceof, sizeof (t_mtrlnt), 1, uptr -> fileref);
err = ferror (uptr -> fileref);
uptr -> pos = uptr -> pos + sizeof (t_mtrlnt);
break;
case BCD_R: /* rewind */
uptr -> pos = 0; /* update position */
return SCPE_OK;
case BCD_U: /* unload */
uptr -> pos = 0; /* update position */
return detach_unit (uptr); /* detach */
default:
return STOP_INVM; }
if (err != 0) { /* I/O error */
perror ("MT I/O error");
clearerr (uptr -> fileref);
if (iochk) return SCPE_IOERR;
ind[IN_TAP] = 1; }
return SCPE_OK;
}
/* Read and write routines
Inputs:
unit = unit character
flag = normal, word mark, or binary mode
mod = modifier character
Outputs:
status = status
*/
t_stat mt_io (int32 unit, int32 flag, int32 mod)
{
int32 err, i, t, wm_seen;
t_mtrlnt tbc;
UNIT *uptr;
if ((uptr = get_unit (unit)) == NULL) return STOP_INVMTU; /* valid unit? */
if ((uptr -> flags & UNIT_ATT) == 0) return SCPE_UNATT; /* attached? */
switch (mod) {
case BCD_R: /* read */
ind[IN_TAP] = ind[IN_END] = 0; /* clear error */
wm_seen = 0; /* no word mk seen */
fseek (uptr -> fileref, uptr -> pos, SEEK_SET);
fxread (&tbc, sizeof (t_mtrlnt), 1, uptr -> fileref);
if ((err = ferror (uptr -> fileref)) || (feof (uptr -> fileref))) {
ind[IN_END] = 1; /* err or eof? */
break; }
if (tbc == 0) { /* tape mark? */
ind[IN_END] = 1; /* set end mark */
uptr -> pos = uptr -> pos + sizeof (t_mtrlnt);
break; }
tbc = MTRL (tbc); /* ignore error flag */
i = fxread (dbuf, sizeof (int8), tbc, uptr -> fileref);
for ( ; i < tbc; i++) dbuf[i] = 0; /* fill with 0's */
err = ferror (uptr -> fileref);
uptr -> pos = uptr -> pos + ((tbc + 1) & ~1) +
(2 * sizeof (t_mtrlnt));
for (i = 0; (i < tbc) && (M[BS] != (BCD_GRPMRK + WM)); i++) {
t = dbuf[i]; /* get char */
if ((flag != MD_BIN) && (t == BCD_ALT)) t = BCD_BLANK;
if (flag == MD_WM) { /* word mk mode? */
if ((t == BCD_WM) && (wm_seen == 0)) wm_seen = WM;
else { M[BS] = wm_seen | (t & CHAR);
wm_seen = 0; } }
else M[BS] = (M[BS] & WM) | (t & CHAR);
if (!wm_seen) BS++;
if (ADDR_ERR (BS)) {
BS = BA | (BS % MAXMEMSIZE);
return STOP_NXM; } }
M[BS++] = BCD_GRPMRK + WM; /* end of record */
break;
case BCD_W:
if (uptr -> flags & UNIT_WPRT) return STOP_MTL; /* locked? */
if (M[BS] == (BCD_GRPMRK + WM)) return STOP_MTZ; /* eor? */
ind[IN_TAP] = ind[IN_END] = 0; /* clear error */
for (tbc = 0; (t = M[BS++]) != (BCD_GRPMRK + WM); ) {
if ((t & WM) && (flag == MD_WM)) dbuf[tbc++] = BCD_WM;
if (((t & CHAR) == BCD_BLANK) && (flag != MD_BIN))
dbuf[tbc++] = BCD_ALT;
else dbuf[tbc++] = t & CHAR;
if (ADDR_ERR (BS)) {
BS = BA | (BS % MAXMEMSIZE);
return STOP_NXM; } }
fseek (uptr -> fileref, uptr -> pos, SEEK_SET);
fxwrite (&tbc, sizeof (t_mtrlnt), 1, uptr -> fileref);
fxwrite (dbuf, sizeof (int8), (tbc + 1) & ~1, uptr -> fileref);
fxwrite (&tbc, sizeof (t_mtrlnt), 1, uptr -> fileref);
err = ferror (uptr -> fileref);
uptr -> pos = uptr -> pos + ((tbc + 1) & ~1) +
(2 * sizeof (t_mtrlnt));
break;
default:
return STOP_INVM; }
if (err != 0) { /* I/O error */
perror ("MT I/O error");
clearerr (uptr -> fileref);
if (iochk) return SCPE_IOERR;
ind[IN_TAP] = 1; } /* flag error */
return SCPE_OK;
}
/* Get unit pointer from unit number */
UNIT *get_unit (int32 unit)
{
if ((unit <= 0) || (unit >= MT_NUMDR)) return NULL;
else return mt_dev.units + unit;
}
/* Reset routine */
t_stat mt_reset (DEVICE *dptr)
{
ind[IN_END] = ind[IN_PAR] = ind[IN_TAP] = 0; /* clear indicators */
return SCPE_OK;
}
/* Bootstrap routine */
#define BOOT_START 3980
#define BOOT_LEN (sizeof (boot_rom) / sizeof (unsigned char))
static const unsigned char boot_rom[] = {
OP_LCA + WM, BCD_PERCNT, BCD_U, BCD_ONE,
BCD_ZERO, BCD_ZERO, BCD_ONE, BCD_R, /* LDA %U1 001 R */
OP_B + WM, BCD_ZERO, BCD_ZERO, BCD_ONE, /* B 001 */
OP_H + WM }; /* HALT */
t_stat mt_boot (int32 unitno)
{
int32 i;
extern int32 saved_IS;
mt_unit[unitno].pos = 0;
for (i = 0; i < BOOT_LEN; i++) M[BOOT_START + i] = boot_rom[i];
M[BOOT_START + 3] = unitno & 07;
saved_IS = BOOT_START;
return SCPE_OK;
}

311
I1401/i1401_sys.c Normal file
View File

@@ -0,0 +1,311 @@
/* i1401_sys.c: IBM 1401 simulator interface
Copyright (c) 1993-2001, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Robert M Supnik shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
17-Sep-01 RMS Removed multiconsole support
13-Jul-01 RMS Fixed bug in symbolic output (found by Peter Schorn)
27-May-01 RMS Added multiconsole support
14-Mar-01 RMS Revised load/dump interface (again)
30-Oct-00 RMS Added support for examine to file
27-Oct-98 RMS V2.4 load interface
*/
#include "i1401_defs.h"
#include <ctype.h>
#define LINE_LNT 80
extern DEVICE cpu_dev, inq_dev, lpt_dev;
extern DEVICE cdr_dev, cdp_dev, stack_dev;
extern DEVICE mt_dev;
extern UNIT cpu_unit;
extern REG cpu_reg[];
extern uint8 M[];
extern char bcd_to_ascii[64], ascii_to_bcd[128];
extern char *get_glyph (char *cptr, char *gbuf, char term);
extern int32 store_addr_h (int32 addr);
extern int32 store_addr_t (int32 addr);
extern int32 store_addr_u (int32 addr);
/* SCP data structures and interface routines
sim_name simulator name string
sim_PC pointer to saved PC register descriptor
sim_emax maximum number of words for examine/deposit
sim_devices array of pointers to simulated devices
sim_stop_messages array of pointers to stop messages
sim_load binary loader
*/
char sim_name[] = "IBM 1401";
REG *sim_PC = &cpu_reg[0];
int32 sim_emax = LINE_LNT;
DEVICE *sim_devices[] = { &cpu_dev, &inq_dev,
&cdr_dev, &cdp_dev, &stack_dev, &lpt_dev,
&mt_dev, NULL };
const char *sim_stop_messages[] = {
"Unknown error",
"Unimplemented instruction",
"Non-existent memory",
"Non-existent device",
"No WM at instruction start",
"Invalid A address",
"Invalid B address",
"Invalid instruction length",
"Invalid modifer",
"Invalid branch address",
"Breakpoint",
"HALT instruction",
"Invalid MT unit number",
"Invalid MT record length",
"Write to locked MT unit",
"Skip to unpunched CCT channel",
"Card reader empty",
"Address register wrap",
"MCE data field too short",
"MCE control field too short",
"MCE EPE hanging $",
"I/O check" };
/* Binary loader -- load carriage control tape
A carriage control tape consists of entries of the form
(repeat count) column number,column number,column number,...
The CCT entries are stored in cct[0:lnt-1], cctlnt contains the
number of entries
*/
t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
int32 col, rpt, ptr, mask, cctbuf[CCT_LNT];
t_stat r;
extern int32 cctlnt, cctptr, cct[CCT_LNT];
char cbuf[CBUFSIZE], gbuf[CBUFSIZE];
if ((*cptr != 0) || (flag != 0)) return SCPE_ARG;
ptr = 0;
for ( ; (cptr = fgets (cbuf, CBUFSIZE, fileref)) != NULL; ) { /* until eof */
mask = 0;
if (*cptr == '(') { /* repeat count? */
cptr = get_glyph (cptr + 1, gbuf, ')'); /* get 1st field */
rpt = get_uint (gbuf, 10, CCT_LNT, &r); /* repeat count */
if (r != SCPE_OK) return SCPE_FMT; }
else rpt = 1;
while (*cptr != 0) { /* get col no's */
cptr = get_glyph (cptr, gbuf, ','); /* get next field */
col = get_uint (gbuf, 10, 12, &r); /* column number */
if (r != SCPE_OK) return SCPE_FMT;
mask = mask | (1 << col); } /* set bit */
for ( ; rpt > 0; rpt--) { /* store vals */
if (ptr >= CCT_LNT) return SCPE_FMT;
cctbuf[ptr++] = mask; } }
if (ptr == 0) return SCPE_FMT;
cctlnt = ptr;
cctptr = 0;
for (rpt = 0; rpt < cctlnt; rpt++) cct[rpt] = cctbuf[rpt];
return SCPE_OK;
}
/* Symbol table */
const char *opcode[64] = {
NULL, "R", "W", "WR", "P", "RP", "WP", "WRP",
"RF", "WF", NULL, "MA", "MUL", NULL, NULL, NULL,
NULL, "CS", "S", NULL, "MTF", "BWZ", "BBE", NULL,
"MZ", "MSZ", NULL, "SWM", "DIV", NULL, NULL, NULL,
NULL, NULL, "SS", "LCA", "MCW", "NOP", NULL, "MCM",
"SAR", NULL, "ZS", NULL, NULL, NULL, NULL, NULL,
NULL, "A", "B", "C", "MN", "MCE", "CC", NULL,
"SBR", NULL, "ZA", "H", "CWM", NULL, NULL, NULL };
/* Print an address from three characters */
void fprint_addr (FILE *of, t_value *dig)
{
int32 addr, xa;
extern int32 hun_table[64], ten_table[64], one_table[64];
addr = hun_table[dig[0]] + ten_table[dig[1]] + one_table[dig[2]];
xa = (addr >> V_INDEX) & M_INDEX;
if (xa) fprintf (of, " %d,%d", addr & ADDRMASK, ((xa - (X1 >> V_INDEX)) / 5) + 1);
else if (addr >= MAXMEMSIZE) fprintf (of, " %d*", addr & ADDRMASK);
else fprintf (of, " %d", addr);
return;
}
/* Symbolic decode
Inputs:
*of = output stream
addr = current address
*val = values to decode
*uptr = pointer to unit
sw = switches
Outputs:
return = if >= 0, error code
if < 0, number of extra words retired
*/
#define FMTASC(x) ((x) < 040)? "<%03o>": "%c", (x)
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw)
{
int32 op, flags, ilnt, i, t;
extern int32 op_table[64], len_table[9];
if (sw & SWMASK ('C')) { /* character? */
t = val[0];
if (uptr -> flags & UNIT_BCD)
fprintf (of, (t & WM)? "~%c": "%c", bcd_to_ascii[t & CHAR]);
else fprintf (of, FMTASC (t & 0177));
return SCPE_OK; }
if ((uptr != NULL) && (uptr != &cpu_unit)) return SCPE_ARG; /* CPU? */
if (sw & SWMASK ('S')) { /* string? */
i = 0;
do { t = val[i++];
fprintf (of, (t & WM)? "~%c": "%c", bcd_to_ascii[t & CHAR]); }
while ((i < LINE_LNT) && ((val[i] & WM) == 0));
return -(i - 1); }
if ((sw & SWMASK ('M')) == 0) return SCPE_ARG;
if ((val[0] & WM) == 0) return STOP_NOWM; /* WM under op? */
op = val[0]& CHAR; /* isolate op */
flags = op_table[op]; /* get flags */
for (ilnt = 1; ilnt < sim_emax; ilnt++) if (val[ilnt] & WM) break;
if (flags & HNOP) ilnt = 1; /* halt, nop? */
else if ((flags & NOWM) && (ilnt > 7)) ilnt = 7; /* cs, swm? */
else if ((op == OP_B) && (ilnt > 4) && (val[4] == BCD_BLANK)) ilnt = 4;
else if (ilnt > 8) ilnt = 8; /* cap length */
if ((flags & len_table[ilnt]) == 0) return STOP_INVL; /* legal length? */
fprintf (of, "%s",opcode[op]); /* print opcode */
if (ilnt > 2) { /* A address? */
if ((flags & IO) && (val[1] == BCD_PERCNT)) fprintf (of, " %%%c%c",
bcd_to_ascii[val[2]], bcd_to_ascii[val[3]]);
else fprint_addr (of, &val[1]); }
if (ilnt > 5) fprint_addr (of, &val[4]); /* B address? */
if ((ilnt == 2) || (ilnt == 5) || (ilnt == 8)) /* d character? */
fprintf (of, " '%c", bcd_to_ascii[val[ilnt - 1]]);
return -(ilnt - 1); /* return # chars */
}
/* get_addr - get address + index pair */
t_stat get_addr (char *cptr, t_value *val)
{
int32 addr, index;
t_stat r;
char gbuf[CBUFSIZE];
cptr = get_glyph (cptr, gbuf, ','); /* get address */
addr = get_uint (gbuf, 10, MAXMEMSIZE, &r);
if (r != SCPE_OK) return SCPE_ARG;
if (*cptr != 0) { /* more? */
cptr = get_glyph (cptr, gbuf, ' ');
index = get_uint (gbuf, 10, 3, &r);
if ((r != SCPE_OK) || (index == 0)) return SCPE_ARG; }
else index = 0;
if (*cptr != 0) return SCPE_ARG;
val[0] = store_addr_h (addr);
val[1] = store_addr_t (addr) | (index << V_ZONE);
val[2] = store_addr_u (addr);
return SCPE_OK;
}
/* get_io - get I/O address */
t_stat get_io (char *cptr, t_value *val)
{
if ((cptr[0] != '%') || (cptr[3] != 0) || !isalnum (cptr[1]) ||
!isalnum (cptr[2])) return SCPE_ARG;
val[0] = BCD_PERCNT;
val[1] = ascii_to_bcd[cptr[1]];
val[2] = ascii_to_bcd[cptr[2]];
return SCPE_OK;
}
/* Symbolic input
Inputs:
*cptr = pointer to input string
addr = current PC
*uptr = pointer to unit
*val = pointer to output values
sw = switches
Outputs:
status = > 0 error code
<= 0 -number of extra words
*/
t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
{
int32 i, op, ilnt, t, cflag, wm_seen;
extern int32 op_table[64], len_table[9];
char gbuf[CBUFSIZE];
cflag = (uptr == NULL) || (uptr == &cpu_unit);
while (isspace (*cptr)) cptr++; /* absorb spaces */
if ((sw & SWMASK ('C')) || (sw & SWMASK ('S')) || (*cptr == '~') ||
((*cptr == '\'') && cptr++) || ((*cptr == '"') && cptr++)) {
wm_seen = 0;
for (i = 0; (i < sim_emax) && (*cptr != 0); ) {
t = *cptr++; /* get character */
if (cflag && (wm_seen == 0) && (t == '~')) wm_seen = WM;
else if (uptr -> flags & UNIT_BCD) {
if (t < 040) return SCPE_ARG;
val[i++] = ascii_to_bcd[t] | wm_seen;
wm_seen = 0; }
else val[i++] = t; }
if ((i == 0) || wm_seen) return SCPE_ARG;
return -(i-1); }
if (cflag == 0) return SCPE_ARG; /* CPU only */
cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
for (op = 0; op < 64; op++) /* look it up */
if (opcode[op] && strcmp (gbuf, opcode[op]) == 0) break;
if (op >= 64) return SCPE_ARG; /* successful? */
val[0] = op | WM; /* store opcode */
cptr = get_glyph (cptr, gbuf, ' '); /* get addr or d */
if (((op_table[op] && IO) && (get_io (gbuf, &val[1]) == SCPE_OK)) ||
(get_addr (gbuf, &val[1]) == SCPE_OK)) {
cptr = get_glyph (cptr, gbuf, ' '); /* get addr or d */
if (get_addr (gbuf, &val[4]) == SCPE_OK) {
cptr = get_glyph (cptr, gbuf, ' '); /* get d */
ilnt = 7; } /* a and b addresses */
else ilnt = 4; } /* a address */
else ilnt = 1; /* no addresses */
if ((gbuf[0] == '\'') || (gbuf[0] == '"')) { /* d character? */
t = gbuf[1];
if ((gbuf[2] != 0) || (*cptr != 0) || (t < 040))
return SCPE_ARG; /* end and legal? */
val[ilnt] = ascii_to_bcd[t]; /* save D char */
ilnt = ilnt + 1; }
if ((op_table[op] & len_table[ilnt]) == 0) return STOP_INVL;
return -(ilnt - 1);
}