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Notes For V2.8
1. New Features
1.1 Directory and documentation
- Only common files (SCP and libraries) are in the top level
directory. Individual simulator files are in their individual
directories.
- simh_doc.txt has been split up. simh_doc.txt now documents
only SCP. The individual simulators are documented in separate
text files in their own directories.
- mingw_build.bat is a batch file for the MINGW/gcc environment
that will build all the simulators, assuming the root directory
structure is at c:\sim.
- Makefile is a UNIX make file for the gcc environment that will
build all the simulators, assuming the root directory is at
c:\sim.
1.2 SCP
- DO <file name> executes the SCP commands in the specified file.
- Replicated registers in unit structures can now be declared as
arrays for examine, modify, save, and restore. Most replicated
unit registers (for example, mag tape position registers) have
been changed to arrays.
- The ADD/REMOVE commands have been replaced by SET unit ONLINE
and SET unit OFFLINE, respectively.
- Register names that are unique within an entire simulator do
not have to be prefaced with the device name.
- The ATTACH command can attach files read only, either under
user option (-r), or because the attached file is ready only.
- The SET/SHOW capabilities have been extended. New forms include:
SET <dev> param{=value}{ param ...}
SET <unit> param{=value}{ param ...}
SHOW <dev> {param param ...}
SHOW <unit> {param param ...}
- Multiple breakpoints have been implemented. Breakpoints are
set/cleared/displayed by:
BREAK addr_list{[count]}
NOBREAK addr_list
SHOW BREAK addr_list
1.3 PDP-11 simulator
- Unibus map implemented, with 22b RP controller (URH70) or 18b
RP controller (URH11) (in debug).
- All DMA peripherals rewritten to use map.
- Many peripherals modified for source sharing with VAX.
- RQDX3 implemented.
- Bugs fixed in RK11 and RL11 write check.
1.4 PDP-10 simulator
- ITS 1-proceed implemented.
- Bugs fixed in ITS PC sampling and LPMR
1.5 18b PDP simulator
- Interrupts split out to multiple levels to allow easier
expansion.
1.5 IBM System 3 Simulator
- Written by Charles (Dutch) Owen.
1.6 VAX Simulator (in debug)
- Simulates MicroVAX 3800 (KA655) with 16MB-64MB memory, RQDX3,
RLV12, TSV11, DZV11, LPV11, PCV11.
- CDROM capability has been added to the RQDX3, to allow testing
with VMS hobbyist images.
1.7 SDS 940 Simulator (not tested)
- Simulates SDS 940, 16K-64K memory, fixed and moving head
disk, magtape, line printer, console.
1.8 Altair Z80
- Revised from Charles (Dutch) Owen's original by Peter Schorn.
- MITS 8080 with full Z80 simulation.
- 4K and 8K BASIC packages, Prolog package.
1.9 Interdata
The I4 simulator has been withdrawn for major rework. Look for
a complete 16b/32b Interdata simulator sometime next year.
2. Release Notes
2.1 SCP
SCP now allows replicated registers in unit structures to be
modelled as arrays. All replicated register declarations have
been replaced by register array declarations. As a result,
save files from prior revisions will generate errors after
restoring main memory.
2.2 PDP-11
The Unibus map code is in debug. The map was implemented primarily
to allow source sharing with the VAX, which requires a DMA map.
DMA devices work correctly with the Unibus map disabled.
The RQDX3 simulator has run a complete RSTS/E SYSGEN, with multiple
drives, and booted the completed system from scratch.
2.3 VAX
The VAX simulator will run the boot code up to the >>> prompt. It
can successfully process a SHOW DEVICE command. It runs the HCORE
instruction diagnostic. It can boot the hobbyist CD through SYSBOOT
and through the date/time dialog and restore the hobbyist CD, using
standalone backup. On the boot of the restored disk, it gets to the
date/time dialog, and then crashes.
2.4 SDS 940
The SDS 940 is untested, awaiting real code.
2.5 GCC Optimization
At -O2 and above, GCC does not correctly compile the simulators which
use setjmp-longjmp (PDP-11, PDP-10, VAX). A working hypothesis is
that optimized state maintained in registers is being used in the
setjmp processing routine. On the PDP-11 and PDP-10, all of this
state has been either made global, or volatile, to encourage GCC to
keep the state up to date in memory. The VAX is still vulnerable.
3. Work list
3.1 SCP
- Better ENABLE/DISABLE.
3.2 PDP-11 RQDX3
Software mapped mode, RCT read simulation, VMS debug.
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
654937fc88
commit
701f0fe028
776
PDP1/pdp1_cpu.c
Normal file
776
PDP1/pdp1_cpu.c
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@@ -0,0 +1,776 @@
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/* pdp1_cpu.c: PDP-1 CPU simulator
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Copyright (c) 1993-2001, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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cpu PDP-1 central processor
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07-Dec-01 RMS Revised to use breakpoint package
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30-Nov-01 RMS Added extended SET/SHOW support
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16-Dec-00 RMS Fixed bug in XCT address calculation
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14-Apr-99 RMS Changed t_addr to unsigned
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The PDP-1 was Digital's first computer. Although Digital built four
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other 18b computers, the later systems (the PDP-4, PDP-7, PDP-9, and
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PDP-15) were similar to each other and quite different from the PDP-1.
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Accordingly, the PDP-1 requires a distinct simulator.
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The register state for the PDP-1 is:
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AC<0:17> accumulator
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IO<0:17> IO register
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OV overflow flag
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PC<0:15> program counter
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IOSTA I/O status register
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SBS<0:2> sequence break flip flops
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IOH I/O halt flip flop
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IOC I/O completion flip flop
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EXTM extend mode
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PF<1:6> program flags
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SS<1:6> sense switches
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TW<0:17> test word (switch register)
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Questions:
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cks: which bits are line printer print done and space done?
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cks: is there a bit for sequence break enabled (yes, according
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to the 1963 Handbook)
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sbs: do sequence breaks accumulate while the system is disabled
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(yes, according to the Maintenance Manual)
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*/
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/* The PDP-1 has six instruction formats: memory reference, skips,
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shifts, load immediate, I/O transfer, and operate. The memory
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reference format is:
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| op |in| address | memory reference
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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<0:4> <5> mnemonic action
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00
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02 AND AC = AC & M[MA]
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04 IOR AC = AC | M[MA]
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06 XOR AC = AC ^ M[MA]
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10 XCT M[MA] is executed as an instruction
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12
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14
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16 0 CAL M[100] = AC, AC = PC, PC = 101
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16 1 JDA M[MA] = AC, AC = PC, PC = MA + 1
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20 LAC AC = M[MA]
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22 LIO IO = M[MA]
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24 DAC M[MA] = AC
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26 DAP M[MA]<6:17> = AC<6:17>
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30 DIP M[MA]<0:5> = AC<0:5>
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32 DIO M[MA] = IO
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34 DZM M[MA] = 0
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36
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40 ADD AC = AC + M[MA]
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42 SUB AC = AC - M[MA]
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44 IDX AC = M[MA] = M[MA] + 1
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46 ISP AC = M[MA] = M[MA] + 1, skip if AC >= 0
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50 SAD skip if AC != M[MA]
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52 SAS skip if AC == M[MA]
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54 MUL AC'IO = AC * M[MA]
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56 DIV AC, IO = AC'IO / M[MA]
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60 JMP PC = MA
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62 JSP AC = PC, PC = MA
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Memory reference instructions can access an address space of 64K words.
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The address space is divided into sixteen 4K word fields. An
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instruction can directly address, via its 12b address, the entire
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current field. If extend mode is off, indirect addresses access
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the current field, and indirect addressing is multi-level; if off,
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they can access all 64K, and indirect addressing is single level.
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*/
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/* The skip format is:
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| 1 1 0 1 0| | | | | | | | | | | | | | skip
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| | | | | | \______/ \______/
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| | | | | | | |
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| | | | | | | +---- program flags
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| | | | | | +------------- sense switches
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| | | | | +------------------- AC == 0
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| | | | +---------------------- AC >= 0
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| | | +------------------------- AC < 0
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| | +---------------------------- OV == 0
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| +------------------------------- IO >= 0
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+------------------------------------- invert skip
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The shift format is:
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| 1 1 0 1 1| subopcode | encoded count | shift
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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The load immediate format is:
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| 1 1 1 0 0| S| immediate | LAW
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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<0:4> mnemonic action
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70 LAW if S = 0, AC = IR<6:17>
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else AC = ~IR<6:17>
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*/
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/* The I/O transfer format is:
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| 1 1 1 0 1| W| C| subopcode | device | I/O transfer
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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The IO transfer instruction sends the the specified subopcode to
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specified I/O device. The I/O device may take data from the IO or
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return data to the IO, initiate or cancel operations, etc. The
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W bit specifies whether the CPU waits for completion, the C bit
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whether a completion pulse will be returned from the device.
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The operate format is:
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| 1 1 1 1 1| | | | | | | | | | | | | | operate
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+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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| | | | | | | \______/
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| | | | | | | |
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| | | | | | | +---- PF select
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| | | | | | +---------- clear/set PF
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| | | | | +------------------- or PC
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| | | | +---------------------- clear AC
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| | | +------------------------- halt
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| | +---------------------------- CMA
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| +------------------------------- or TW
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+---------------------------------- clear IO
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The operate instruction can be microprogrammed.
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*/
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/* This routine is the instruction decode routine for the PDP-1.
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It is called from the simulator control program to execute
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instructions in simulated memory, starting at the simulated PC.
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It runs until 'reason' is set non-zero.
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General notes:
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1. Reasons to stop. The simulator can be stopped by:
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HALT instruction
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breakpoint encountered
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unimplemented instruction and STOP_INST flag set
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XCT loop
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indirect address loop
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infinite wait state
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I/O error in I/O simulator
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2. Interrupts. With a single channel sequence break system, the
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PDP-1 has a single break request (flop b2, here sbs<SB_V_RQ>).
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If sequence breaks are enabled (flop sbm, here sbs<SB_V_ON>),
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and one is not already in progress (flop b4, here sbs<SB_V_IP>),
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a sequence break occurs.
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3. Arithmetic. The PDP-1 is a 1's complement system. In 1's
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complement arithmetic, a negative number is represented by the
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complement (XOR 0777777) of its absolute value. Addition of 1's
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complement numbers requires propagating the carry out of the high
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order bit back to the low order bit.
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4. Adding I/O devices. Three modules must be modified:
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pdp1_defs.h add interrupt request definition
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pdp1_cpu.c add IOT dispatches
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pdp1_sys.c add pointer to data structures to sim_devices
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*/
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#include "pdp1_defs.h"
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#define UNIT_V_MDV (UNIT_V_UF) /* mul/div */
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#define UNIT_MDV (1 << UNIT_V_MDV)
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#define UNIT_V_MSIZE (UNIT_V_UF+1) /* dummy mask */
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#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
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int32 M[MAXMEMSIZE] = { 0 }; /* memory */
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int32 AC = 0; /* AC */
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int32 IO = 0; /* IO */
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int32 PC = 0; /* PC */
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int32 OV = 0; /* overflow */
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int32 SS = 0; /* sense switches */
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int32 PF = 0; /* program flags */
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int32 TW = 0; /* test word */
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int32 iosta = 0; /* status reg */
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int32 sbs = 0; /* sequence break */
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int32 sbs_init = 0; /* seq break startup */
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int32 ioh = 0; /* I/O halt */
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int32 ioc = 0; /* I/O completion */
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int32 extm = 0; /* ext mem mode */
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int32 extm_init = 0; /* ext mem startup */
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int32 stop_inst = 0; /* stop on rsrv inst */
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int32 xct_max = 16; /* nested XCT limit */
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int32 ind_max = 16; /* nested ind limit */
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int32 old_PC = 0; /* old PC */
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extern UNIT *sim_clock_queue;
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extern int32 sim_int_char;
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extern int32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
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t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_reset (DEVICE *dptr);
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t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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extern int32 ptr (int32 inst, int32 dev, int32 IO);
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extern int32 ptp (int32 inst, int32 dev, int32 IO);
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extern int32 tti (int32 inst, int32 dev, int32 IO);
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extern int32 tto (int32 inst, int32 dev, int32 IO);
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extern int32 lpt (int32 inst, int32 dev, int32 IO);
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extern t_stat sim_activate (UNIT *uptr, int32 delay);
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int32 sc_map[512] = {
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0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, /* 00000xxxx */
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1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 00001xxxx */
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1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 00010xxxx */
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2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 00011xxxx */
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1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 00100xxxx */
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2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 00101xxxx */
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2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 00110xxxx */
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3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 00111xxxx */
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1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 01000xxxx */
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2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 01001xxxx */
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2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 01010xxxx */
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3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 01011xxxx */
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2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 01100xxxx */
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3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 01101xxxx */
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3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 01110xxxx */
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4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, /* 01111xxxx */
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1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, /* 10000xxxx */
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2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 10001xxxx */
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2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 10010xxxx */
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3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 10011xxxx */
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2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 10100xxxx */
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3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 10101xxxx */
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3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 10110xxxx */
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4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, /* 11011xxxx */
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2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, /* 11000xxxx */
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3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 11001xxxx */
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3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 11010xxxx */
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4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, /* 11011xxxx */
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3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, /* 11100xxxx */
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4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, /* 11101xxxx */
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4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, /* 11110xxxx */
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5, 6, 6, 7, 6, 7, 7, 8, 6, 7, 7, 8, 7, 8, 8, 9 /* 11111xxxx */
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};
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/* CPU data structures
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cpu_dev CPU device descriptor
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cpu_unit CPU unit
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cpu_reg CPU register list
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cpu_mod CPU modifier list
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*/
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UNIT cpu_unit = { UDATA (NULL, UNIT_FIX + UNIT_BINK, MAXMEMSIZE) };
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REG cpu_reg[] = {
|
||||
{ ORDATA (PC, PC, ASIZE) },
|
||||
{ ORDATA (AC, AC, 18) },
|
||||
{ ORDATA (IO, IO, 18) },
|
||||
{ FLDATA (OV, OV, 0) },
|
||||
{ ORDATA (PF, PF, 6) },
|
||||
{ ORDATA (SS, SS, 6) },
|
||||
{ ORDATA (TW, TW, 18) },
|
||||
{ FLDATA (EXTM, extm, 0) },
|
||||
{ ORDATA (IOSTA, iosta, 18), REG_RO },
|
||||
{ FLDATA (SBON, sbs, SB_V_ON) },
|
||||
{ FLDATA (SBRQ, sbs, SB_V_RQ) },
|
||||
{ FLDATA (SBIP, sbs, SB_V_IP) },
|
||||
{ FLDATA (IOH, ioh, 0) },
|
||||
{ FLDATA (IOC, ioc, 0) },
|
||||
{ ORDATA (OLDPC, old_PC, ASIZE), REG_RO },
|
||||
{ FLDATA (STOP_INST, stop_inst, 0) },
|
||||
{ FLDATA (SBS_INIT, sbs_init, SB_V_ON) },
|
||||
{ FLDATA (EXTM_INIT, extm_init, 0) },
|
||||
{ FLDATA (MDV, cpu_unit.flags, UNIT_V_MDV), REG_HRO },
|
||||
{ DRDATA (XCT_MAX, xct_max, 8), PV_LEFT + REG_NZ },
|
||||
{ DRDATA (IND_MAX, ind_max, 8), PV_LEFT + REG_NZ },
|
||||
{ ORDATA (WRU, sim_int_char, 8) },
|
||||
{ NULL } };
|
||||
|
||||
MTAB cpu_mod[] = {
|
||||
{ UNIT_MDV, UNIT_MDV, "multiply/divide", "MDV", NULL },
|
||||
{ UNIT_MDV, 0, "no multiply/divide", "NOMDV", NULL },
|
||||
{ UNIT_MSIZE, 4096, NULL, "4K", &cpu_set_size },
|
||||
{ UNIT_MSIZE, 8192, NULL, "8K", &cpu_set_size },
|
||||
{ UNIT_MSIZE, 12288, NULL, "12K", &cpu_set_size },
|
||||
{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size },
|
||||
{ UNIT_MSIZE, 20480, NULL, "20K", &cpu_set_size },
|
||||
{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size },
|
||||
{ UNIT_MSIZE, 28672, NULL, "28K", &cpu_set_size },
|
||||
{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size },
|
||||
{ UNIT_MSIZE, 49152, NULL, "48K", &cpu_set_size },
|
||||
{ UNIT_MSIZE, 65536, NULL, "64K", &cpu_set_size },
|
||||
{ 0 } };
|
||||
|
||||
DEVICE cpu_dev = {
|
||||
"CPU", &cpu_unit, cpu_reg, cpu_mod,
|
||||
1, 8, ASIZE, 1, 8, 18,
|
||||
&cpu_ex, &cpu_dep, &cpu_reset,
|
||||
NULL, NULL, NULL };
|
||||
|
||||
t_stat sim_instr (void)
|
||||
{
|
||||
extern int32 sim_interval;
|
||||
int32 IR, MA, op, i, t, xct_count;
|
||||
int32 sign, signd, v;
|
||||
int32 dev, io_data, sc, skip;
|
||||
t_stat reason;
|
||||
static int32 fs_test[8] = {
|
||||
0, 040, 020, 010, 04, 02, 01, 077 };
|
||||
|
||||
#define EPC_WORD ((OV << 17) | (extm << 16) | PC)
|
||||
#define INCR_ADDR(x) (((x) & EPCMASK) | (((x) + 1) & DAMASK))
|
||||
#define DECR_ADDR(x) (((x) & EPCMASK) | (((x) - 1) & DAMASK))
|
||||
#define ABS(x) ((x) ^ (((x) & 0400000)? 0777777: 0))
|
||||
|
||||
/* Main instruction fetch/decode loop: check events and interrupts */
|
||||
|
||||
reason = 0;
|
||||
while (reason == 0) { /* loop until halted */
|
||||
|
||||
if (sim_interval <= 0) { /* check clock queue */
|
||||
if (reason = sim_process_event ()) break; }
|
||||
|
||||
if (sbs == (SB_ON | SB_RQ)) { /* interrupt? */
|
||||
sbs = SB_ON | SB_IP; /* set in prog flag */
|
||||
old_PC = PC; /* save old PC */
|
||||
M[0] = AC; /* save state */
|
||||
M[1] = EPC_WORD;
|
||||
M[2] = IO;
|
||||
PC = 3; /* fetch next from 3 */
|
||||
extm = 0; /* extend off */
|
||||
OV = 0; } /* clear overflow */
|
||||
|
||||
if (sim_brk_summ && sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */
|
||||
reason = STOP_IBKPT; /* stop simulation */
|
||||
break; }
|
||||
|
||||
/* Fetch, decode instruction */
|
||||
|
||||
MA = PC; /* PC to MA */
|
||||
IR = M[MA]; /* fetch instruction */
|
||||
PC = INCR_ADDR (PC); /* increment PC */
|
||||
xct_count = 0; /* track nested XCT's */
|
||||
sim_interval = sim_interval - 1;
|
||||
|
||||
xct_instr: /* label for XCT */
|
||||
if ((IR == 0610001) && ((MA & EPCMASK) == 0) && (sbs & SB_ON)) {
|
||||
sbs = sbs & ~SB_IP; /* seq debreak */
|
||||
old_PC = PC; /* save old PC */
|
||||
OV = (M[1] >> 17) & 1; /* restore OV */
|
||||
extm = (M[1] >> 16) & 1; /* restore ext mode */
|
||||
PC = M[1] & AMASK; /* JMP I 1 */
|
||||
continue; }
|
||||
|
||||
op = ((IR >> 13) & 037); /* get opcode */
|
||||
if ((op < 032) && (op != 007)) { /* mem ref instr */
|
||||
MA = (MA & EPCMASK) | (IR & DAMASK); /* direct address */
|
||||
if (IR & IA) { /* indirect addr? */
|
||||
if (extm) MA = M[MA] & AMASK; /* if ext, one level */
|
||||
else { for (i = 0; i < ind_max; i++) { /* count indirects */
|
||||
t = M[MA]; /* get indirect word */
|
||||
MA = (MA & EPCMASK) | (t & DAMASK);
|
||||
if ((t & IA) == 0) break; }
|
||||
if (i >= ind_max) { /* indirect loop? */
|
||||
reason = STOP_IND;
|
||||
break; } } } }
|
||||
|
||||
switch (op) { /* decode IR<0:4> */
|
||||
|
||||
/* Logical, load, store instructions */
|
||||
|
||||
case 001: /* AND */
|
||||
AC = AC & M[MA];
|
||||
break;
|
||||
case 002: /* IOR */
|
||||
AC = AC | M[MA];
|
||||
break;
|
||||
case 003: /* XOR */
|
||||
AC = AC ^ M[MA];
|
||||
break;
|
||||
case 004: /* XCT */
|
||||
if (xct_count >= xct_max) { /* too many XCT's? */
|
||||
reason = STOP_XCT;
|
||||
break; }
|
||||
xct_count = xct_count + 1; /* count XCT's */
|
||||
IR = M[MA]; /* get instruction */
|
||||
goto xct_instr; /* go execute */
|
||||
case 007: /* CAL, JDA */
|
||||
MA = (PC & EPCMASK) | ((IR & IA)? (IR & DAMASK): 0100);
|
||||
old_PC = PC;
|
||||
M[MA] = AC;
|
||||
AC = EPC_WORD;
|
||||
PC = INCR_ADDR (MA);
|
||||
break;
|
||||
case 010: /* LAC */
|
||||
AC = M[MA];
|
||||
break;
|
||||
case 011: /* LIO */
|
||||
IO = M[MA];
|
||||
break;
|
||||
case 012: /* DAC */
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = AC;
|
||||
break;
|
||||
case 013: /* DAP */
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = (AC & DAMASK) | (M[MA] & ~DAMASK);
|
||||
break;
|
||||
case 014: /* DIP */
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = (AC & ~DAMASK) | (M[MA] & DAMASK);
|
||||
break;
|
||||
case 015: /* DIO */
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = IO;
|
||||
break;
|
||||
case 016: /* DZM */
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = 0;
|
||||
break;
|
||||
|
||||
/* Add, subtract, control
|
||||
|
||||
Add is performed in sequential steps, as follows:
|
||||
1. add
|
||||
2. end around carry propagate
|
||||
3. overflow check
|
||||
4. -0 cleanup
|
||||
|
||||
Subtract is performed in sequential steps, as follows:
|
||||
1. complement AC
|
||||
2. add
|
||||
3. end around carry propagate
|
||||
4. overflow check
|
||||
5. complement AC
|
||||
Because no -0 check is done, (-0) - (+0) yields a result of -0
|
||||
*/
|
||||
|
||||
case 020: /* ADD */
|
||||
t = AC;
|
||||
AC = AC + M[MA];
|
||||
if (AC > 0777777) AC = (AC + 1) & 0777777; /* end around carry */
|
||||
if (((~t ^ M[MA]) & (t ^ AC)) & 0400000) OV = 1;
|
||||
if (AC == 0777777) AC = 0; /* minus 0 cleanup */
|
||||
break;
|
||||
case 021: /* SUB */
|
||||
t = AC ^ 0777777; /* complement AC */
|
||||
AC = t + M[MA]; /* -AC + MB */
|
||||
if (AC > 0777777) AC = (AC + 1) & 0777777; /* end around carry */
|
||||
if (((~t ^ M[MA]) & (t ^ AC)) & 0400000) OV = 1;
|
||||
AC = AC ^ 0777777; /* recomplement AC */
|
||||
break;
|
||||
case 022: /* IDX */
|
||||
AC = M[MA] + 1;
|
||||
if (AC >= 0777777) AC = (AC + 1) & 0777777;
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = AC;
|
||||
break;
|
||||
case 023: /* ISP */
|
||||
AC = M[MA] + 1;
|
||||
if (AC >= 0777777) AC = (AC + 1) & 0777777;
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = AC;
|
||||
if (AC < 0400000) PC = INCR_ADDR (PC);
|
||||
break;
|
||||
case 024: /* SAD */
|
||||
if (AC != M[MA]) PC = INCR_ADDR (PC);
|
||||
break;
|
||||
case 025: /* SAS */
|
||||
if (AC == M[MA]) PC = INCR_ADDR (PC);
|
||||
break;
|
||||
case 030: /* JMP */
|
||||
old_PC = PC;
|
||||
PC = MA;
|
||||
break;
|
||||
case 031: /* JSP */
|
||||
AC = EPC_WORD;
|
||||
old_PC = PC;
|
||||
PC = MA;
|
||||
break;
|
||||
case 034: /* LAW */
|
||||
AC = (IR & 07777) ^ ((IR & IA)? 0777777: 0);
|
||||
break;
|
||||
|
||||
/* Multiply and divide
|
||||
|
||||
Multiply and divide step and hardware multiply are exact implementations.
|
||||
Hardware divide is a 2's complement analog to the actual hardware.
|
||||
*/
|
||||
|
||||
case 026: /* MUL */
|
||||
if (cpu_unit.flags & UNIT_MDV) { /* hardware? */
|
||||
sign = AC ^ M[MA]; /* result sign */
|
||||
IO = ABS (AC); /* IO = |AC| */
|
||||
v = ABS (M[MA]); /* v = |mpy| */
|
||||
for (i = AC = 0; i < 17; i++) {
|
||||
if (IO & 1) AC = AC + v;
|
||||
IO = (IO >> 1) | ((AC & 1) << 17);
|
||||
AC = AC >> 1; }
|
||||
if ((sign & 0400000) && (AC | IO)) { /* negative, > 0? */
|
||||
AC = AC ^ 0777777;
|
||||
IO = IO ^ 0777777; } }
|
||||
else { if (IO & 1) AC = AC + M[MA]; /* multiply step */
|
||||
if (AC > 0777777) AC = (AC + 1) & 0777777;
|
||||
if (AC == 0777777) AC = 0;
|
||||
IO = (IO >> 1) | ((AC & 1) << 17);
|
||||
AC = AC >> 1; }
|
||||
break;
|
||||
|
||||
case 027: /* DIV */
|
||||
if (cpu_unit.flags & UNIT_MDV) { /* hardware */
|
||||
sign = AC ^ M[MA]; /* result sign */
|
||||
signd = AC; /* remainder sign */
|
||||
if (AC & 0400000) {
|
||||
AC = AC ^ 0777777; /* AC'IO = |AC'IO| */
|
||||
IO = IO ^ 0777777; }
|
||||
v = ABS (M[MA]); /* v = |divr| */
|
||||
if (AC >= v) break; /* overflow? */
|
||||
for (i = t = 0; i < 18; i++) {
|
||||
if (t) AC = (AC + v) & 0777777;
|
||||
else AC = (AC - v) & 0777777;
|
||||
t = AC >> 17;
|
||||
if (i != 17) AC = ((AC << 1) | (IO >> 17)) & 0777777;
|
||||
IO = ((IO << 1) | (t ^ 1)) & 0777777; }
|
||||
if (t) AC = (AC + v) & 0777777; /* correct remainder */
|
||||
t = ((signd & 0400000) && AC)? AC ^ 0777777: AC;
|
||||
AC = ((sign & 0400000) && IO)? IO ^ 0777777: IO;
|
||||
IO = t;
|
||||
PC = INCR_ADDR (PC); } /* skip */
|
||||
else { t = AC >> 17; /* divide step */
|
||||
AC = ((AC << 1) | (IO >> 17)) & 0777777;
|
||||
IO = ((IO << 1) | (t ^ 1)) & 0777777;
|
||||
if (IO & 1) AC = AC + (M[MA] ^ 0777777);
|
||||
else AC = AC + M[MA] + 1;
|
||||
if (AC > 0777777) AC = (AC + 1) & 0777777;
|
||||
if (AC == 0777777) AC = 0; }
|
||||
break;
|
||||
|
||||
/* Skip and operate
|
||||
|
||||
Operates execute in the order shown; there are no timing conflicts
|
||||
*/
|
||||
|
||||
case 032: /* skip */
|
||||
v = (IR >> 3) & 07; /* sense switches */
|
||||
t = IR & 07; /* program flags */
|
||||
skip = (((IR & 02000) && (IO < 0400000)) || /* SPI */
|
||||
((IR & 01000) && (OV == 0)) || /* SZO */
|
||||
((IR & 00400) && (AC >= 0400000)) || /* SMA */
|
||||
((IR & 00200) && (AC < 0400000)) || /* SPA */
|
||||
((IR & 00100) && (AC == 0)) || /* SZA */
|
||||
(v && ((SS & fs_test[v]) == 0)) || /* SZSn */
|
||||
(t && ((PF & fs_test[t]) == 0))); /* SZFn */
|
||||
if (IR & IA) skip = skip ^ 1; /* invert skip? */
|
||||
if (skip) PC = INCR_ADDR (PC);
|
||||
if (IR & 01000) OV = 0; /* SOV clears OV */
|
||||
break;
|
||||
|
||||
case 037: /* operate */
|
||||
if (IR & 04000) IO = 0; /* CLI */
|
||||
if (IR & 00200) AC = 0; /* CLA */
|
||||
if (IR & 02000) AC = AC | TW; /* LAT */
|
||||
if (IR & 00100) AC = AC | EPC_WORD; /* LAP */
|
||||
if (IR & 01000) AC = AC ^ 0777777; /* CMA */
|
||||
if (IR & 00400) reason = STOP_HALT; /* HALT */
|
||||
t = IR & 07; /* flag select */
|
||||
if (IR & 010) PF = PF | fs_test[t]; /* STFn */
|
||||
else PF = PF & ~fs_test[t]; /* CLFn */
|
||||
break;
|
||||
|
||||
/* Shifts */
|
||||
|
||||
case 033:
|
||||
sc = sc_map[IR & 0777]; /* map shift count */
|
||||
switch ((IR >> 9) & 017) { /* case on IR<5:8> */
|
||||
case 001: /* RAL */
|
||||
AC = ((AC << sc) | (AC >> (18 - sc))) & 0777777;
|
||||
break;
|
||||
case 002: /* RIL */
|
||||
IO = ((IO << sc) | (IO >> (18 - sc))) & 0777777;
|
||||
break;
|
||||
case 003: /* RCL */
|
||||
t = AC;
|
||||
AC = ((AC << sc) | (IO >> (18 - sc))) & 0777777;
|
||||
IO = ((IO << sc) | (t >> (18 - sc))) & 0777777;
|
||||
break;
|
||||
case 005: /* SAL */
|
||||
t = (AC & 0400000)? 0777777: 0;
|
||||
AC = (AC & 0400000) | ((AC << sc) & 0377777) |
|
||||
(t >> (18 - sc));
|
||||
break;
|
||||
case 006: /* SIL */
|
||||
t = (IO & 0400000)? 0777777: 0;
|
||||
IO = (IO & 0400000) | ((IO << sc) & 0377777) |
|
||||
(t >> (18 - sc));
|
||||
break;
|
||||
case 007: /* SCL */
|
||||
t = (AC & 0400000)? 0777777: 0;
|
||||
AC = (AC & 0400000) | ((AC << sc) & 0377777) |
|
||||
(IO >> (18 - sc));
|
||||
IO = ((IO << sc) | (t >> (18 - sc))) & 0777777;
|
||||
break;
|
||||
case 011: /* RAR */
|
||||
AC = ((AC >> sc) | (AC << (18 - sc))) & 0777777;
|
||||
break;
|
||||
case 012: /* RIR */
|
||||
IO = ((IO >> sc) | (IO << (18 - sc))) & 0777777;
|
||||
break;
|
||||
case 013: /* RCR */
|
||||
t = IO;
|
||||
IO = ((IO >> sc) | (AC << (18 - sc))) & 0777777;
|
||||
AC = ((AC >> sc) | (t << (18 - sc))) & 0777777;
|
||||
break;
|
||||
case 015: /* SAR */
|
||||
t = (AC & 0400000)? 0777777: 0;
|
||||
AC = ((AC >> sc) | (t << (18 - sc))) & 0777777;
|
||||
break;
|
||||
case 016: /* SIR */
|
||||
t = (IO & 0400000)? 0777777: 0;
|
||||
IO = ((IO >> sc) | (t << (18 - sc))) & 0777777;
|
||||
break;
|
||||
case 017: /* SCR */
|
||||
t = (AC & 0400000)? 0777777: 0;
|
||||
IO = ((IO >> sc) | (AC << (18 - sc))) & 0777777;
|
||||
AC = ((AC >> sc) | (t << (18 - sc))) & 0777777;
|
||||
break;
|
||||
default: /* undefined */
|
||||
reason = stop_inst;
|
||||
break; } /* end switch shifts */
|
||||
break;
|
||||
|
||||
/* IOT */
|
||||
|
||||
case 035:
|
||||
if (IR & IO_WAIT) { /* wait? */
|
||||
if (ioh) { /* I/O halt? */
|
||||
if (ioc) ioh = 0; /* comp pulse? done */
|
||||
else { sim_interval = 0; /* force event */
|
||||
PC = DECR_ADDR (PC); } /* re-execute */
|
||||
break; } /* skip iot */
|
||||
ioh = 1; /* turn on halt */
|
||||
PC = DECR_ADDR (PC); } /* re-execute */
|
||||
dev = IR & 077; /* get dev addr */
|
||||
io_data = IO; /* default data */
|
||||
switch (dev) { /* case on dev */
|
||||
case 000: /* I/O wait */
|
||||
break;
|
||||
case 001: case 002: case 030: /* paper tape rdr */
|
||||
io_data = ptr (IR, dev, IO);
|
||||
break;
|
||||
case 003: /* typewriter */
|
||||
io_data = tto (IR, dev, IO);
|
||||
break;
|
||||
case 004: /* keyboard */
|
||||
io_data = tti (IR, dev, IO);
|
||||
break;
|
||||
case 005: case 006: /* paper tape punch */
|
||||
io_data = ptp (IR, dev, IO);
|
||||
break;
|
||||
case 033: /* check status */
|
||||
io_data = iosta | ((sbs & SB_ON)? IOS_SQB: 0);
|
||||
break;
|
||||
case 045: /* line printer */
|
||||
io_data = lpt (IR, dev, IO);
|
||||
break;
|
||||
case 054: /* seq brk off */
|
||||
sbs = sbs & ~SB_ON;
|
||||
break;
|
||||
case 055: /* seq brk on */
|
||||
sbs = sbs | SB_ON;
|
||||
break;
|
||||
case 056: /* clear seq brk */
|
||||
sbs = sbs & ~SB_IP;
|
||||
break;
|
||||
case 074: /* extend mode */
|
||||
extm = (IR >> 11) & 1; /* set from IR<6> */
|
||||
break;
|
||||
default: /* undefined */
|
||||
reason = stop_inst;
|
||||
break; } /* end switch dev */
|
||||
IO = io_data & 0777777;
|
||||
if (io_data >= IOT_REASON) reason = io_data >> IOT_V_REASON;
|
||||
break;
|
||||
default: /* undefined */
|
||||
reason = STOP_RSRV; /* halt */
|
||||
break; } /* end switch opcode */
|
||||
} /* end while */
|
||||
return reason;
|
||||
}
|
||||
|
||||
/* Reset routine */
|
||||
|
||||
t_stat cpu_reset (DEVICE *dptr)
|
||||
{
|
||||
sbs = sbs_init;
|
||||
extm = extm_init;
|
||||
ioh = ioc = 0;
|
||||
OV = 0;
|
||||
PF = 0;
|
||||
sim_brk_types = sim_brk_dflt = SWMASK ('E');
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Memory examine */
|
||||
|
||||
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
|
||||
{
|
||||
if (addr >= MEMSIZE) return SCPE_NXM;
|
||||
if (vptr != NULL) *vptr = M[addr] & 0777777;
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Memory deposit */
|
||||
|
||||
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw)
|
||||
{
|
||||
if (addr >= MEMSIZE) return SCPE_NXM;
|
||||
M[addr] = val & 0777777;
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Change memory size */
|
||||
|
||||
t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||||
{
|
||||
int32 mc = 0;
|
||||
t_addr i;
|
||||
|
||||
if ((val <= 0) || (val > MAXMEMSIZE) || ((val & 07777) != 0))
|
||||
return SCPE_ARG;
|
||||
for (i = val; i < MEMSIZE; i++) mc = mc | M[i];
|
||||
if ((mc != 0) && (!get_yn ("Really truncate memory [N]?", FALSE)))
|
||||
return SCPE_OK;
|
||||
MEMSIZE = val;
|
||||
for (i = MEMSIZE; i < MAXMEMSIZE; i++) M[i] = 0;
|
||||
return SCPE_OK;
|
||||
}
|
||||
103
PDP1/pdp1_defs.h
Normal file
103
PDP1/pdp1_defs.h
Normal file
@@ -0,0 +1,103 @@
|
||||
/* pdp1_defs.h: 18b PDP simulator definitions
|
||||
|
||||
Copyright (c) 1993-2001, Robert M. Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of Robert M Supnik shall not
|
||||
be used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
14-Apr-99 RMS Changed t_addr to unsigned
|
||||
|
||||
The PDP-1 was Digital's first computer. The system design evolved during
|
||||
its life, and as a result, specifications are sketchy or contradictory.
|
||||
This simulator is based on the 1962 maintenance manual.
|
||||
|
||||
This simulator implements the following options:
|
||||
|
||||
Automatic multiply/divide Type 10
|
||||
Memory extension control Type 15
|
||||
Line printer control Type 62
|
||||
*/
|
||||
|
||||
#include "sim_defs.h"
|
||||
|
||||
/* Simulator stop codes */
|
||||
|
||||
#define STOP_RSRV 1 /* must be 1 */
|
||||
#define STOP_HALT 2 /* HALT */
|
||||
#define STOP_IBKPT 3 /* breakpoint */
|
||||
#define STOP_XCT 4 /* nested XCT's */
|
||||
#define STOP_IND 5 /* nested indirects */
|
||||
#define STOP_WAIT 6 /* wait state */
|
||||
|
||||
/* Memory */
|
||||
|
||||
#define ASIZE 16 /* address bits */
|
||||
#define MAXMEMSIZE (1u << ASIZE) /* max mem size */
|
||||
#define AMASK (MAXMEMSIZE - 1) /* address mask */
|
||||
#define MEMSIZE (cpu_unit.capac) /* actual memory size */
|
||||
#define MEM_ADDR_OK(x) (((t_addr) (x)) < MEMSIZE)
|
||||
|
||||
/* Architectural constants */
|
||||
|
||||
#define DAMASK 007777 /* direct addr */
|
||||
#define EPCMASK (AMASK & ~DAMASK) /* extended addr */
|
||||
#define IA 010000 /* indirect flag */
|
||||
#define IO_WAIT 010000 /* I/O sync wait */
|
||||
#define IO_CPLS 004000 /* completion pulse */
|
||||
#define GEN_CPLS(x) (((x) ^ ((x) << 1)) & IO_WAIT) /* completion pulse? */
|
||||
|
||||
/* IOT subroutine return codes */
|
||||
|
||||
#define IOT_V_REASON 18 /* reason */
|
||||
#define IOT_REASON (1 << IOT_V_REASON)
|
||||
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */
|
||||
|
||||
/* I/O status flags */
|
||||
|
||||
#define IOS_V_LPN 17 /* light pen */
|
||||
#define IOS_V_PTR 16 /* paper tape reader */
|
||||
#define IOS_V_TTO 15 /* typewriter out */
|
||||
#define IOS_V_TTI 14 /* typewriter in */
|
||||
#define IOS_V_PTP 13 /* paper tape punch */
|
||||
#define IOS_V_DRM 12 /* drum */
|
||||
#define IOS_V_SQB 11 /* sequence break */
|
||||
#define IOS_V_PNT 2 /* print done */
|
||||
#define IOS_V_SPC 1 /* space done */
|
||||
|
||||
#define IOS_LPN (1 << IOS_V_LPN)
|
||||
#define IOS_PTR (1 << IOS_V_PTR)
|
||||
#define IOS_TTO (1 << IOS_V_TTO)
|
||||
#define IOS_TTI (1 << IOS_V_TTI)
|
||||
#define IOS_PTP (1 << IOS_V_PTP)
|
||||
#define IOS_DRM (1 << IOS_V_DRM)
|
||||
#define IOS_SQB (1 << IOS_V_SQB)
|
||||
#define IOS_PNT (1 << IOS_V_PNT)
|
||||
#define IOS_SPC (1 << IOS_V_SPC)
|
||||
|
||||
/* Sequence break flags */
|
||||
|
||||
#define SB_V_IP 0 /* in progress */
|
||||
#define SB_V_RQ 1 /* request */
|
||||
#define SB_V_ON 2 /* enabled */
|
||||
|
||||
#define SB_IP (1 << SB_V_IP)
|
||||
#define SB_RQ (1 << SB_V_RQ)
|
||||
#define SB_ON (1 << SB_V_ON)
|
||||
409
PDP1/pdp1_doc.txt
Normal file
409
PDP1/pdp1_doc.txt
Normal file
@@ -0,0 +1,409 @@
|
||||
To: Users
|
||||
From: Bob Supnik
|
||||
Subj: PDP-1 Simulator Usage
|
||||
Date: 1-Dec-01
|
||||
|
||||
COPYRIGHT NOTICE
|
||||
|
||||
The following copyright notice applies to both the SIMH source and binary:
|
||||
|
||||
Original code published in 1993-2001, written by Robert M Supnik
|
||||
Copyright (c) 1993-2001, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of Robert M Supnik shall not
|
||||
be used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
This memorandum documents the PDP-1 simulator.
|
||||
|
||||
|
||||
1. Simulator Files
|
||||
|
||||
sim/ sim_defs.h
|
||||
scp.c
|
||||
scp_tty.c
|
||||
sim_rev.c
|
||||
|
||||
sim/pdp1/ pdp1_defs.h
|
||||
pdp1_cpu.c
|
||||
pdp1_lp.c
|
||||
pdp1_stddev.c
|
||||
pdp1_sys.c
|
||||
|
||||
2. PDP-1 Features
|
||||
|
||||
The PDP-1 is configured as follows:
|
||||
|
||||
device simulates
|
||||
name(s)
|
||||
|
||||
CPU PDP-1 CPU with up to 64KW of memory
|
||||
PTR,PTP integral paper tape reader/punch
|
||||
TTI,TTO Flexowriter typewriter input/output
|
||||
LPT Type 62 line printer
|
||||
|
||||
The PDP-1 simulator implements the following unique stop conditions:
|
||||
|
||||
- an unimplemented instruction is decoded, and register
|
||||
STOP_INST is set
|
||||
- more than INDMAX indirect addresses are detected during
|
||||
memory reference address decoding
|
||||
- more than XCTMAX nested executes are detected during
|
||||
instruction execution
|
||||
- wait state entered, and no I/O operations outstanding
|
||||
(ie, no interrupt can ever occur)
|
||||
|
||||
The PDP-1 loader supports RIM format tapes. The DUMP command is not
|
||||
implemented.
|
||||
|
||||
2.1 CPU
|
||||
|
||||
The only CPU options are the presence of hardware multiply/divide and the
|
||||
size of main memory.
|
||||
|
||||
SET CPU MDV enable multiply/divide
|
||||
SET CPU NOMDV disable multiply/divide
|
||||
SET CPU 4K set memory size = 4K
|
||||
SET CPU 8K set memory size = 8K
|
||||
SET CPU 12K set memory size = 12K
|
||||
SET CPU 16K set memory size = 16K
|
||||
SET CPU 20K set memory size = 20K
|
||||
SET CPU 24K set memory size = 24K
|
||||
SET CPU 28K set memory size = 28K
|
||||
SET CPU 32K set memory size = 32K
|
||||
SET CPU 48K set memory size = 48K
|
||||
SET CPU 64K set memory size = 64K
|
||||
|
||||
If memory size is being reduced, and the memory being truncated contains
|
||||
non-zero data, the simulator asks for confirmation. Data in the truncated
|
||||
portion of memory is lost. Initial memory size is 64K.
|
||||
|
||||
CPU registers include the visible state of the processor as well as the
|
||||
control registers for the interrupt system.
|
||||
|
||||
name size comments
|
||||
|
||||
PC 16 program counter
|
||||
AC 18 accumulator
|
||||
IO 18 IO register
|
||||
OV 1 overflow flag
|
||||
PF 6 program flags<1:6>
|
||||
SS 6 sense switches<1:6>
|
||||
TW 18 test word (front panel switches)
|
||||
EXTM 1 extend mode
|
||||
IOSTA 18 IO status register
|
||||
SBON 1 sequence break enable
|
||||
SBRQ 1 sequence break request
|
||||
SBIP 1 sequence break in progress
|
||||
IOH 1 I/O halt in progress
|
||||
IOC 1 I/O continue
|
||||
OLDPC 16 PC prior to last transfer
|
||||
STOP_INST 1 stop on undefined instruction
|
||||
SBS_INIT 1 initial state of sequence break enable
|
||||
EXTM_INIT 1 initial state of extend mode
|
||||
WRU 8 interrupt character
|
||||
|
||||
2.2 Programmed I/O Devices
|
||||
|
||||
2.2.1 Paper Tape Reader (PTR)
|
||||
|
||||
The paper tape reader (PTR) reads data from or a disk file. The POS
|
||||
register specifies the number of the next data item to be read. Thus,
|
||||
by changing POS, the user can backspace or advance the reader.
|
||||
|
||||
The paper tape reader supports the BOOT command. BOOT PTR copies the
|
||||
RIM loader into memory and starts it running.
|
||||
|
||||
The paper tape reader implements these registers:
|
||||
|
||||
name size comments
|
||||
|
||||
BUF 8 last data item processed
|
||||
DONE 1 device done flag
|
||||
RPLS 1 return restart pulse flag
|
||||
POS 31 position in the input file
|
||||
TIME 24 time from I/O initiation to interrupt
|
||||
STOP_IOE 1 stop on I/O error
|
||||
|
||||
Error handling is as follows:
|
||||
|
||||
error STOP_IOE processed as
|
||||
|
||||
not attached 1 report error and stop
|
||||
0 out of tape
|
||||
|
||||
end of file 1 report error and stop
|
||||
0 out of tape
|
||||
|
||||
OS I/O error x report error and stop
|
||||
|
||||
2.2.2 Paper Tape Punch (PTP)
|
||||
|
||||
The paper tape punch (PTP) writes data to a disk file. The POS
|
||||
register specifies the number of the next data item to be written.
|
||||
Thus, by changing POS, the user can backspace or advance the punch.
|
||||
|
||||
The paper tape punch implements these registers:
|
||||
|
||||
name size comments
|
||||
|
||||
BUF 8 last data item processed
|
||||
DONE 1 device done flag
|
||||
RPLS 1 return restart pulse flag
|
||||
POS 31 position in the output file
|
||||
TIME 24 time from I/O initiation to interrupt
|
||||
STOP_IOE 1 stop on I/O error
|
||||
|
||||
Error handling is as follows:
|
||||
|
||||
error STOP_IOE processed as
|
||||
|
||||
not attached 1 report error and stop
|
||||
0 out of tape
|
||||
|
||||
OS I/O error x report error and stop
|
||||
|
||||
2.2.3 Terminal Input (TTI)
|
||||
|
||||
The terminal input (TTI) polls the console keyboard for input. It
|
||||
implements these registers:
|
||||
|
||||
name size comments
|
||||
|
||||
BUF 8 last data item processed
|
||||
DONE 1 device done flag
|
||||
POS 31 number of characters input
|
||||
TIME 24 keyboard polling interval
|
||||
|
||||
2.2.4 Terminal Output (TTO)
|
||||
|
||||
The terminal output (TTO) writes to the simulator console window.
|
||||
It implements these registers:
|
||||
|
||||
name size comments
|
||||
|
||||
BUF 8 last data item processed
|
||||
DONE 1 device done flag
|
||||
RPLS 1 return restart pulse flag
|
||||
POS 31 number of characters output
|
||||
TIME 24 time from I/O initiation to interrupt
|
||||
|
||||
2.2.5 Type 62 Line Printer (LPT)
|
||||
|
||||
The paper line printer (LPT) writes data to a disk file. The POS
|
||||
register specifies the number of the next data item to be written.
|
||||
Thus, by changing POS, the user can backspace or advance the printer.
|
||||
|
||||
The line printer implements these registers:
|
||||
|
||||
name size comments
|
||||
|
||||
BUF 8 last data item processed
|
||||
PNT 1 printing done flag
|
||||
SPC 1 spacing done flag
|
||||
RPLS 1 return restart pulse flag
|
||||
BPTR 6 print buffer pointer
|
||||
POS 31 position in the output file
|
||||
TIME 24 time from I/O initiation to interrupt
|
||||
STOP_IOE 1 stop on I/O error
|
||||
LBUF[0:119] 8 line buffer
|
||||
|
||||
Error handling is as follows:
|
||||
|
||||
error STOP_IOE processed as
|
||||
|
||||
not attached 1 report error and stop
|
||||
0 out of tape or paper
|
||||
|
||||
OS I/O error x report error and stop
|
||||
|
||||
2.3 Symbolic Display and Input
|
||||
|
||||
The PDP-1 simulator implements symbolic display and input. Display is
|
||||
controlled by command line switches:
|
||||
|
||||
-a display as ASCII character
|
||||
-c display as FIODEC character string
|
||||
-m display instruction mnemonics
|
||||
|
||||
Input parsing is controlled by the first character typed in or by command
|
||||
line switches:
|
||||
|
||||
' or -a ASCII character
|
||||
" or -c three character FIODEC string
|
||||
alphabetic instruction mnemonic
|
||||
numeric octal number
|
||||
|
||||
Instruction input uses modified PDP-1 assembler syntax. There are six
|
||||
instruction classes: memory reference, shift, skip, operate, IOT, and
|
||||
LAW.
|
||||
|
||||
Memory reference instructions have the format
|
||||
|
||||
memref {I} address
|
||||
|
||||
where I signifies indirect reference. The address is an octal number in
|
||||
the range 0 - 0177777.
|
||||
|
||||
Shift instructions have the format
|
||||
|
||||
shift shift_count
|
||||
|
||||
The shift count is an octal number in the range 0-9.
|
||||
|
||||
Skip instructions consist of single mnemonics, eg, SZA, SZS4. Skip
|
||||
instructions may be or'd together
|
||||
|
||||
skip skip skip...
|
||||
|
||||
The sense of a skip can be inverted by including the mnemonic I.
|
||||
|
||||
Operate instructions consist of single mnemonics, eg, CLA, CLI. Operate
|
||||
instructions may be or'd together
|
||||
|
||||
opr opr opr...
|
||||
|
||||
IOT instructions consist of single mnemonics, eg, TYI, TYO. IOT
|
||||
instructions may include an octal numeric modifier or the modifier I:
|
||||
|
||||
iot modifier
|
||||
|
||||
The simulator does not check the legality of skip, operate, or IOT
|
||||
combinations.
|
||||
|
||||
Finally, the LAW instruction has the format
|
||||
|
||||
LAW {I} immediate
|
||||
|
||||
where immediate is in the range 0 to 07777.
|
||||
|
||||
2.4 Character Sets
|
||||
|
||||
The PDP-1's console was a Frieden Flexowriter; its character encoding
|
||||
was known as FIODEC. The PDP-1's line printer used a modified Hollerith
|
||||
character set. The following table provides equivalences between ASCII
|
||||
characters and the PDP-1's I/O devices. In the console table, UC stands
|
||||
for upper case.
|
||||
|
||||
PDP-1 PDP-1
|
||||
ASCII console line printer
|
||||
|
||||
000 - 007 none none
|
||||
bs 075 none
|
||||
tab 036 none
|
||||
012 - 014 none none
|
||||
cr 077 none
|
||||
016 - 037 none none
|
||||
space 000 000
|
||||
! {OR} UC+005 none
|
||||
" UC+001 none
|
||||
# {IMPLIES} UC+004 none
|
||||
$ none none
|
||||
% none none
|
||||
& {AND} UC+006 none
|
||||
' UC+002 none
|
||||
( 057 057
|
||||
) 055 055
|
||||
* {TIMES} UC+073 072
|
||||
+ UC+054 074
|
||||
, 033 033
|
||||
- 054 054
|
||||
. 073 073
|
||||
/ 021 021
|
||||
0 020 020
|
||||
1 001 001
|
||||
2 002 002
|
||||
3 003 003
|
||||
4 004 004
|
||||
5 005 005
|
||||
6 006 006
|
||||
7 007 007
|
||||
8 010 010
|
||||
9 011 011
|
||||
: none none
|
||||
; none none
|
||||
< UC+007 034
|
||||
= UC+033 053
|
||||
> UC+010 034
|
||||
? UC+021 037
|
||||
@ {MID DOT} 040 {MID DOT} 040
|
||||
A UC+061 061
|
||||
B UC+062 062
|
||||
C UC+063 063
|
||||
D UC+064 064
|
||||
E UC+065 065
|
||||
F UC+066 066
|
||||
G UC+067 067
|
||||
H UC+070 070
|
||||
I UC+071 071
|
||||
J UC+041 041
|
||||
K UC+042 042
|
||||
L UC+043 043
|
||||
M UC+044 044
|
||||
N UC+045 045
|
||||
O UC+046 046
|
||||
P UC+047 047
|
||||
Q UC+050 050
|
||||
R UC+051 051
|
||||
S UC+022 022
|
||||
T UC+023 023
|
||||
U UC+024 024
|
||||
V UC+025 025
|
||||
W UC+026 026
|
||||
X UC+027 027
|
||||
Y UC+030 030
|
||||
Z UC+031 031
|
||||
[ UC+057 none
|
||||
\ {OVERLINE} 056 {OVERLINE} 056
|
||||
] UC+055 none
|
||||
^ {UP ARROW} UC+011 {UP ARROW} 035
|
||||
_ UC+040 UC+040
|
||||
` {RT ARROW} UC+020 036
|
||||
a 061 none
|
||||
b 062 none
|
||||
c 063 none
|
||||
d 064 none
|
||||
e 065 none
|
||||
f 066 none
|
||||
g 067 none
|
||||
h 070 none
|
||||
i 071 none
|
||||
j 041 none
|
||||
k 042 none
|
||||
l 043 none
|
||||
m 044 none
|
||||
n 045 none
|
||||
o 046 none
|
||||
p 047 none
|
||||
q 050 none
|
||||
r 051 none
|
||||
s 022 none
|
||||
t 023 none
|
||||
u 024 none
|
||||
v 025 none
|
||||
w 026 none
|
||||
x 027 none
|
||||
y 030 none
|
||||
z 031 none
|
||||
{ none none
|
||||
| UC+056 076
|
||||
} none none
|
||||
~ UC+003 013
|
||||
del 075 none
|
||||
164
PDP1/pdp1_lp.c
Normal file
164
PDP1/pdp1_lp.c
Normal file
@@ -0,0 +1,164 @@
|
||||
/* pdp1_lp.c: PDP-1 line printer simulator
|
||||
|
||||
Copyright (c) 1993-2001, Robert M. Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of Robert M Supnik shall not
|
||||
be used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
lpt Type 62 line printer for the PDP-1
|
||||
|
||||
13-Apr-01 RMS Revised for register arrays
|
||||
*/
|
||||
|
||||
#include "pdp1_defs.h"
|
||||
#define BPTR_MAX 40 /* pointer max */
|
||||
#define LPT_BSIZE (BPTR_MAX * 3) /* line size */
|
||||
#define BPTR_MASK 077 /* buf ptr mask */
|
||||
extern int32 ioc, sbs, iosta;
|
||||
int32 lpt_rpls = 0, lpt_iot = 0, lpt_stopioe = 0, bptr = 0;
|
||||
char lpt_buf[LPT_BSIZE + 1] = { 0 };
|
||||
t_stat lpt_svc (UNIT *uptr);
|
||||
t_stat lpt_reset (DEVICE *dptr);
|
||||
|
||||
/* LPT data structures
|
||||
|
||||
lpt_dev LPT device descriptor
|
||||
lpt_unit LPT unit
|
||||
lpt_reg LPT register list
|
||||
*/
|
||||
|
||||
UNIT lpt_unit = {
|
||||
UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
|
||||
|
||||
REG lpt_reg[] = {
|
||||
{ ORDATA (BUF, lpt_unit.buf, 8) },
|
||||
{ FLDATA (PNT, iosta, IOS_V_PNT) },
|
||||
{ FLDATA (SPC, iosta, IOS_V_SPC) },
|
||||
{ FLDATA (RPLS, lpt_rpls, 0) },
|
||||
{ DRDATA (BPTR, bptr, 6) },
|
||||
{ ORDATA (LPT_STATE, lpt_iot, 6), REG_HRO },
|
||||
{ DRDATA (POS, lpt_unit.pos, 31), PV_LEFT },
|
||||
{ DRDATA (TIME, lpt_unit.wait, 24), PV_LEFT },
|
||||
{ FLDATA (STOP_IOE, lpt_stopioe, 0) },
|
||||
{ BRDATA (LBUF, lpt_buf, 8, 8, LPT_BSIZE) },
|
||||
{ NULL } };
|
||||
|
||||
DEVICE lpt_dev = {
|
||||
"LPT", &lpt_unit, lpt_reg, NULL,
|
||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &lpt_reset,
|
||||
NULL, NULL, NULL };
|
||||
|
||||
/* Line printer IOT routine */
|
||||
|
||||
int32 lpt (int32 inst, int32 dev, int32 data)
|
||||
{
|
||||
int32 i;
|
||||
|
||||
static const unsigned char lpt_trans[64] = {
|
||||
' ','1','2','3','4','5','6','7','8','9','\'','~','#','V','^','<',
|
||||
'0','/','S','T','U','V','W','X','Y','Z','"',',','>','^','-','?',
|
||||
'@','J','K','L','M','N','O','P','Q','R','$','=','-',')','-','(',
|
||||
'_','A','B','C','D','E','F','G','H','I','*','.','+',']','|','[' };
|
||||
|
||||
if ((inst & 0700) == 0100) { /* fill buf */
|
||||
if (bptr < BPTR_MAX) { /* limit test ptr */
|
||||
i = bptr * 3; /* cvt to chr ptr */
|
||||
lpt_buf[i++] = lpt_trans[(data >> 12) & 077];
|
||||
lpt_buf[i++] = lpt_trans[(data >> 6) & 077];
|
||||
lpt_buf[i++] = lpt_trans[data & 077]; }
|
||||
bptr = (bptr + 1) & BPTR_MASK;
|
||||
return data; }
|
||||
lpt_rpls = 0;
|
||||
if ((inst & 0700) == 0200) { /* space */
|
||||
iosta = iosta & ~IOS_SPC; /* space, clear flag */
|
||||
lpt_iot = (inst >> 6) & 077; } /* state = space n */
|
||||
else { iosta = iosta & ~IOS_PNT; /* clear flag */
|
||||
lpt_iot = 0; } /* state = print */
|
||||
if (GEN_CPLS (inst)) { /* comp pulse? */
|
||||
ioc = 0; /* clear flop */
|
||||
lpt_rpls = 1; } /* request completion */
|
||||
sim_activate (&lpt_unit, lpt_unit.wait); /* activate */
|
||||
return data;
|
||||
}
|
||||
|
||||
/* Unit service, printer is in one of three states
|
||||
|
||||
lpt_iot = 000 write buffer to file, set state to
|
||||
lpt_iot = 010 write cr, then write buffer to file
|
||||
lpt_iot = 02x space command x, then set state to 0
|
||||
*/
|
||||
|
||||
t_stat lpt_svc (UNIT *uptr)
|
||||
{
|
||||
int32 i;
|
||||
static const char *lpt_cc[] = {
|
||||
"\n",
|
||||
"\n\n",
|
||||
"\n\n\n",
|
||||
"\n\n\n\n\n\n",
|
||||
"\n\n\n\n\n\n\n\n\n\n\n",
|
||||
"\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n",
|
||||
"\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n",
|
||||
"\f" };
|
||||
|
||||
sbs = sbs | SB_RQ; /* req seq break */
|
||||
ioc = ioc | lpt_rpls; /* restart */
|
||||
if (lpt_iot & 020) { /* space? */
|
||||
iosta = iosta | IOS_SPC; /* set flag */
|
||||
if ((lpt_unit.flags & UNIT_ATT) == 0) /* attached? */
|
||||
return IORETURN (lpt_stopioe, SCPE_UNATT);
|
||||
fputs (lpt_cc[lpt_iot & 07], lpt_unit.fileref); /* print cctl */
|
||||
if (ferror (lpt_unit.fileref)) { /* error? */
|
||||
perror ("LPT I/O error");
|
||||
clearerr (lpt_unit.fileref);
|
||||
return SCPE_IOERR; }
|
||||
lpt_iot = 0; } /* clear state */
|
||||
else { iosta = iosta | IOS_PNT; /* print */
|
||||
if ((lpt_unit.flags & UNIT_ATT) == 0) /* attached? */
|
||||
return IORETURN (lpt_stopioe, SCPE_UNATT);
|
||||
if (lpt_iot & 010) fputc ('\r', lpt_unit.fileref);
|
||||
fputs (lpt_buf, lpt_unit.fileref); /* print buffer */
|
||||
if (ferror (lpt_unit.fileref)) { /* test error */
|
||||
perror ("LPT I/O error");
|
||||
clearerr (lpt_unit.fileref);
|
||||
return SCPE_IOERR; }
|
||||
bptr = 0;
|
||||
for (i = 0; i <= LPT_BSIZE; i++) lpt_buf[i] = 0; /* clear buffer */
|
||||
lpt_iot = 010; } /* set state */
|
||||
lpt_unit.pos = ftell (lpt_unit.fileref); /* update position */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Reset routine */
|
||||
|
||||
t_stat lpt_reset (DEVICE *dptr)
|
||||
{
|
||||
int32 i;
|
||||
|
||||
iosta = iosta & ~(IOS_PNT | IOS_SPC); /* clear flags */
|
||||
bptr = 0; /* clear buffer ptr */
|
||||
for (i = 0; i <= LPT_BSIZE; i++) lpt_buf[i] = 0; /* clear buffer */
|
||||
lpt_iot = 0; /* clear state */
|
||||
lpt_rpls = 0;
|
||||
sim_cancel (&lpt_unit); /* deactivate unit */
|
||||
return SCPE_OK;
|
||||
}
|
||||
418
PDP1/pdp1_stddev.c
Normal file
418
PDP1/pdp1_stddev.c
Normal file
@@ -0,0 +1,418 @@
|
||||
/* pdp1_stddev.c: PDP-1 standard devices
|
||||
|
||||
Copyright (c) 1993-2001, Robert M. Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of Robert M Supnik shall not
|
||||
be used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
ptr paper tape reader
|
||||
ptp paper tape punch
|
||||
tti keyboard
|
||||
tto teleprinter
|
||||
|
||||
29-Nov-01 RMS Added read only unit support
|
||||
07-Sep-01 RMS Moved function prototypes
|
||||
10-Jun-01 RMS Fixed comment
|
||||
30-Oct-00 RMS Standardized device naming
|
||||
*/
|
||||
|
||||
#include "pdp1_defs.h"
|
||||
|
||||
#define FIODEC_UC 074
|
||||
#define FIODEC_LC 072
|
||||
#define UC 0100 /* upper case */
|
||||
#define BOTH 0200 /* both cases */
|
||||
#define CW 0400 /* char waiting */
|
||||
#define TT_WIDTH 077
|
||||
extern int32 sbs, ioc, iosta, PF, IO, PC;
|
||||
extern int32 M[];
|
||||
int32 ptr_rpls = 0, ptr_stopioe = 0, ptr_state = 0;
|
||||
int32 ptp_rpls = 0, ptp_stopioe = 0;
|
||||
int32 tti_state = 0;
|
||||
int32 tto_rpls = 0, tto_state = 0;
|
||||
t_stat ptr_svc (UNIT *uptr);
|
||||
t_stat ptp_svc (UNIT *uptr);
|
||||
t_stat tti_svc (UNIT *uptr);
|
||||
t_stat tto_svc (UNIT *uptr);
|
||||
t_stat ptr_reset (DEVICE *dptr);
|
||||
t_stat ptp_reset (DEVICE *dptr);
|
||||
t_stat tti_reset (DEVICE *dptr);
|
||||
t_stat tto_reset (DEVICE *dptr);
|
||||
t_stat ptr_boot (int32 unitno);
|
||||
|
||||
/* Character translation tables */
|
||||
|
||||
int32 fiodec_to_ascii[128] = {
|
||||
' ', '1', '2', '3', '4', '5', '6', '7', /* lower case */
|
||||
'8', '9', 0, 0, 0, 0, 0, 0,
|
||||
'0', '/', 's', 't', 'u', 'v', 'w', 'x',
|
||||
'y', 'z', 0, ',', 0, 0, '\t', 0,
|
||||
'@', 'j', 'k', 'l', 'm', 'n', 'o', 'p',
|
||||
'q', 'r', 0, 0, '-', ')', '\\', '(',
|
||||
0, 'a', 'b', 'c', 'd', 'e', 'f', 'g',
|
||||
'h', 'i', '{', '.', '}', '\b', 0, '\r',
|
||||
' ', '"', '\'', '~', '#', '!', '&', '<', /* upper case */
|
||||
'>', '^', 0, 0, 0, 0, 0, 0,
|
||||
'`', '?', 'S', 'T', 'U', 'V', 'W', 'X',
|
||||
'Y', 'Z', 0, '=', 0, 0, '\t', 0,
|
||||
'_', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
|
||||
'Q', 'R', 0, 0, '+', ']', '|', '[',
|
||||
0, 'A', 'B', 'C', 'D', 'E', 'F', 'G',
|
||||
'H', 'I', '{', '*', '}', '\b', 0, '\r' };
|
||||
|
||||
int32 ascii_to_fiodec[128] = {
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
BOTH+075, BOTH+036, 0, 0, 0, BOTH+077, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
BOTH+0, UC+005, UC+001, UC+004, 0, 0, UC+006, UC+002,
|
||||
057, 055, UC+073, UC+054, 033, 054, 073, 021,
|
||||
020, 001, 002, 003, 004, 005, 006, 007,
|
||||
010, 011, 0, 0, UC+007, UC+033, UC+010, UC+021,
|
||||
040, UC+061, UC+062, UC+063, UC+064, UC+065, UC+066, UC+067,
|
||||
UC+070, UC+071, UC+041, UC+042, UC+043, UC+044, UC+045, UC+046,
|
||||
UC+047, UC+050, UC+051, UC+022, UC+023, UC+024, UC+025, UC+026,
|
||||
UC+027, UC+030, UC+031, UC+057, 056, UC+055, UC+011, UC+040,
|
||||
UC+020, 061, 062, 063, 064, 065, 066, 067,
|
||||
070, 071, 041, 042, 043, 044, 045, 046,
|
||||
047, 050, 051, 022, 023, 024, 025, 026,
|
||||
027, 030, 031, 0, UC+056, 0, UC+003, BOTH+075 };
|
||||
|
||||
/* PTR data structures
|
||||
|
||||
ptr_dev PTR device descriptor
|
||||
ptr_unit PTR unit
|
||||
ptr_reg PTR register list
|
||||
*/
|
||||
|
||||
UNIT ptr_unit = {
|
||||
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
|
||||
SERIAL_IN_WAIT };
|
||||
|
||||
REG ptr_reg[] = {
|
||||
{ ORDATA (BUF, ptr_unit.buf, 18) },
|
||||
{ FLDATA (DONE, iosta, IOS_V_PTR) },
|
||||
{ FLDATA (RPLS, ptr_rpls, 0) },
|
||||
{ ORDATA (STATE, ptr_state, 5), REG_HRO },
|
||||
{ DRDATA (POS, ptr_unit.pos, 31), PV_LEFT },
|
||||
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
|
||||
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
|
||||
{ NULL } };
|
||||
|
||||
DEVICE ptr_dev = {
|
||||
"PTR", &ptr_unit, ptr_reg, NULL,
|
||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &ptr_reset,
|
||||
&ptr_boot, NULL, NULL };
|
||||
|
||||
/* PTP data structures
|
||||
|
||||
ptp_dev PTP device descriptor
|
||||
ptp_unit PTP unit
|
||||
ptp_reg PTP register list
|
||||
*/
|
||||
|
||||
UNIT ptp_unit = {
|
||||
UDATA (&ptp_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
|
||||
|
||||
REG ptp_reg[] = {
|
||||
{ ORDATA (BUF, ptp_unit.buf, 8) },
|
||||
{ FLDATA (DONE, iosta, IOS_V_PTP) },
|
||||
{ FLDATA (RPLS, ptp_rpls, 0) },
|
||||
{ DRDATA (POS, ptp_unit.pos, 31), PV_LEFT },
|
||||
{ DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT },
|
||||
{ FLDATA (STOP_IOE, ptp_stopioe, 0) },
|
||||
{ NULL } };
|
||||
|
||||
DEVICE ptp_dev = {
|
||||
"PTP", &ptp_unit, ptp_reg, NULL,
|
||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &ptp_reset,
|
||||
NULL, NULL, NULL };
|
||||
|
||||
/* TTI data structures
|
||||
|
||||
tti_dev TTI device descriptor
|
||||
tti_unit TTI unit
|
||||
tti_reg TTI register list
|
||||
*/
|
||||
|
||||
UNIT tti_unit = { UDATA (&tti_svc, 0, 0), KBD_POLL_WAIT };
|
||||
|
||||
REG tti_reg[] = {
|
||||
{ ORDATA (BUF, tti_unit.buf, 6) },
|
||||
{ FLDATA (DONE, iosta, IOS_V_TTI) },
|
||||
{ ORDATA (STATE, tti_state, 10), REG_HRO },
|
||||
{ DRDATA (POS, tti_unit.pos, 31), PV_LEFT },
|
||||
{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
|
||||
{ NULL } };
|
||||
|
||||
DEVICE tti_dev = {
|
||||
"TTI", &tti_unit, tti_reg, NULL,
|
||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &tti_reset,
|
||||
NULL, NULL, NULL };
|
||||
|
||||
/* TTO data structures
|
||||
|
||||
tto_dev TTO device descriptor
|
||||
tto_unit TTO unit
|
||||
tto_reg TTO register list
|
||||
*/
|
||||
|
||||
UNIT tto_unit = { UDATA (&tto_svc, 0, 0), SERIAL_OUT_WAIT };
|
||||
|
||||
REG tto_reg[] = {
|
||||
{ ORDATA (BUF, tto_unit.buf, 6) },
|
||||
{ FLDATA (DONE, iosta, IOS_V_TTO) },
|
||||
{ FLDATA (RPLS, tto_rpls, 0) },
|
||||
{ ORDATA (STATE, tto_state, 10), REG_HRO },
|
||||
{ DRDATA (POS, tto_unit.pos, 31), PV_LEFT },
|
||||
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
|
||||
{ NULL } };
|
||||
|
||||
DEVICE tto_dev = {
|
||||
"TTO", &tto_unit, tto_reg, NULL,
|
||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &tto_reset,
|
||||
NULL, NULL, NULL };
|
||||
|
||||
/* Paper tape reader: IOT routine */
|
||||
|
||||
int32 ptr (int32 inst, int32 dev, int32 data)
|
||||
{
|
||||
iosta = iosta & ~IOS_PTR; /* clear flag */
|
||||
if (dev == 0030) return ptr_unit.buf; /* RRB */
|
||||
ptr_state = (dev == 0002)? 18: 0; /* mode = bin/alp */
|
||||
ptr_rpls = 0;
|
||||
ptr_unit.buf = 0; /* clear buffer */
|
||||
sim_activate (&ptr_unit, ptr_unit.wait);
|
||||
if (GEN_CPLS (inst)) { /* comp pulse? */
|
||||
ioc = 0;
|
||||
ptr_rpls = 1; }
|
||||
return data;
|
||||
}
|
||||
|
||||
/* Unit service */
|
||||
|
||||
t_stat ptr_svc (UNIT *uptr)
|
||||
{
|
||||
int32 temp;
|
||||
|
||||
if ((ptr_unit.flags & UNIT_ATT) == 0) /* attached? */
|
||||
return IORETURN (ptr_stopioe, SCPE_UNATT);
|
||||
if ((temp = getc (ptr_unit.fileref)) == EOF) { /* end of file? */
|
||||
if (feof (ptr_unit.fileref)) {
|
||||
if (ptr_stopioe) printf ("PTR end of file\n");
|
||||
else return SCPE_OK; }
|
||||
else perror ("PTR I/O error");
|
||||
clearerr (ptr_unit.fileref);
|
||||
return SCPE_IOERR; }
|
||||
ptr_unit.pos = ptr_unit.pos + 1;
|
||||
if (ptr_state == 0) ptr_unit.buf = temp & 0377; /* alpha */
|
||||
else if (temp & 0200) { /* binary */
|
||||
ptr_state = ptr_state - 6;
|
||||
ptr_unit.buf = ptr_unit.buf | ((temp & 077) << ptr_state); }
|
||||
if (ptr_state == 0) { /* done? */
|
||||
if (ptr_rpls) IO = ptr_unit.buf; /* restart? fill IO */
|
||||
iosta = iosta | IOS_PTR; /* set flag */
|
||||
sbs = sbs | SB_RQ; /* req seq break */
|
||||
ioc = ioc | ptr_rpls; } /* restart */
|
||||
else sim_activate (&ptr_unit, ptr_unit.wait); /* get next char */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Reset routine */
|
||||
|
||||
t_stat ptr_reset (DEVICE *dptr)
|
||||
{
|
||||
ptr_state = 0; /* clear state */
|
||||
ptr_unit.buf = 0;
|
||||
ptr_rpls = 0;
|
||||
iosta = iosta & ~IOS_PTR; /* clear flag */
|
||||
sim_cancel (&ptr_unit); /* deactivate unit */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Bootstrap routine */
|
||||
|
||||
#define BOOT_START 07772
|
||||
#define BOOT_LEN (sizeof (boot_rom) / sizeof (int))
|
||||
|
||||
static const int32 boot_rom[] = {
|
||||
0730002, /* r, rpb + wait */
|
||||
0327776, /* dio x */
|
||||
0107776, /* xct x */
|
||||
0730002, /* rpb + wait */
|
||||
0760400, /* x, halt */
|
||||
0607772 /* jmp r */
|
||||
};
|
||||
|
||||
t_stat ptr_boot (int32 unitno)
|
||||
{
|
||||
int32 i;
|
||||
|
||||
for (i = 0; i < BOOT_LEN; i++) M[BOOT_START + i] = boot_rom[i];
|
||||
PC = BOOT_START;
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Paper tape punch: IOT routine */
|
||||
|
||||
int32 ptp (int32 inst, int32 dev, int32 data)
|
||||
{
|
||||
iosta = iosta & ~IOS_PTP; /* clear flag */
|
||||
ptp_rpls = 0;
|
||||
ptp_unit.buf = (dev == 0006)? ((data >> 12) | 0200): (data & 0377);
|
||||
sim_activate (&ptp_unit, ptp_unit.wait); /* start unit */
|
||||
if (GEN_CPLS (inst)) { /* comp pulse? */
|
||||
ioc = 0;
|
||||
ptp_rpls = 1; }
|
||||
return data;
|
||||
}
|
||||
|
||||
/* Unit service */
|
||||
|
||||
t_stat ptp_svc (UNIT *uptr)
|
||||
{
|
||||
iosta = iosta | IOS_PTP; /* set flag */
|
||||
sbs = sbs | SB_RQ; /* req seq break */
|
||||
ioc = ioc | ptp_rpls; /* process restart */
|
||||
if ((ptp_unit.flags & UNIT_ATT) == 0) /* not attached? */
|
||||
return IORETURN (ptp_stopioe, SCPE_UNATT);
|
||||
if (putc (ptp_unit.buf, ptp_unit.fileref) == EOF) { /* I/O error? */
|
||||
perror ("PTP I/O error");
|
||||
clearerr (ptp_unit.fileref);
|
||||
return SCPE_IOERR; }
|
||||
ptp_unit.pos = ptp_unit.pos + 1;
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Reset routine */
|
||||
|
||||
t_stat ptp_reset (DEVICE *dptr)
|
||||
{
|
||||
ptp_unit.buf = 0; /* clear state */
|
||||
ptp_rpls = 0;
|
||||
iosta = iosta & ~IOS_PTP; /* clear flag */
|
||||
sim_cancel (&ptp_unit); /* deactivate unit */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Terminal input: IOT routine */
|
||||
|
||||
int32 tti (int32 inst, int32 dev, int32 data)
|
||||
{
|
||||
iosta = iosta & ~IOS_TTI; /* clear flag */
|
||||
if (inst & (IO_WAIT | IO_CPLS)) /* wait or sync? */
|
||||
return (STOP_RSRV << IOT_V_REASON) | (tti_unit.buf & 077);
|
||||
return tti_unit.buf & 077;
|
||||
}
|
||||
|
||||
/* Unit service */
|
||||
|
||||
t_stat tti_svc (UNIT *uptr)
|
||||
{
|
||||
int32 in, temp;
|
||||
|
||||
sim_activate (&tti_unit, tti_unit.wait); /* continue poll */
|
||||
if (tti_state & CW) { /* char waiting? */
|
||||
tti_unit.buf = tti_state & TT_WIDTH; /* return char */
|
||||
tti_state = tti_state & ~CW; } /* not waiting */
|
||||
else { if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp;
|
||||
temp = temp & 0177;
|
||||
if (temp == 0177) temp = '\b'; /* rubout? bs */
|
||||
sim_putchar (temp); /* echo */
|
||||
if (temp == '\r') sim_putchar ('\n'); /* cr? add nl */
|
||||
in = ascii_to_fiodec[temp]; /* translate char */
|
||||
if (in == 0) return SCPE_OK; /* no xlation? */
|
||||
if ((in & BOTH) || ((in & UC) == (tti_state & UC)))
|
||||
tti_unit.buf = in & TT_WIDTH;
|
||||
else { tti_unit.buf = (in & UC)? FIODEC_UC: FIODEC_LC;
|
||||
tti_state = in | CW; } } /* set 2nd waiting */
|
||||
iosta = iosta | IOS_TTI; /* set flag */
|
||||
sbs = sbs | SB_RQ; /* req seq break */
|
||||
PF = PF | 040; /* set prog flag 1 */
|
||||
tti_unit.pos = tti_unit.pos + 1;
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Reset routine */
|
||||
|
||||
t_stat tti_reset (DEVICE *dptr)
|
||||
{
|
||||
tti_unit.buf = 0; /* clear buffer */
|
||||
tti_state = 0; /* clear state */
|
||||
iosta = iosta & ~IOS_TTI; /* clear flag */
|
||||
sim_activate (&tti_unit, tti_unit.wait); /* activate unit */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Terminal output: IOT routine */
|
||||
|
||||
int32 tto (int32 inst, int32 dev, int32 data)
|
||||
{
|
||||
iosta = iosta & ~IOS_TTO; /* clear flag */
|
||||
tto_rpls = 0;
|
||||
tto_unit.buf = data & TT_WIDTH; /* load buffer */
|
||||
sim_activate (&tto_unit, tto_unit.wait); /* activate unit */
|
||||
if (GEN_CPLS (inst)) { /* comp pulse? */
|
||||
ioc = 0;
|
||||
tto_rpls = 1; }
|
||||
return data;
|
||||
}
|
||||
|
||||
/* Unit service */
|
||||
|
||||
t_stat tto_svc (UNIT *uptr)
|
||||
{
|
||||
int32 out;
|
||||
|
||||
iosta = iosta | IOS_TTO; /* set flag */
|
||||
sbs = sbs | SB_RQ; /* req seq break */
|
||||
ioc = ioc | tto_rpls; /* process restart */
|
||||
if (tto_unit.buf == FIODEC_UC) { /* upper case? */
|
||||
tto_state = UC;
|
||||
return SCPE_OK; }
|
||||
if (tto_unit.buf == FIODEC_LC) { /* lower case? */
|
||||
tto_state = 0;
|
||||
return SCPE_OK; }
|
||||
out = fiodec_to_ascii[tto_unit.buf | tto_state]; /* translate */
|
||||
if (out == 0) return SCPE_OK; /* no translation? */
|
||||
sim_putchar (out);
|
||||
tto_unit.pos = tto_unit.pos + 1;
|
||||
if (out == '\r') { /* cr? add lf */
|
||||
sim_putchar ('\n');
|
||||
tto_unit.pos = tto_unit.pos + 1; }
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Reset routine */
|
||||
|
||||
t_stat tto_reset (DEVICE *dptr)
|
||||
{
|
||||
tto_unit.buf = 0; /* clear buffer */
|
||||
tto_state = 0; /* clear state */
|
||||
tto_rpls = 0;
|
||||
iosta = iosta & ~IOS_TTO; /* clear flag */
|
||||
sim_cancel (&tto_unit); /* deactivate unit */
|
||||
return SCPE_OK;
|
||||
}
|
||||
448
PDP1/pdp1_sys.c
Normal file
448
PDP1/pdp1_sys.c
Normal file
@@ -0,0 +1,448 @@
|
||||
/* pdp1_sys.c: PDP-1 simulator interface
|
||||
|
||||
Copyright (c) 1993-2001, Robert M. Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of Robert M Supnik shall not
|
||||
be used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
17-Sep-01 RMS Removed multiconsole support
|
||||
13-Jul-01 RMS Fixed RIM loader format
|
||||
27-May-01 RMS Added multiconsole support
|
||||
14-Mar-01 RMS Revised load/dump interface (again)
|
||||
30-Oct-00 RMS Added support for examine to file
|
||||
27-Oct-98 RMS V2.4 load interface
|
||||
20-Oct-97 RMS Fixed endian-dependence in RIM loader
|
||||
(found by Michael Somos)
|
||||
*/
|
||||
|
||||
#include "pdp1_defs.h"
|
||||
#include <ctype.h>
|
||||
|
||||
extern DEVICE cpu_dev;
|
||||
extern DEVICE ptr_dev, ptp_dev;
|
||||
extern DEVICE tti_dev, tto_dev;
|
||||
extern DEVICE lpt_dev;
|
||||
extern UNIT cpu_unit;
|
||||
extern REG cpu_reg[];
|
||||
extern int32 M[];
|
||||
extern int32 PC;
|
||||
extern int32 ascii_to_fiodec[], fiodec_to_ascii[];
|
||||
extern int32 sc_map[];
|
||||
|
||||
/* SCP data structures and interface routines
|
||||
|
||||
sim_name simulator name string
|
||||
sim_PC pointer to saved PC register descriptor
|
||||
sim_emax number of words for examine
|
||||
sim_devices array of pointers to simulated devices
|
||||
sim_stop_messages array of pointers to stop messages
|
||||
sim_load binary loader
|
||||
*/
|
||||
|
||||
char sim_name[] = "PDP-1";
|
||||
|
||||
REG *sim_PC = &cpu_reg[0];
|
||||
|
||||
int32 sim_emax = 1;
|
||||
|
||||
DEVICE *sim_devices[] = { &cpu_dev,
|
||||
&ptr_dev, &ptp_dev, &tti_dev, &tto_dev,
|
||||
&lpt_dev, NULL };
|
||||
|
||||
const char *sim_stop_messages[] = {
|
||||
"Unknown error",
|
||||
"Undefined instruction",
|
||||
"HALT instruction",
|
||||
"Breakpoint",
|
||||
"Nested XCT's",
|
||||
"Nested indirect addresses",
|
||||
"Infinite wait state" };
|
||||
|
||||
/* Binary loader
|
||||
|
||||
At the moment, implements RIM loader format
|
||||
*/
|
||||
|
||||
int32 getword (FILE *fileref)
|
||||
{
|
||||
int32 i, tmp, word;
|
||||
|
||||
word = 0;
|
||||
for (i = 0; i < 3;) {
|
||||
if ((tmp = getc (fileref)) == EOF) return -1;
|
||||
if (tmp & 0200) {
|
||||
word = (word << 6) | (tmp & 077);
|
||||
i++; } }
|
||||
return word;
|
||||
}
|
||||
|
||||
t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
|
||||
{
|
||||
int32 origin, val;
|
||||
|
||||
if ((*cptr != 0) || (flag != 0)) return SCPE_ARG;
|
||||
for (;;) {
|
||||
if ((val = getword (fileref)) < 0) return SCPE_FMT;
|
||||
if (((val & 0770000) == 0320000) || /* DIO? */
|
||||
((val & 0770000) == 0240000)) { /* DAC? - incorrect */
|
||||
origin = val & 07777;
|
||||
if ((val = getword (fileref)) < 0) return SCPE_FMT;
|
||||
if (MEM_ADDR_OK (origin)) M[origin++] = val; }
|
||||
else if ((val & 0770000) == 0600000) { /* JMP? */
|
||||
PC = val & 007777;
|
||||
return SCPE_OK; } }
|
||||
return SCPE_FMT; /* error */
|
||||
}
|
||||
|
||||
/* Symbol tables */
|
||||
|
||||
#define I_V_FL 18 /* inst class */
|
||||
#define I_M_FL 07 /* class mask */
|
||||
#define I_V_NPN 0 /* no operand */
|
||||
#define I_V_IOT 1 /* IOT */
|
||||
#define I_V_LAW 2 /* LAW */
|
||||
#define I_V_MRF 3 /* memory reference */
|
||||
#define I_V_MRI 4 /* mem ref no ind */
|
||||
#define I_V_OPR 5 /* OPR */
|
||||
#define I_V_SKP 6 /* skip */
|
||||
#define I_V_SHF 7 /* shift */
|
||||
#define I_NPN (I_V_NPN << I_V_FL) /* no operand */
|
||||
#define I_IOT (I_V_IOT << I_V_FL) /* IOT */
|
||||
#define I_LAW (I_V_LAW << I_V_FL) /* LAW */
|
||||
#define I_MRF (I_V_MRF << I_V_FL) /* memory reference */
|
||||
#define I_MRI (I_V_MRI << I_V_FL) /* mem ref no ind */
|
||||
#define I_OPR (I_V_OPR << I_V_FL) /* OPR */
|
||||
#define I_SKP (I_V_SKP << I_V_FL) /* skip */
|
||||
#define I_SHF (I_V_SHF << I_V_FL) /* shift */
|
||||
|
||||
static const int32 masks[] = {
|
||||
0777777, 0763777, 0760000, 0760000,
|
||||
0770000, 0760017, 0760077, 0777000 };
|
||||
|
||||
static const char *opcode[] = {
|
||||
"AND", "IOR", "XOR", "XCT", /* mem refs */
|
||||
"LAC", "LIO", "DAC", "DAP",
|
||||
"DIP", "DIO", "DZM", "ADD",
|
||||
"SUB", "IDX", "ISP", "SAD",
|
||||
"SAS", "MUL", "DIV", "JMP", "JSP",
|
||||
|
||||
"CAL", "JDA", /* mem ref no ind */
|
||||
|
||||
"IOH", "RPA", "RPB", "RRB", /* I/O instructions */
|
||||
"PPA", "PPB", "TYO", "TYI",
|
||||
"LSM", "ESM", "CBS",
|
||||
"LEM", "EEM", "CKS",
|
||||
|
||||
"SKP", "SKP I", "CLO",
|
||||
"SFT", "LAW", "OPR",
|
||||
|
||||
"RAL", "RIL", "RCL", /* shifts */
|
||||
"SAL", "SIL", "SCL",
|
||||
"RAR", "RIR", "RCR",
|
||||
"SAR", "SIR", "SCR",
|
||||
|
||||
"SZF1", "SZF2", "SZF3", /* skips */
|
||||
"SZF4", "SZF5", "SZF6", "SZF7",
|
||||
"SZS1", "SZS1 SZF1", "SZS1 SZF2", "SZS1 SZ3",
|
||||
"SZS1 SZF4", "SZS1 SZF5", "SZS1 SZF6", "SZS1 SZF7",
|
||||
"SZS2", "SZS2 SZF1", "SZS2 SZF2", "SZS2 SZ3",
|
||||
"SZS2 SZF4", "SZS2 SZF5", "SZS2 SZF6", "SZS2 SZF7",
|
||||
"SZS3", "SZS3 SZF1", "SZS3 SZF2", "SZS3 SZ3",
|
||||
"SZS3 SZF4", "SZS3 SZF5", "SZS3 SZF6", "SZS3 SZF7",
|
||||
"SZS4", "SZS4 SZF1", "SZS4 SZF2", "SZS4 SZ3",
|
||||
"SZS4 SZF4", "SZS4 SZF5", "SZS4 SZF6", "SZS4 SZF7",
|
||||
"SZS5", "SZS5 SZF1", "SZS5 SZF2", "SZS5 SZ3",
|
||||
"SZS5 SZF4", "SZS5 SZF5", "SZS5 SZF6", "SZS5 SZF7",
|
||||
"SZS6", "SZS6 SZF1", "SZS6 SZF2", "SZS6 SZ3",
|
||||
"SZS6 SZF4", "SZS6 SZF5", "SZS6 SZF6", "SZS6 SZF7",
|
||||
"SZS7", "SZS7 SZF1", "SZS7 SZF2", "SZS7 SZ3",
|
||||
"SZS7 SZF4", "SZS7 SZF5", "SZS7 SZF6", "SZS7 SZF7",
|
||||
|
||||
"CLF1", "CLF2", "CLF3", /* operates */
|
||||
"CLF4", "CLF5", "CLF6", "CLF7",
|
||||
"STF1", "STF2", "STF3",
|
||||
"STF4", "STF5", "STF6", "STF7",
|
||||
|
||||
"SZA", "SPA", "SMA", /* encode only */
|
||||
"SZO", "SPI", "I",
|
||||
"LAP", "CLA", "HLT",
|
||||
"CMA", "LAT", "CLI",
|
||||
NULL, NULL, /* decode only */
|
||||
NULL };
|
||||
|
||||
static const int32 opc_val[] = {
|
||||
0020000+I_MRF, 0040000+I_MRF, 0060000+I_MRF, 0100000+I_MRF,
|
||||
0200000+I_MRF, 0220000+I_MRF, 0240000+I_MRF, 0260000+I_MRF,
|
||||
0300000+I_MRF, 0320000+I_MRF, 0340000+I_MRF, 0400000+I_MRF,
|
||||
0420000+I_MRF, 0440000+I_MRF, 0460000+I_MRF, 0500000+I_MRF,
|
||||
0520000+I_MRF, 0540000+I_MRF, 0560000+I_MRF, 0600000+I_MRF, 0620000+I_MRF,
|
||||
|
||||
0160000+I_MRI, 0170000+I_MRI,
|
||||
|
||||
0730000+I_NPN, 0720001+I_IOT, 0720002+I_IOT, 0720030+I_IOT,
|
||||
0720005+I_IOT, 0720006+I_IOT, 0720003+I_IOT, 0720004+I_IOT,
|
||||
0720054+I_NPN, 0720055+I_NPN, 0720056+I_NPN,
|
||||
0720074+I_NPN, 0724074+I_NPN, 0720033+I_NPN,
|
||||
|
||||
0640000+I_NPN, 0650000+I_NPN, 0651600+I_NPN,
|
||||
0660000+I_NPN, 0700000+I_LAW, 0760000+I_NPN,
|
||||
|
||||
0661000+I_SHF, 0662000+I_SHF, 0663000+I_SHF,
|
||||
0665000+I_SHF, 0666000+I_SHF, 0667000+I_SHF,
|
||||
0671000+I_SHF, 0672000+I_SHF, 0673000+I_SHF,
|
||||
0675000+I_SHF, 0676000+I_SHF, 0677000+I_SHF,
|
||||
|
||||
0640001+I_SKP, 0640002+I_SKP, 0640003+I_SKP,
|
||||
0640004+I_SKP, 0640005+I_SKP, 0640006+I_SKP, 0640007+I_SKP,
|
||||
0640010+I_SKP, 0640011+I_SKP, 0640012+I_SKP, 0640013+I_SKP,
|
||||
0640014+I_SKP, 0640015+I_SKP, 0640016+I_SKP, 0640017+I_SKP,
|
||||
0640020+I_SKP, 0640021+I_SKP, 0640022+I_SKP, 0640023+I_SKP,
|
||||
0640024+I_SKP, 0640025+I_SKP, 0640026+I_SKP, 0640027+I_SKP,
|
||||
0640030+I_SKP, 0640031+I_SKP, 0640032+I_SKP, 0640033+I_SKP,
|
||||
0640034+I_SKP, 0640035+I_SKP, 0640036+I_SKP, 0640037+I_SKP,
|
||||
0640040+I_SKP, 0640041+I_SKP, 0640042+I_SKP, 0640043+I_SKP,
|
||||
0640044+I_SKP, 0640045+I_SKP, 0640046+I_SKP, 0640047+I_SKP,
|
||||
0640050+I_SKP, 0640051+I_SKP, 0640052+I_SKP, 0640053+I_SKP,
|
||||
0640054+I_SKP, 0640055+I_SKP, 0640056+I_SKP, 0640057+I_SKP,
|
||||
0640060+I_SKP, 0640061+I_SKP, 0640062+I_SKP, 0640063+I_SKP,
|
||||
0640064+I_SKP, 0640065+I_SKP, 0640066+I_SKP, 0640067+I_SKP,
|
||||
0640070+I_SKP, 0640071+I_SKP, 0640072+I_SKP, 0640073+I_SKP,
|
||||
0640074+I_SKP, 0640075+I_SKP, 0640076+I_SKP, 0640077+I_SKP,
|
||||
|
||||
0760001+I_OPR, 0760002+I_OPR, 0760003+I_OPR,
|
||||
0760004+I_OPR, 0760005+I_OPR, 0760006+I_OPR, 0760007+I_OPR,
|
||||
0760011+I_OPR, 0760012+I_OPR, 0760013+I_OPR,
|
||||
0760014+I_OPR, 0760015+I_OPR, 0760016+I_OPR, 0760017+I_OPR,
|
||||
|
||||
0640100+I_SKP, 0640200+I_SKP, 0640400+I_SKP, /* encode only */
|
||||
0641000+I_SKP, 0642000+I_SKP, 0010000+I_SKP,
|
||||
0760100+I_OPR, 0760200+I_OPR, 0760400+I_OPR,
|
||||
0761000+I_OPR, 0762000+I_OPR, 0764000+I_OPR,
|
||||
|
||||
0640000+I_SKP, 0760000+I_OPR, /* decode only */
|
||||
-1 };
|
||||
|
||||
/* Operate or skip decode
|
||||
|
||||
Inputs:
|
||||
*of = output stream
|
||||
inst = mask bits
|
||||
class = instruction class code
|
||||
sp = space needed?
|
||||
Outputs:
|
||||
status = space needed?
|
||||
*/
|
||||
|
||||
int32 fprint_opr (FILE *of, int32 inst, int32 class, int32 sp)
|
||||
{
|
||||
int32 i, j;
|
||||
|
||||
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
||||
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
||||
if ((j == class) && (opc_val[i] & inst)) { /* same class? */
|
||||
inst = inst & ~opc_val[i]; /* mask bit set? */
|
||||
fprintf (of, (sp? " %s": "%s"), opcode[i]);
|
||||
sp = 1; } }
|
||||
return sp;
|
||||
}
|
||||
|
||||
/* Symbolic decode
|
||||
|
||||
Inputs:
|
||||
*of = output stream
|
||||
addr = current PC
|
||||
*val = pointer to values
|
||||
*uptr = pointer to unit
|
||||
sw = switches
|
||||
Outputs:
|
||||
return = status code
|
||||
*/
|
||||
|
||||
#define FMTASC(x) ((x) < 040)? "<%03o>": "%c", (x)
|
||||
#define SIXTOASC(x) fiodec_to_ascii[x]
|
||||
#define ASCTOSIX(x) (ascii_to_fiodec[x] & 077)
|
||||
|
||||
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
|
||||
UNIT *uptr, int32 sw)
|
||||
{
|
||||
int32 cflag, i, j, sp, inst, disp, ma;
|
||||
|
||||
inst = val[0];
|
||||
cflag = (uptr == NULL) || (uptr == &cpu_unit);
|
||||
if (sw & SWMASK ('A')) { /* ASCII? */
|
||||
if (inst > 0377) return SCPE_ARG;
|
||||
fprintf (of, FMTASC (inst & 0177));
|
||||
return SCPE_OK; }
|
||||
if (sw & SWMASK ('C')) { /* character? */
|
||||
fprintf (of, "%c", SIXTOASC ((inst >> 12) & 077));
|
||||
fprintf (of, "%c", SIXTOASC ((inst >> 6) & 077));
|
||||
fprintf (of, "%c", SIXTOASC (inst & 077));
|
||||
return SCPE_OK; }
|
||||
if (!(sw & SWMASK ('M'))) return SCPE_ARG;
|
||||
|
||||
/* Instruction decode */
|
||||
|
||||
disp = inst & 007777;
|
||||
ma = (addr & EPCMASK) | disp;
|
||||
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
||||
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
||||
if ((opc_val[i] & 0777777) == (inst & masks[j])) { /* match? */
|
||||
|
||||
switch (j) { /* case on class */
|
||||
case I_V_NPN: /* no operands */
|
||||
fprintf (of, "%s", opcode[i]); /* opcode */
|
||||
break;
|
||||
case I_V_IOT: /* IOT */
|
||||
disp = (inst - opc_val[i]) & 017777;
|
||||
if (disp == IA) fprintf (of, "%s I", opcode[i]);
|
||||
else if (disp) fprintf (of, "%s %-o", opcode[i], disp);
|
||||
else fprintf (of, "%s", opcode[i]);
|
||||
break;
|
||||
case I_V_LAW: /* LAW */
|
||||
cflag = 0; /* fall thru to MRF */
|
||||
case I_V_MRF: /* mem ref */
|
||||
fprintf (of, "%s%s%-o", opcode[i],
|
||||
((inst & IA)? " I ": " "), (cflag? ma: disp));
|
||||
break;
|
||||
case I_V_MRI: /* mem ref no ind */
|
||||
fprintf (of, "%s %-o", opcode[i], (cflag? ma: disp));
|
||||
break;
|
||||
case I_V_OPR: /* operates */
|
||||
sp = fprint_opr (of, inst & 007700, j, 0);
|
||||
if (opcode[i]) fprintf (of, (sp? " %s": "%s"), opcode[i]);
|
||||
break;
|
||||
case I_V_SKP: /* skips */
|
||||
sp = fprint_opr (of, inst & 007700, j, 0);
|
||||
if (opcode[i]) sp = fprintf (of, (sp? " %s": "%s"), opcode[i]);
|
||||
if (inst & IA) fprintf (of, sp? " I": "I");
|
||||
break;
|
||||
case I_V_SHF: /* shifts */
|
||||
fprintf (of, "%s %-d", opcode[i], sc_map[inst & 0777]);
|
||||
break; } /* end case */
|
||||
return SCPE_OK; } /* end if */
|
||||
} /* end for */
|
||||
return SCPE_ARG;
|
||||
}
|
||||
|
||||
/* Get 18b signed number
|
||||
|
||||
Inputs:
|
||||
*cptr = pointer to input string
|
||||
*sign = pointer to sign
|
||||
*status = pointer to error status
|
||||
Outputs:
|
||||
val = output value
|
||||
*/
|
||||
|
||||
t_value get_sint (char *cptr, int32 *sign, t_stat *status)
|
||||
{
|
||||
*sign = 1;
|
||||
if (*cptr == '+') {
|
||||
*sign = 0;
|
||||
cptr++; }
|
||||
else if (*cptr == '-') {
|
||||
*sign = -1;
|
||||
cptr++; }
|
||||
return get_uint (cptr, 8, 0777777, status);
|
||||
}
|
||||
|
||||
/* Symbolic input
|
||||
|
||||
Inputs:
|
||||
*cptr = pointer to input string
|
||||
addr = current PC
|
||||
uptr = pointer to unit
|
||||
*val = pointer to output values
|
||||
sw = switches
|
||||
Outputs:
|
||||
status = error status
|
||||
*/
|
||||
|
||||
t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
|
||||
{
|
||||
int32 cflag, d, i, j, k, sign;
|
||||
t_stat r;
|
||||
static int32 sc_enc[10] = { 0, 01, 03, 07, 017, 037, 077, 0177, 0377, 0777 };
|
||||
char gbuf[CBUFSIZE];
|
||||
|
||||
cflag = (uptr == NULL) || (uptr == &cpu_unit);
|
||||
while (isspace (*cptr)) cptr++;
|
||||
for (i = 1; (i < 3) && (cptr[i] != 0); i++)
|
||||
if (cptr[i] == 0) for (j = i + 1; j <= 3; j++) cptr[j] = 0;
|
||||
if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */
|
||||
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
||||
val[0] = (t_value) cptr[0];
|
||||
return SCPE_OK; }
|
||||
if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* sixbit string? */
|
||||
if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
|
||||
val[0] = (ASCTOSIX (cptr[0] & 077) << 12) |
|
||||
(ASCTOSIX (cptr[1] & 077) << 6) |
|
||||
ASCTOSIX (cptr[2] & 077);
|
||||
return SCPE_OK; }
|
||||
|
||||
/* Symbolic input, continued */
|
||||
|
||||
cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
|
||||
for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
||||
if (opcode[i] == NULL) return SCPE_ARG;
|
||||
val[0] = opc_val[i] & 0777777; /* get value */
|
||||
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
|
||||
|
||||
switch (j) { /* case on class */
|
||||
case I_V_LAW: /* LAW */
|
||||
cflag = 0; /* fall through */
|
||||
case I_V_MRF: case I_V_MRI: /* mem ref */
|
||||
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
|
||||
if ((j != I_V_MRI) && strcmp (gbuf, "I") == 0) { /* indirect? */
|
||||
val[0] = val[0] | IA;
|
||||
cptr = get_glyph (cptr, gbuf, 0); }
|
||||
d = get_uint (gbuf, 8, AMASK, &r);
|
||||
if (r != SCPE_OK) return SCPE_ARG;
|
||||
if (d <= DAMASK) val[0] = val[0] | d;
|
||||
else if (cflag && (((addr ^ d) & EPCMASK) == 0))
|
||||
val[0] = val[0] | (d & DAMASK);
|
||||
else return SCPE_ARG;
|
||||
break;
|
||||
case I_V_SHF: /* shift */
|
||||
cptr = get_glyph (cptr, gbuf, 0);
|
||||
d = get_uint (gbuf, 10, 9, &r);
|
||||
if (r != SCPE_OK) return SCPE_ARG;
|
||||
val[0] = val[0] | sc_enc[d];
|
||||
break;
|
||||
case I_V_NPN: case I_V_IOT: case I_V_OPR: case I_V_SKP:
|
||||
for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
|
||||
cptr = get_glyph (cptr, gbuf, 0)) {
|
||||
for (i = 0; (opcode[i] != NULL) &&
|
||||
(strcmp (opcode[i], gbuf) != 0) ; i++) ;
|
||||
if (opcode[i] != NULL) {
|
||||
k = opc_val[i] & 0777777;
|
||||
if ((k != IA) && (((k ^ val[0]) & 0760000) != 0))
|
||||
return SCPE_ARG;
|
||||
val[0] = val[0] | k; }
|
||||
else { d = get_sint (gbuf, &sign, &r);
|
||||
if (r != SCPE_OK) return SCPE_ARG;
|
||||
if (sign == 0) val[0] = val[0] + d;
|
||||
else if (sign < 0) val[0] = val[0] - d;
|
||||
else val[0] = val[0] | d; } }
|
||||
break; } /* end case */
|
||||
if (*cptr != 0) return SCPE_ARG; /* junk at end? */
|
||||
return SCPE_OK;
|
||||
}
|
||||
Reference in New Issue
Block a user