github.com/simh.simh
1
0
Fork 0
mirror of https://github.com/simh/simh.git synced 2026-04-25 19:51:25 +00:00
Code Releases Activity

PDP18B: Latest updates from Bob Supnik

Browse Source 
- Added unix v0 terminal support
- Added 3-cycle databreak set/show entries
- Revised for dynamically allocated memory
- Added support for -u modifier (UC15 and Unix v0)

These changes are to support the Unix v0 bringup and to implement a
"Unix input" mode on the console terminal.  In Unix mode, CR and LF are
swapped (so that a modern terminal can use 'enter' instead of CTRK-J to
create the newline Unix expects), escape is mapped to altmode (175),
upper and lower case are enabled and the parity bit is forced to 1.  This
most closely matches the characteristics of the KSR-37, but there is no
definitive evidence of the terminal that was actually used.
This commit is contained in:
Mark Pizzolato
2016-03-15 09:53:19 -07:00
parent 1f3c9550d5
commit 7251196f31
13 changed files with 126 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
PDP18B/pdp18b_cpu.c
View File

@@ -1,6 +1,6 @@
/* pdp18b_cpu.c: 18b PDP CPU simulator
Copyright (c) 1993-2015, Robert M Supnik
Copyright (c) 1993-2016, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,8 @@
cpu PDP-4/7/9/15 central processor
10-Mar-16 RMS Added 3-cycle databreak set/show routines
07-Mar-16 RMS Revised to allocate memory dynamically
28-Mar-15 RMS Revised to use sim_printf
28-Apr-07 RMS Removed clock initialization
26-Dec-06 RMS Fixed boundary test in KT15/XVM (Andrew Warkentin)
@@ -331,7 +333,7 @@ typedef struct {
#define ASW_DFLT 017720
#endif
int32 M[MAXMEMSIZE] = { 0 }; /* memory */
int32 *M = NULL; /* memory */
int32 LAC = 0; /* link'AC */
int32 MQ = 0; /* MQ */
int32 PC = 0; /* PC */
@@ -1551,7 +1553,7 @@ while (reason == 0) { /* loop until halted */
}
else if (pulse == 004) { /* ISA */
api_enb = (iot_data & SIGN)? 1: 0;
api_req = api_req | ((LAC >> 8) & 017);
api_req = api_req | ((LAC >> 8) & 017); /* swre levels only */
api_act = api_act | (LAC & 0377);
}
break;
@@ -1644,7 +1646,7 @@ while (reason == 0) { /* loop until halted */
}
else if (pulse == 004) { /* ISA */
api_enb = (iot_data & SIGN)? 1: 0;
api_req = api_req | ((LAC >> 8) & 017);
api_req = api_req | ((LAC >> 8) & 017); /* swre levels only */
api_act = api_act | (LAC & 0377);
}
else if (pulse == 021) /* ENB */
@@ -2097,6 +2099,10 @@ usmd = usmd_buf = usmd_defer = 0;
memm = memm_init;
nexm = prvn = trap_pending = 0;
emir_pending = rest_pending = 0;
if (M == NULL)
M = (int32 *) calloc (MEMSIZE, sizeof (int32));
if (M == NULL)
return SCPE_MEM;
pcq_r = find_reg ("PCQ", NULL, dptr);
if (pcq_r)
pcq_r->qptr = 0;
@@ -2272,6 +2278,31 @@ for (i = p = 0; (dptr = sim_devices[i]) != NULL; i++) { /* add devices */
return FALSE;
}
/* Set in memory 3-cycle databreak register */
t_stat set_3cyc_reg (UNIT *uptr, int32 val, char *cptr, void *desc)
{
t_stat r;
int32 newv;
if (cptr == NULL)
return SCPE_ARG;
newv = (int32) get_uint (cptr, 8, 0777777, &r);
if (r != SCPE_OK)
return SCPE_ARG;
M[val] = newv;
return SCPE_OK;
}
/* Show in-memory 3-cycle databreak register */
t_stat show_3cyc_reg (FILE *st, UNIT *uptr, int32 val, void *desc)
{
fprintf (st, "%s=", (char *) desc);
fprint_val (st, (t_value) M[val], 8, 18, PV_RZRO);
return SCPE_OK;
}
/* Set history */
t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc)