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Merge branch 'master' into Extra-VAXen

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This commit is contained in:
Mark Pizzolato
2011-12-18 19:53:19 -08:00
parent 71bc2e80c1 93f09d3253
commit 754c31b0ec
14 changed files with 295 additions and 133 deletions
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19
VAX/vax780_defs.h
View File

@@ -1,6 +1,6 @@
/* vax780_defs.h: VAX 780 model-specific definitions file
Copyright (c) 2004-2008, Robert M Supnik
Copyright (c) 2004-2011, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,8 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
26-Nov-11 MP Changed RQ amd TQ BR levels to BR4 to reflect real hardware
25-Nov-11 RMS Added VEC_QBUS definition
19-Nov-08 RMS Moved I/O support routines to I/O library
29-Apr-07 RMS Modified model-specific reserved operand check macros
to reflect 780 microcode patches (found by Naoki Hamada)
@@ -317,16 +319,16 @@ typedef struct {
#define INT_V_DZTX 1
#define INT_V_HK 2
#define INT_V_RL 3
#define INT_V_RQ 4
#define INT_V_TQ 5
#define INT_V_TS 6
#define INT_V_RY 7
#define INT_V_XU 8
#define INT_V_TS 4
#define INT_V_RY 5
#define INT_V_XU 6
#define INT_V_LPT 0 /* BR4 */
#define INT_V_PTR 1
#define INT_V_PTP 2
#define INT_V_CR 3
#define INT_V_RQ 4
#define INT_V_TQ 5
#define INT_DZRX (1u << INT_V_DZRX)
#define INT_DZTX (1u << INT_V_DZTX)
@@ -346,8 +348,8 @@ typedef struct {
#define IPL_DZTX (0x15 - IPL_HMIN)
#define IPL_HK (0x15 - IPL_HMIN)
#define IPL_RL (0x15 - IPL_HMIN)
#define IPL_RQ (0x15 - IPL_HMIN)
#define IPL_TQ (0x15 - IPL_HMIN)
#define IPL_RQ (0x14 - IPL_HMIN)
#define IPL_TQ (0x14 - IPL_HMIN)
#define IPL_TS (0x15 - IPL_HMIN)
#define IPL_RY (0x15 - IPL_HMIN)
#define IPL_XU (0x15 - IPL_HMIN)
@@ -358,6 +360,7 @@ typedef struct {
/* Device vectors */
#define VEC_QBUS 0
#define VEC_Q 0000
#define VEC_PTR 0070
#define VEC_PTP 0074

18
VAX/vax_cpu1.c
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@@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
25-Nov-11 RMS Added VEC_QBUS test in interrupt handler
23-Mar-11 RMS Revised idle design (from Mark Pizzolato)
28-May-08 RMS Inlined physical memory routines
29-Apr-07 RMS Separated base register access checks for 11/780
@@ -860,7 +861,7 @@ else {
else R[5] = MVC_FILL; /* fill, set state */
R[5] = R[5] | (cc << MVC_V_CC); /* pack with state */
PSL = PSL | PSL_FPD; /* set FPD */
}
}
/* At this point,
@@ -1099,7 +1100,7 @@ return (R[0]? 0: CC_Z);
/* Interrupt or exception
vec = SCB vector
vec = SCB vector (bit<0> = interrupt in Qbus mode)
cc = condition codes
ipl = new IPL if interrupt
ei = -1: severe exception
@@ -1118,8 +1119,8 @@ int32 acc;
in_ie = 1; /* flag int/exc */
CLR_TRAPS; /* clear traps */
newpc = ReadLP ((SCBB + vec) & PAMASK); /* read new PC */
if (ei < 0) /* severe? on istk */
newpc = ReadLP ((SCBB + vec) & (PAMASK & ~3)); /* read new PC */
if (ei == IE_SVE) /* severe? on istk */
newpc = newpc | 1;
if (newpc & 2) /* bad flags? */
ABORT (STOP_ILLVEC);
@@ -1136,8 +1137,13 @@ else {
SP = KSP; /* new stack */
}
}
if (ei > 0) /* if int, new IPL */
PSL = newpsl | (ipl << PSL_V_IPL);
if (ei == IE_INT) { /* if int, new IPL */
int32 newipl;
if (VEC_QBUS && ((vec & VEC_Q) != 0)) /* Qbus and Qbus vector? */
newipl = PSL_IPL17; /* force IPL 17 */
else newipl = ipl << PSL_V_IPL; /* otherwise, int IPL */
PSL = newpsl | newipl;
}
else PSL = newpsl | /* exc, old IPL/1F */
((newpc & 1)? PSL_IPL1F: (oldpsl & PSL_IPL)) | (oldcur << PSL_V_PRV);
if (DEBUG_PRI (cpu_dev, LOG_CPU_I))

1
VAX/vax_defs.h
View File

@@ -188,6 +188,7 @@
#define PSL_M_IPL 0x1F
#define PSL_IPL (PSL_M_IPL << PSL_V_IPL)
#define PSL_IPL1 (0x01 << PSL_V_IPL)
#define PSL_IPL17 (0x17 << PSL_V_IPL)
#define PSL_IPL1F (0x1F << PSL_V_IPL)
#define PSL_MBZ (0x30200000 | PSW_MBZ) /* must be zero */
#define PSW_MBZ 0xFF00 /* must be zero */

66
VAX/vaxmod_defs.h
View File

@@ -1,6 +1,6 @@
/* vaxmod_defs.h: VAX model-specific definitions file
Copyright (c) 1998-2007, Robert M Supnik
Copyright (c) 1998-2011, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,8 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
11-Dec-11 RMS Moved all Qbus devices to BR4; deleted RP definitions
25-Nov-11 RMS Added VEC_QBUS definition
29-Apr-07 RMS Separated checks for PxBR and SBR
17-May-06 RMS Added CR11/CD11 support
10-May-06 RMS Added NOP'd reserved operand checking macros
@@ -317,7 +319,8 @@ typedef struct {
#define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */
#define IOLN_PTP 004
/* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14
/* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
however, DEC Qbus controllers all interrupt on IPL 14
Within each IPL, priority is right to left
*/
@@ -329,38 +332,36 @@ typedef struct {
/* IPL 15 */
/* IPL 14 - devices through RY are IPL 15 on Unibus systems */
#define INT_V_RQ 0 /* RQDX3 */
#define INT_V_RL 1 /* RLV12/RL02 */
#define INT_V_DZRX 2 /* DZ11 */
#define INT_V_DZTX 3
#define INT_V_RP 4 /* RP,RM drives */
#define INT_V_TS 5 /* TS11/TSV05 */
#define INT_V_TQ 6 /* TMSCP */
#define INT_V_XQ 7 /* DEQNA/DELQA */
#define INT_V_RY 8 /* RXV21 */
#define INT_V_TS 4 /* TS11/TSV05 */
#define INT_V_TQ 5 /* TMSCP */
#define INT_V_XQ 6 /* DEQNA/DELQA */
#define INT_V_RY 7 /* RXV21 */
/* IPL 14 */
#define INT_V_TTI 0 /* console */
#define INT_V_TTO 1
#define INT_V_PTR 2 /* PC11 */
#define INT_V_PTP 3
#define INT_V_LPT 4 /* LP11 */
#define INT_V_CSI 5 /* SSC cons UART */
#define INT_V_CSO 6
#define INT_V_TMR0 7 /* SSC timers */
#define INT_V_TMR1 8
#define INT_V_VHRX 9 /* DHQ11 */
#define INT_V_VHTX 10
#define INT_V_QDSS 11 /* QDSS */
#define INT_V_CR 12
#define INT_V_TTI 8 /* console */
#define INT_V_TTO 9
#define INT_V_PTR 10 /* PC11 */
#define INT_V_PTP 11
#define INT_V_LPT 12 /* LP11 */
#define INT_V_CSI 13 /* SSC cons UART */
#define INT_V_CSO 14
#define INT_V_TMR0 15 /* SSC timers */
#define INT_V_TMR1 16
#define INT_V_VHRX 17 /* DHQ11 */
#define INT_V_VHTX 18
#define INT_V_QDSS 19 /* QDSS */
#define INT_V_CR 20
#define INT_CLK (1u << INT_V_CLK)
#define INT_RQ (1u << INT_V_RQ)
#define INT_RL (1u << INT_V_RL)
#define INT_DZRX (1u << INT_V_DZRX)
#define INT_DZTX (1u << INT_V_DZTX)
#define INT_RP (1u << INT_V_RP)
#define INT_TS (1u << INT_V_TS)
#define INT_TQ (1u << INT_V_TQ)
#define INT_XQ (1u << INT_V_XQ)
@@ -380,15 +381,14 @@ typedef struct {
#define INT_CR (1u << INT_V_CR)
#define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */
#define IPL_RQ (0x15 - IPL_HMIN)
#define IPL_RL (0x15 - IPL_HMIN)
#define IPL_DZRX (0x15 - IPL_HMIN)
#define IPL_DZTX (0x15 - IPL_HMIN)
#define IPL_RP (0x15 - IPL_HMIN)
#define IPL_TS (0x15 - IPL_HMIN)
#define IPL_TQ (0x15 - IPL_HMIN)
#define IPL_XQ (0x15 - IPL_HMIN)
#define IPL_RY (0x15 - IPL_HMIN)
#define IPL_RQ (0x14 - IPL_HMIN)
#define IPL_RL (0x14 - IPL_HMIN)
#define IPL_DZRX (0x14 - IPL_HMIN)
#define IPL_DZTX (0x14 - IPL_HMIN)
#define IPL_TS (0x14 - IPL_HMIN)
#define IPL_TQ (0x14 - IPL_HMIN)
#define IPL_XQ (0x14 - IPL_HMIN)
#define IPL_RY (0x14 - IPL_HMIN)
#define IPL_TTI (0x14 - IPL_HMIN)
#define IPL_TTO (0x14 - IPL_HMIN)
#define IPL_PTR (0x14 - IPL_HMIN)
@@ -410,6 +410,7 @@ typedef struct {
/* Device vectors */
#define VEC_QBUS 1 /* Qbus system */
#define VEC_Q 0x200 /* Qbus vector offset */
#define VEC_PTR (VEC_Q + 0070)
#define VEC_PTP (VEC_Q + 0074)
@@ -420,7 +421,6 @@ typedef struct {
#define VEC_LPT (VEC_Q + 0200)
#define VEC_TS (VEC_Q + 0224)
#define VEC_CR (VEC_Q + 0230)
#define VEC_RP (VEC_Q + 0254)
#define VEC_TQ (VEC_Q + 0260)
#define VEC_RX (VEC_Q + 0264)
#define VEC_RY (VEC_Q + 0264)