From 7bfe28957ea4927646da7557af0d5a136617ad46 Mon Sep 17 00:00:00 2001
From: Mark Pizzolato <mark@infocomm.com>
Date: Thu, 12 Jan 2023 08:55:16 -1000
Subject: [PATCH] SDS: Optimize frontpanel register access and add clock
 precalibration setup

---
 SDS/sds_cpu.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/SDS/sds_cpu.c b/SDS/sds_cpu.c
index d77cdbad..41fb57eb 100644
--- a/SDS/sds_cpu.c
+++ b/SDS/sds_cpu.c
@@ -1550,6 +1550,7 @@ sim_brk_dflt = SWMASK ('E');
 sim_brk_types = SWMASK ('E') | SWMASK ('M') | SWMASK ('N') | SWMASK ('U');
 sim_vm_is_subroutine_call = cpu_is_pc_a_subroutine_call;
 sim_vm_post = cpu_post_cmd;
+sim_set_stable_registers_state ();
 return SCPE_OK;
 }
 
@@ -1787,10 +1788,31 @@ if ((op == MIN && dat == 0) || (dat & SIGN))            /* set clk sync int */
 return SCPE_OK;
 }
 
+/*
+ * This sequence of instructions is a mix that hopefully
+ * represents a resonable instruction set that is a close 
+ * estimate to the normal calibrated result.
+ */
+
+static const char *sds_clock_precalibrate_commands[] = {
+    "100 NOP  100",
+    "101 NOP  200",
+    "102 NOP  300",
+    "103 NOP  400",
+    "104 BRU 100",
+    "105 EOM 02001",
+    "106 WIM 00077",
+    "107 DSC 0",
+    "110 HLT",
+    "111 BRU 100",
+    NULL};
+
+
 /* Clock reset */
 
 t_stat rtc_reset (DEVICE *dptr)
 {
+sim_clock_precalibrate_commands = sds_clock_precalibrate_commands;
 rtc_pie = 0;                                            /* disable pulse */
 rtc_unit.wait = sim_rtcn_init (rtc_unit.wait, TMR_RTC); /* initialize clock calibration */
 sim_activate (&rtc_unit, rtc_unit.wait);                /* activate unit */