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Code Releases Activity

Asynchronous Support

Browse Source 
scp.c, scp.h
	- added sim_uname (Unit Name) API to simplify places which might want to display it (mostly debug messages).
	- added support for clock co-scheduling
	- added debugging to trace event queue activities

    sim_defs.h
	- added support for clock co-scheduling
	- added support for sim_uname (Thread local storage macro)
	- added support for debugging to trace event queue activities
	- simplified debug code by using sim_uname
	- fixed support macro for sim_is_active when asynch timers are in use

   sim_rev.h
	- fixed nested comments

    sim_tmxr.c, sim_tmxr.h
	- added support for clock co-scheduling
	- simplified debug code by using sim_uname
	- added support for devices which poll for output on different units

    sim_timer.c, sim_timer.h
	- added support for clock co-scheduling
	- fixed asynchronous clock calibration to smooth out calibration adjustments
	- simplified debug code by using sim_uname
	- added ability (when running with asynchronous support) to explicitly disable or enable asynchronous timer support.
	- changed sim_timer_inst_per_sec to return a double value since the result is always used in a double expression and integer overflow could occur under strange timing conditions

    vax/vax_stddev.c
	- converted from simulator specific clock co-scheduling to generic clock co-scheduling.

    vax/vax_cpu.c
	- added EVENT and ACTIVATE debug flag (SET CPU DEBUG=EVENT;ACTIVATE) support

    pdp11/pdp11_dz.c
	- converted from simulator specific clock co-scheduling to generic clock co-scheduling.

    pdp11/pdp11_vh.c
	- converted from simulator specific clock co-scheduling to generic clock co-scheduling.

    pdp11/pdp11_xq.c
	- converted from simulator specific clock co-scheduling to generic clock co-scheduling.
This commit is contained in:
Mark Pizzolato
2012-11-12 15:33:35 -08:00
parent 030d790b4c
commit 7c7df669ad
14 changed files with 367 additions and 115 deletions
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4
PDP11/pdp11_dz.c
View File

@@ -334,7 +334,7 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
if (data & CSR_CLR) /* clr? reset */
dz_clear (dz, FALSE);
if (data & CSR_MSE) /* MSE? start poll */
sim_activate (&dz_unit, clk_cosched (tmxr_poll));
sim_clock_coschedule (&dz_unit, tmxr_poll);
else dz_csr[dz] &= ~(CSR_SA | CSR_RDONE | CSR_TRDY);
if ((data & CSR_RIE) == 0) /* RIE = 0? */
dz_clr_rxint (dz);
@@ -439,7 +439,7 @@ if (t) { /* any enabled? */
dz_update_rcvi (); /* upd rcv intr */
tmxr_poll_tx (&dz_desc); /* poll output */
dz_update_xmti (); /* upd xmt intr */
sim_activate (uptr, clk_cosched (tmxr_poll)); /* reactivate */
sim_clock_coschedule (uptr, tmxr_poll); /* reactivate */
}
return SCPE_OK;
}

22
PDP11/pdp11_vh.c
View File

@@ -343,7 +343,7 @@ static DIB vh_dib = {
static UNIT vh_unit[VH_MUXES] = {
{ UDATA (&vh_svc, UNIT_IDLE|UNIT_ATTABLE, 0) },
{ UDATA (&vh_timersvc, 0, 0) },
{ UDATA (&vh_timersvc, UNIT_IDLE, 0) },
};
static const REG vh_reg[] = {
@@ -841,9 +841,9 @@ static t_stat vh_wr ( int32 data,
if ((vh_unit[vh].flags & UNIT_MODEDHU) && (data & CSR_SKIP))
data &= ~CSR_MASTER_RESET;
if (vh == 0) /* Only start unit service on the first unit. Units are polled there */
sim_activate (&vh_unit[0], clk_cosched (tmxr_poll));
sim_clock_coschedule (&vh_unit[0], tmxr_poll);
vh_mcount[vh] = MS2SIMH (1200); /* 1.2 seconds */
sim_activate (&vh_unit[1], clk_cosched (tmxr_poll));
sim_clock_coschedule (&vh_unit[1], tmxr_poll);
}
if ((data & CSR_RXIE) == 0)
vh_clr_rxint (vh);
@@ -875,7 +875,7 @@ static t_stat vh_wr ( int32 data,
break;
if ((data == RESET_ABORT) && (vh_csr[vh] & CSR_MASTER_RESET)) {
vh_mcount[vh] = 1;
sim_activate (&vh_unit[1], clk_cosched (tmxr_poll));
sim_clock_coschedule (&vh_unit[1], tmxr_poll);
break;
}
if (vh_unit[vh].flags & UNIT_MODEDHU) {
@@ -920,7 +920,7 @@ static t_stat vh_wr ( int32 data,
case 2: /* LPR */
if ((data == RESET_ABORT) && (vh_csr[vh] & CSR_MASTER_RESET)) {
vh_mcount[vh] = 1;
sim_activate (&vh_unit[1], clk_cosched (tmxr_poll));
sim_clock_coschedule (&vh_unit[1], tmxr_poll);
break;
}
if (CSR_GETCHAN (vh_csr[vh]) >= VH_LINES)
@@ -947,7 +947,7 @@ static t_stat vh_wr ( int32 data,
case 3: /* STAT/FIFODATA */
if ((data == RESET_ABORT) && (vh_csr[vh] & CSR_MASTER_RESET)) {
vh_mcount[vh] = 1;
sim_activate (&vh_unit[1], clk_cosched (tmxr_poll));
sim_clock_coschedule (&vh_unit[1], tmxr_poll);
break;
}
if (CSR_GETCHAN (vh_csr[vh]) >= VH_LINES)
@@ -971,7 +971,7 @@ static t_stat vh_wr ( int32 data,
case 4: /* LNCTRL */
if ((data == RESET_ABORT) && (vh_csr[vh] & CSR_MASTER_RESET)) {
vh_mcount[vh] = 1;
sim_activate (&vh_unit[1], clk_cosched (tmxr_poll));
sim_clock_coschedule (&vh_unit[1], tmxr_poll);
break;
}
if (CSR_GETCHAN (vh_csr[vh]) >= VH_LINES)
@@ -1039,7 +1039,7 @@ static t_stat vh_wr ( int32 data,
case 5: /* TBUFFAD1 */
if ((data == RESET_ABORT) && (vh_csr[vh] & CSR_MASTER_RESET)) {
vh_mcount[vh] = 1;
sim_activate (&vh_unit[1], clk_cosched (tmxr_poll));
sim_clock_coschedule (&vh_unit[1], tmxr_poll);
break;
}
if (CSR_GETCHAN (vh_csr[vh]) >= VH_LINES)
@@ -1055,7 +1055,7 @@ static t_stat vh_wr ( int32 data,
case 6: /* TBUFFAD2 */
if ((data == RESET_ABORT) && (vh_csr[vh] & CSR_MASTER_RESET)) {
vh_mcount[vh] = 1;
sim_activate (&vh_unit[1], clk_cosched (tmxr_poll));
sim_clock_coschedule (&vh_unit[1], tmxr_poll);
break;
}
if (CSR_GETCHAN (vh_csr[vh]) >= VH_LINES)
@@ -1076,7 +1076,7 @@ static t_stat vh_wr ( int32 data,
case 7: /* TBUFFCT */
if ((data == RESET_ABORT) && (vh_csr[vh] & CSR_MASTER_RESET)) {
vh_mcount[vh] = 1;
sim_activate (&vh_unit[1], clk_cosched (tmxr_poll));
sim_clock_coschedule (&vh_unit[1], tmxr_poll);
break;
}
if (CSR_GETCHAN (vh_csr[vh]) >= VH_LINES)
@@ -1154,7 +1154,7 @@ static t_stat vh_timersvc ( UNIT *uptr )
}
}
if (again)
sim_activate (uptr, clk_cosched (tmxr_poll)); /* requeue ourselves */
sim_clock_coschedule (uptr, tmxr_poll); /* requeue ourselves */
return (SCPE_OK);
}

26
PDP11/pdp11_xq.c
View File

@@ -435,10 +435,10 @@ REG xqb_reg[] = {
};
MTAB xq_mod[] = {
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", NULL,
NULL, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", NULL,
NULL, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ MTAB_XTD | MTAB_VDV, 0, "MAC", "MAC=xx:xx:xx:xx:xx:xx",
&xq_setmac, &xq_showmac, NULL },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "ETH", "ETH",
@@ -2139,13 +2139,20 @@ void xq_start_receiver(CTLR* xq)
return;
/* start the read service timer or enable asynch reading as appropriate */
if (xq->var->must_poll)
sim_activate(xq->unit, (sim_idle_enab ? clk_cosched(tmxr_poll) : (tmr_poll*clk_tps)/xq->var->poll));
if (xq->var->must_poll) {
if (sim_idle_enab)
sim_clock_coschedule(xq->unit, tmxr_poll);
else
sim_activate(xq->unit, (tmr_poll*clk_tps)/xq->var->poll);
}
else
if ((xq->var->poll == 0) || (xq->var->mode == XQ_T_DELQA_PLUS))
eth_set_async(xq->var->etherface, xq->var->coalesce_latency_ticks);
else
sim_activate(xq->unit, (sim_idle_enab ? clk_cosched(tmxr_poll) : (tmr_poll*clk_tps)/xq->var->poll));
if (sim_idle_enab)
sim_clock_coschedule(xq->unit, tmxr_poll);
else
sim_activate(xq->unit, (tmr_poll*clk_tps)/xq->var->poll);
}
void xq_stop_receiver(CTLR* xq)
@@ -2520,7 +2527,10 @@ t_stat xq_svc(UNIT* uptr)
/* resubmit service timer */
if ((xq->var->must_poll) || (xq->var->poll && (xq->var->mode != XQ_T_DELQA_PLUS)))
sim_activate(uptr, (sim_idle_enab ? clk_cosched(tmxr_poll) : (tmr_poll*clk_tps)/xq->var->poll));
if (sim_idle_enab)
sim_clock_coschedule(uptr, tmxr_poll);
else
sim_activate(uptr, (tmr_poll*clk_tps)/xq->var->poll);
return SCPE_OK;
}