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PDP11: Fix bug in FUIV operation

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Problem reported by James Fehlinger
This commit is contained in:
Bob Supnik
2022-12-11 09:45:12 -10:00
committed by Mark Pizzolato
parent 921a2bbc4c
commit 7e39e112da
1 changed files with 15 additions and 8 deletions
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23
PDP11/pdp11_fp.c
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@@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik. in this Software without prior written authorization from Robert M Supnik.
10-Dec-22 RMS Fixed bug in FUIV operation (James Fehlinger)
21-Aug-22 RMS Restored MMR1 operation for 11/44, 11/45-70 (Walter Mueller) 21-Aug-22 RMS Restored MMR1 operation for 11/44, 11/45-70 (Walter Mueller)
24-Mar-15 RMS MMR1 does not track register changes (Johnny Billquist) 24-Mar-15 RMS MMR1 does not track register changes (Johnny Billquist)
20-Apr-13 RMS MMR1 does not track PC changes (Johnny Billquist) 20-Apr-13 RMS MMR1 does not track PC changes (Johnny Billquist)
@@ -87,12 +88,19 @@
accessed; if the operand is 32b or 64b, these accessed; if the operand is 32b or 64b, these
are the high order 16b of the operand. are the high order 16b of the operand.
The FP11 cannot update MMR1 on specifier changes, because the The J11 cannot update MMR1 on specifier changes, because the
quantity field is too narrow for +8 or -8. Instead, the simulator quantity field is too narrow for +8 or -8. However, the 11/44 and
records changes to be made and only commits them at instruction 11/70 can. So the simulator treats the two cases differently.
completion. Instructions that can overwrite a general register On the J11, the simulator records changes to be made and only
(STFPS, STST, STEXP, STCFi in mode 0) need not check for conflicts; commits them at instruction. On all other systems, changes occur
in mode 0, no general register changes occur in the specifier flow. as they happen and are recorded in MMR1. However, all systems
update the general registers on floating point exceptions. Thus,
when an exception occurs, the simulator in most cases cannot
abort but must let the instruction "run to completion." For
undefined variable and divide by zero, this means skipping
the actual processing logic.
*/ */
#include "pdp11_defs.h" #include "pdp11_defs.h"
@@ -538,7 +546,7 @@ switch ((IR >> 8) & 017) { /* decode IR<11:8> */
case 003: /* MODf */ case 003: /* MODf */
if (ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf)) { if (ReadFP (&fsrc, GeteaFP (dstspec, lenf), dstspec, lenf)) {
F_LOAD (qdouble, FR[ac], fac); F_LOAD (qdouble, FR[ac], fac);
newV = modfp11 (&fac, &fsrc, &modfrac); newV = modfp11 (&fac, &fsrc, &modfrac);
F_STORE (qdouble, fac, FR[ac | 1]); F_STORE (qdouble, fac, FR[ac | 1]);
F_STORE (qdouble, modfrac, FR[ac]); F_STORE (qdouble, modfrac, FR[ac]);
@@ -805,7 +813,6 @@ else {
if ((GET_SIGN (fptr->h) != 0) && /* undef variable? */ if ((GET_SIGN (fptr->h) != 0) && /* undef variable? */
(GET_EXP (fptr->h) == 0) && (GET_EXP (fptr->h) == 0) &&
!fpnotrap (FEC_UNDFV)) { /* trap enabled? */ !fpnotrap (FEC_UNDFV)) { /* trap enabled? */
fp_change = 0; /* J11, no reg changes */
return FALSE; /* NOP instruction */ return FALSE; /* NOP instruction */
} }
return TRUE; return TRUE;