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PDP-8: added register description and fixed typo in doc
This commit is contained in:
committed by
Mark Pizzolato
parent
57d49f832c
commit
81f68216ec
@@ -69,12 +69,12 @@ DIB tti_dib = { DEV_TTI, 1, { &tti } };
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UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_KSR, 0), SERIAL_IN_WAIT };
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REG tti_reg[] = {
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{ ORDATA (BUF, tti_unit.buf, 8) },
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{ FLDATA (DONE, dev_done, INT_V_TTI) },
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{ FLDATA (ENABLE, int_enable, INT_V_TTI) },
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{ FLDATA (INT, int_req, INT_V_TTI) },
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{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
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{ ORDATAD (BUF, tti_unit.buf, 8, "last data item processed") },
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{ FLDATAD (DONE, dev_done, INT_V_TTI, "device done flag") },
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{ FLDATAD (ENABLE, int_enable, INT_V_TTI, "interrupt enable flag") },
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{ FLDATAD (INT, int_req, INT_V_TTI, "interrupt pending flag") },
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{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
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{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval (if 0, the keyboard is polled synchronously with the clock)"), PV_LEFT },
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{ NULL }
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};
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@@ -107,12 +107,12 @@ DIB tto_dib = { DEV_TTO, 1, { &tto } };
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UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_KSR, 0), SERIAL_OUT_WAIT };
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REG tto_reg[] = {
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{ ORDATA (BUF, tto_unit.buf, 8) },
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{ FLDATA (DONE, dev_done, INT_V_TTO) },
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{ FLDATA (ENABLE, int_enable, INT_V_TTO) },
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{ FLDATA (INT, int_req, INT_V_TTO) },
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{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
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{ ORDATAD (BUF, tto_unit.buf, 8, "last date item processed") },
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{ FLDATAD (DONE, dev_done, INT_V_TTO, "device done flag") },
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{ FLDATAD (ENABLE, int_enable, INT_V_TTO, "interrupt enable flag") },
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{ FLDATAD (INT, int_req, INT_V_TTO, "interrupt pending flag") },
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{ DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT },
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{ DRDATAD (TIME, tto_unit.wait, 24, "time form I/O initiation to interrupt"), PV_LEFT },
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{ NULL }
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};
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