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Merge branch 'master' into AsyncTmxr

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Conflicts merged and missing changes in new modules added as needed for clock co-scheduling.
This commit is contained in:
Mark Pizzolato
2013-01-21 16:52:42 -08:00
parent 7c7df669ad 95033cee15
commit 83c1d80194
344 changed files with 64292 additions and 11863 deletions
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8
Interdata/id16_cpu.c
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@@ -223,11 +223,6 @@ InstHistory *hst = NULL; /* instruction history *
struct BlockIO blk_io; /* block I/O status */
uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL };
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern t_bool sim_idle_enab;
uint32 ReadB (uint32 loc);
uint32 ReadH (uint32 loc);
void WriteB (uint32 loc, uint32 val);
@@ -651,7 +646,6 @@ while (reason == 0) { /* loop until halted */
if (PSW & PSW_WAIT) { /* wait state? */
sim_idle (TMR_LFC, TRUE); /* idling */
else sim_interval = sim_interval - 1; /* no, count cycle */
continue;
}
@@ -2010,8 +2004,6 @@ char *cptr = (char *) desc;
t_value sim_eval[2];
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

11
Interdata/id32_cpu.c
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@@ -222,7 +222,7 @@ uint32 GREG[16 * NRSETS] = { 0 }; /* general registers */
uint32 *M = NULL; /* memory */
uint32 *R = &GREG[0]; /* working reg set */
uint32 F[8] = { 0 }; /* sp fp registers */
dpr_t D[8] = { 0 }; /* dp fp registers */
dpr_t D[8] = { {0} }; /* dp fp registers */
uint32 PSW = 0; /* processor status word */
uint32 PC = 0; /* program counter */
uint32 oPC = 0; /* PC at inst start */
@@ -253,12 +253,6 @@ jmp_buf save_env; /* abort handler */
struct BlockIO blk_io; /* block I/O status */
uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL };
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern t_bool sim_idle_enab;
extern FILE *sim_deb;
uint32 ReadB (uint32 loc, uint32 rel);
uint32 ReadH (uint32 loc, uint32 rel);
void WriteB (uint32 loc, uint32 val, uint32 rel);
@@ -715,7 +709,6 @@ while (reason == 0) { /* loop until halted */
if (PSW & PSW_WAIT) { /* wait state? */
sim_idle (TMR_LFC, TRUE); /* idling */
else sim_interval = sim_interval - 1; /* no, count cycle */
continue;
}
@@ -2399,8 +2392,6 @@ char *cptr = (char *) desc;
t_value sim_eval[3];
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

1
Interdata/id32_dboot.c
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@@ -288,7 +288,6 @@ t_stat id_dboot (int32 u, DEVICE *dptr)
{
extern DIB ttp_dib, sch_dib;
extern uint32 PC;
extern int32 sim_switches;
uint32 i, typ, ctlno, off, add, cap, sch_dev;
UNIT *uptr;

1
Interdata/id_dp.c
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@@ -139,7 +139,6 @@ static struct drvtyp drv_tab[] = {
};
extern uint32 int_req[INTSZ], int_enb[INTSZ];
extern FILE *sim_deb;
uint8 dpxb[DP_NUMBY]; /* xfer buffer */
uint32 dp_bptr = 0; /* buffer ptr */

2
Interdata/id_fd.c
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@@ -115,7 +115,7 @@ uint32 fd_cmd = 0; /* command */
uint32 fd_db = 0; /* data buffer */
uint32 fd_bptr = 0; /* buffer pointer */
uint8 fdxb[FD_NUMBY] = { 0 }; /* sector buffer */
uint8 fd_es[FD_NUMDR][ES_SIZE] = { 0 }; /* ext status */
uint8 fd_es[FD_NUMDR][ES_SIZE] = { {0} }; /* ext status */
uint32 fd_lrn = 0; /* log rec # */
uint32 fd_wdv = 0; /* wd valid */
uint32 fd_stopioe = 1; /* stop on error */

2
Interdata/id_io.c
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@@ -66,8 +66,6 @@ extern uint32 int_req[INTSZ], int_enb[INTSZ];
extern uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout);
extern uint32 pawidth;
extern UNIT cpu_unit;
extern FILE *sim_log;
extern DEVICE *sim_devices[];
uint32 sch_max = 2; /* sch count */
uint32 sch_sa[SCH_NUMCH] = { 0 }; /* start addr */

2
Interdata/id_mt.c
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@@ -168,7 +168,7 @@ DEVICE mt_dev = {
MT_NUMDR, 10, 31, 1, 16, 8,
NULL, NULL, &mt_reset,
&mt_boot, &mt_attach, &mt_detach,
&mt_dib, DEV_DISABLE
&mt_dib, DEV_DISABLE | DEV_TAPE
};
/* Magtape: IO routine */

4
Interdata/id_pas.c
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@@ -103,7 +103,7 @@ uint8 pas_xarm[PAS_LINES]; /* xmt int armed */
uint8 pas_rchp[PAS_LINES]; /* rcvr chr pend */
uint8 pas_tplte[PAS_LINES * 2 + 1]; /* template */
TMLN pas_ldsc[PAS_LINES] = { 0 }; /* line descriptors */
TMLN pas_ldsc[PAS_LINES] = { {0} }; /* line descriptors */
TMXR pas_desc = { 8, 0, 0, pas_ldsc }; /* mux descriptor */
#define PAS_ENAB pas_desc.lines
@@ -165,7 +165,7 @@ DEVICE pas_dev = {
1, 10, 31, 1, 16, 8,
&tmxr_ex, &tmxr_dep, &pas_reset,
NULL, &pas_attach, &pas_detach,
&pas_dib, DEV_NET | DEV_DISABLE
&pas_dib, DEV_MUX | DEV_DISABLE
};
/* PASL data structures

3
Interdata/id_ttp.c
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@@ -130,7 +130,7 @@ DEVICE ttp_dev = {
uint32 ttp (uint32 dev, uint32 op, uint32 dat)
{
int32 xmt = dev & 1;
int32 t, old_cmd;
int32 t;
switch (op) { /* case IO op */
@@ -160,7 +160,6 @@ switch (op) { /* case IO op */
return t;
case IO_OC: /* command */
old_cmd = ttp_cmd; /* old cmd */
if (dat & CMD_TYP) { /* type 1? */
ttp_cmd = (ttp_cmd & 0xFF) | (dat << 8);
if (ttp_cmd & CMD_WRT) /* write? */

2
Interdata/id_uvc.c
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@@ -358,7 +358,7 @@ int32 lfc_cosched (int32 wait)
{
int32 t;
t = sim_is_active (&lfc_unit);
t = sim_activate_time (&lfc_unit);
return (t? t - 1: wait);
}