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3B2-700 Initial Public Release
This commit introduces dozens of changes to make the 3B2-700 simulator fully functional and ready for wider use. In addition to 3B2-700 availability, this commit includes a tremendous amount of refactoring of the 3B2-400 and common code to make the project structure easier to maintain and reason about.
This commit is contained in:
committed by
Mark Pizzolato
parent
48f1430bd0
commit
88916c7bf1
@@ -1,6 +1,6 @@
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/* 3b2_sys.c: AT&T 3B2 common system definitions
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/* 3b2_sys.c: Common System Definition
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Copyright (c) 2021, Seth J. Morabito
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Copyright (c) 2021-2022, Seth J. Morabito
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Permission is hereby granted, free of charge, to any person
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obtaining a copy of this software and associated documentation
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@@ -53,25 +53,57 @@ const char *sim_stop_messages[SCPE_BASE] = {
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"Simulator Error"
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};
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/*
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* ROM and Binary loader
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*
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* -r load ROM
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* -o for memory, specify origin
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*
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*/
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t_stat sim_load(FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)
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{
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t_stat r;
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int32 i;
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uint32 addr = 0;
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uint32 origin = 0, limit = 0;
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int32 cnt = 0;
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if ((*cptr != 0) || (flag != 0)) {
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return SCPE_ARG;
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if (flag) {
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return sim_messagef(SCPE_NOFNC, "Command not implemented.");
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}
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addr = R[NUM_PC];
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while ((i = getc (fileref)) != EOF) {
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pwrite_b(addr, (uint8)i);
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addr++;
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if (sim_switches & SWMASK('R')) {
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origin = ROM_BASE;
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limit = ROM_BASE + ROM_SIZE;
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} else {
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origin = 0;
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limit = (uint32) cpu_unit.capac;
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if (sim_switches & SWMASK('O')) {
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origin = (uint32) get_uint(cptr, 16, 0xffffffff, &r);
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if (r != SCPE_OK) {
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return SCPE_ARG;
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}
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}
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}
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while ((i = Fgetc (fileref)) != EOF) {
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if (origin >= limit) {
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return SCPE_NXM;
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}
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if (sim_switches & SWMASK('R')) {
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pwrite_b_rom(origin, (uint8)i);
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} else {
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pwrite_b(origin, (uint8)i, BUS_CPU);
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}
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origin++;
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cnt++;
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}
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printf ("%d Bytes loaded.\n", cnt);
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if (sim_switches & SWMASK('R')) {
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rom_loaded = TRUE;
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sim_messagef(SCPE_OK, "%d bytes loaded into ROM\n", cnt);
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} else {
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sim_messagef(SCPE_OK, "%d bytes loaded at address 0x%08x\n", cnt, origin - cnt);
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}
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return SCPE_OK;
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}
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