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KA10: Initial release of PDP10 KA/KI and PDP6 simulators.
This commit is contained in:
Richard Cornwell
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PDP10/kx10_dk.c
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PDP10/kx10_dk.c
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/* ka10_dk.c: PDP-10 DK subsystem simulator
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Copyright (c) 2013-2017, Richard Cornwell
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Richard Cornwell shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Richard Cornwell.
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*/
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#include "kx10_defs.h"
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#include <time.h>
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#ifndef NUM_DEVS_DK
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#define NUM_DEVS_DK 0
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#endif
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#if (NUM_DEVS_DK > 0)
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#define DK_DEVNUM 070
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#define STAT_REG u3
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#define CLK_REG u4
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#define INT_REG u5
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#define CLK_TIM u6
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/* CONO */
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#define PIA 000007
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#define CLK_CLR_FLG 000010 /* Clear Clock flag */
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#define CLK_CLR_OVF 000020 /* Clear OVFL flag */
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#define CLK_SET_EN 000040 /* Enable Clock */
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#define CLK_CLR_EN 000100 /* Disable Clock */
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#define CLK_SET_PI 000200 /* Set PI Control Flip-Flop */
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#define CLK_CLR_PI 000400 /* Clear PI Control Flip-Flop */
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#define CLK_GEN_CLR 001000 /* Clear control */
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#define CLK_ADD_ONE 002000 /* Bump clock */
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#define CLK_SET_FLG 004000 /* Set Clock Flag */
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#define CLK_SET_OVF 010000 /* Set OVFL Flag */
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/* CONI */
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#define CLK_FLG 000010
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#define CLK_OVF 000020
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#define CLK_EN 000040
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#define CLK_PI 000200
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#define CLK_EXT 001000
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t_stat dk_devio(uint32 dev, uint64 *data);
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void dk_test (UNIT *uptr);
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t_stat dk_svc (UNIT *uptr);
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const char *dk_description (DEVICE *dptr);
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DIB dk_dib[] = {
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{ DK_DEVNUM, 1, &dk_devio, NULL },
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{ DK_DEVNUM + 4, 1, &dk_devio, NULL}};
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UNIT dk_unit[] = {
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{UDATA (&dk_svc, UNIT_IDLE, 0) },
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#if (NUM_DEVS_DK > 1)
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{UDATA (&dk_svc, UNIT_IDLE, 0) },
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#endif
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};
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DEVICE dk_dev = {
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"DK", dk_unit, NULL, NULL,
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NUM_DEVS_DK, 0, 0, 0, 0, 0,
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NULL, NULL, NULL,
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NULL, NULL, NULL,
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&dk_dib, DEV_DISABLE | DEV_DEBUG, 0, dev_debug,
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NULL, NULL, NULL, NULL, NULL, &dk_description
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};
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t_stat dk_devio(uint32 dev, uint64 *data) {
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int unit = (dev - DK_DEVNUM) >> 2;
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UNIT *uptr;
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double us;
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int32 t;
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if (unit < 0 || unit >= NUM_DEVS_DK)
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return SCPE_OK;
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uptr = &dk_unit[unit];
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switch (dev & 3) {
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case CONI:
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*data = (uint64)(uptr->STAT_REG);
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*data |= ((uint64)uptr->INT_REG) << 18;
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sim_debug(DEBUG_CONI, &dk_dev, "DK %03o CONI %06o PC=%o %06o\n",
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dev, (uint32)*data, PC, uptr->CLK_REG);
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break;
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case CONO:
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/* Adjust U3 */
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clr_interrupt(dev);
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uptr->STAT_REG &= ~07;
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if (*data & CLK_GEN_CLR) {
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uptr->CLK_REG = 0;
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uptr->STAT_REG = 0;
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sim_cancel(uptr);
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}
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uptr->STAT_REG |= (uint32)(*data & 07);
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if (*data & CLK_ADD_ONE) {
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if ((uptr->STAT_REG & CLK_EN) == 0) {
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uptr->CLK_REG++;
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dk_test(uptr);
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}
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}
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if (*data & CLK_SET_EN)
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uptr->STAT_REG |= CLK_EN;
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if (*data & CLK_CLR_EN)
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uptr->STAT_REG &= ~CLK_EN;
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if (*data & CLK_SET_OVF)
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uptr->STAT_REG |= CLK_OVF;
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if (*data & CLK_CLR_OVF)
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uptr->STAT_REG &= ~CLK_OVF;
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if (*data & CLK_SET_FLG)
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uptr->STAT_REG |= CLK_FLG;
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if (*data & CLK_CLR_FLG)
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uptr->STAT_REG &= ~CLK_FLG;
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if (*data & CLK_SET_PI)
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uptr->STAT_REG |= CLK_PI;
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if (*data & CLK_CLR_PI)
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uptr->STAT_REG &= ~CLK_PI;
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if ((uptr->STAT_REG & CLK_EN) != 0 &&
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(uptr->STAT_REG & (CLK_FLG|CLK_OVF))) {
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set_interrupt(dev, uptr->STAT_REG);
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}
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set_clock:
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if (sim_is_active(uptr)) { /* Save current clock time */
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us = sim_activate_time_usecs(uptr);
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uptr->CLK_REG += uptr->CLK_TIM - (uint32)(us / 10.0);
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sim_cancel(uptr);
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}
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if (uptr->INT_REG == uptr->CLK_REG) {
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uptr->STAT_REG |= CLK_FLG;
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set_interrupt(dev, uptr->STAT_REG);
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}
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if (uptr->STAT_REG & CLK_EN) {
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if (uptr->INT_REG < uptr->CLK_REG) /* Count until overflow */
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uptr->CLK_TIM = 01000000;
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else
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uptr->CLK_TIM = uptr->INT_REG;
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t = uptr->CLK_TIM - uptr->CLK_REG;
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us = (double)(t) * 10.0;
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sim_activate_after_d(uptr, us);
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} else {
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sim_cancel(uptr);
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}
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sim_debug(DEBUG_CONO, &dk_dev, "DK %03o CONO %06o PC=%06o %06o\n",
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dev, (uint32)*data, PC, uptr->STAT_REG);
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break;
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case DATAO:
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uptr->INT_REG = (uint32)(*data & RMASK);
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sim_debug(DEBUG_DATAIO, &dk_dev, "DK %03o DATO %012llo PC=%06o\n",
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dev, *data, PC);
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goto set_clock;
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case DATAI:
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if (sim_is_active(uptr)) { /* Save current clock time */
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double us = sim_activate_time_usecs(uptr);
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uptr->CLK_REG += uptr->CLK_TIM - (uint32)(us / 10.0);
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sim_cancel(uptr);
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}
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*data = (uint64)(uptr->CLK_REG);
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sim_debug(DEBUG_DATAIO, &dk_dev, "DK %03o DATI %012llo PC=%06o\n",
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dev, *data, PC);
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goto set_clock;
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}
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return SCPE_OK;
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}
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/* Bump counter by 1 */
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void dk_test (UNIT *uptr)
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{
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int dev;
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if (uptr->CLK_REG & (~RMASK))
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uptr->STAT_REG |= CLK_OVF;
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uptr->CLK_REG &= RMASK;
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if (uptr->INT_REG == uptr->CLK_REG)
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uptr->STAT_REG |= CLK_FLG;
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if (uptr->STAT_REG & (CLK_FLG|CLK_OVF)) {
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dev = ((uptr - dk_unit) << 2) + DK_DEVNUM;
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set_interrupt(dev, uptr->STAT_REG);
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}
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}
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/* Timer service - */
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t_stat dk_svc (UNIT *uptr)
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{
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uptr->CLK_REG = uptr->CLK_TIM;
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dk_test (uptr);
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return SCPE_OK;
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}
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const char *dk_description (DEVICE *dptr)
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{
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return "DK10 Timer module";
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}
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#endif
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