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KA10: Initial release of PDP10 KA/KI and PDP6 simulators.
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Richard Cornwell
284
PDP10/pdp6_dct.c
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284
PDP10/pdp6_dct.c
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/* ka10_dct.c: Type 136 Data Control
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Copyright (c) 2013-2019, Richard Cornwell
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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RICHARD CORNWELL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "kx10_defs.h"
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#ifndef NUM_DEVS_DCT
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#define NUM_DEVS_DCT 0
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#endif
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#if (NUM_DEVS_DCT > 0)
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#define DCT_DEVNUM 0200 /* First device number */
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#define STATUS u3
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/* CONI/CONO Flags */
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#define PIA 0000000000007LL
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#define DEV 0000000000070LL
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#define PACK 0000000000300LL
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#define IN_OUT 0000000000400LL
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#define DB_RQ 0000000001000LL /* DCT has data for 10 or needs data */
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#define DB_AC 0000000002000LL /* DCT has completed a word. */
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#define DB_MV 0000000004000LL /* Data needs to be moved between buffers */
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#define MISS 0000000010000LL
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#define NUM_CHARS 0000000160000LL
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uint64 dct_buf[NUM_DEVS_DCT];
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uint64 dct_acc[NUM_DEVS_DCT];
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t_stat dct_devio(uint32 dev, uint64 *data);
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t_stat dct_svc(UNIT *);
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t_stat dct_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag,
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const char *cptr);
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const char *dct_description (DEVICE *dptr);
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#if !PDP6
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#define D DEV_DIS
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#else
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#define D 0
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#endif
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UNIT dct_unit[] = {
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/* Controller 1 */
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{ UDATA (&dct_svc, UNIT_DISABLE, 0) },
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{ UDATA (&dct_svc, UNIT_DISABLE, 0) },
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};
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DIB dct_dib[] = {
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{DCT_DEVNUM, NUM_DEVS_DCT, &dct_devio, NULL},
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};
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REG dct_reg[] = {
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{BRDATA(BUFF, &dct_buf[0], 16, 36, NUM_DEVS_DCT), REG_HRO},
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{BRDATA(BUFF, &dct_acc[0], 16, 36, NUM_DEVS_DCT), REG_HRO},
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{0}
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};
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DEVICE dct_dev = {
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"DCT", dct_unit, dct_reg, NULL,
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NUM_DEVS_DCT, 8, 18, 1, 8, 36,
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NULL, NULL, NULL, NULL, NULL, NULL,
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&dct_dib[0], DEV_DISABLE | DEV_DEBUG | D, 0, dev_debug,
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NULL, NULL, &dct_help, NULL, NULL, &dct_description
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};
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t_stat
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dct_devio(uint32 dev, uint64 *data) {
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int u;
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UNIT *uptr = NULL;
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u = (dev - dct_dib[0].dev_num) >> 2;
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if (u >= NUM_DEVS_DCT)
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return SCPE_OK;
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uptr = &dct_unit[u];
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switch(dev & 3) {
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case CONI:
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*data = (uint64)(uptr->STATUS);
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sim_debug(DEBUG_CONI, &dct_dev, "DCT %03o CONI %012llo %d PC=%o\n", dev,
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*data, u, PC);
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break;
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case CONO:
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clr_interrupt(dev);
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/* Clear flags */
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uptr->STATUS = *data & 017777;
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if (uptr->STATUS & DB_RQ)
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set_interrupt(dev, uptr->STATUS);
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sim_debug(DEBUG_CONO, &dct_dev, "DCT %03o CONO %06o %d PC=%o %06o\n", dev,
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(uint32)*data, u, PC, uptr->STATUS);
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break;
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case DATAI:
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clr_interrupt(dev);
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if (uptr->STATUS & DB_RQ) {
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*data = dct_buf[u];
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uptr->STATUS &= ~(DB_RQ);
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uptr->STATUS |= DB_MV;
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sim_activate(uptr, 10);
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}
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sim_debug(DEBUG_DATAIO, &dct_dev, "DCT %03o DATI %012llo %d PC=%o\n",
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dev, *data, u, PC);
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break;
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case DATAO:
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clr_interrupt(dev);
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sim_debug(DEBUG_DATAIO, &dct_dev, "DCT %03o DATO %012llo, %d PC=%o\n",
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dev, *data, u, PC);
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if (uptr->STATUS & DB_RQ) {
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dct_buf[u] = *data;
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uptr->STATUS &= ~(DB_RQ);
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uptr->STATUS |= DB_MV;
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sim_activate(uptr, 10);
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}
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}
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return SCPE_OK;
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}
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/* OUT = 0, dev-> 10, OUT=1 10 -> dev */
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/* OUT starts with RQ & AC with MV =0 */
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/* IN starts with MV = 1 RQ & AC = 0 */
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t_stat
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dct_svc (UNIT *uptr)
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{
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int u = uptr - dct_unit;
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int dev = dct_dib[0].dev_num + (u << 2);
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/* Transfer from 10 to device */
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if ((uptr->STATUS & (DB_MV|IN_OUT|DB_AC|DB_RQ)) == (DB_AC|DB_MV|IN_OUT)) {
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dct_acc[u] = dct_buf[u];
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uptr->STATUS &= ~(DB_MV|DB_AC);
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uptr->STATUS |= DB_RQ;
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}
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/* Tranfer from device to 10 */
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if ((uptr->STATUS & (DB_MV|IN_OUT|DB_AC|DB_RQ)) == (DB_AC|DB_MV)) {
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dct_buf[u] = dct_acc[u];
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uptr->STATUS &= ~(DB_MV|DB_AC);
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uptr->STATUS |= DB_RQ;
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}
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if (uptr->STATUS & DB_RQ)
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set_interrupt(dev, uptr->STATUS);
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return SCPE_OK;
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}
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/* Check if the dct is still connected to this device. */
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int
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dct_is_connect (int dev)
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{
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int d = dev & 07;
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int u = (dev >> 3) & 07;
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UNIT *uptr;
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/* Valid device? */
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if (u >= NUM_DEVS_DCT)
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return 0;
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uptr = &dct_unit[u];
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/* Is DCT pointed at this device? */
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if (((uptr->STATUS & DEV) >> 3) != d)
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return 0;
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/* If sending processor to device, and no data, terminate */
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if ((uptr->STATUS & IN_OUT) != 0 && (uptr->STATUS & DB_AC) != 0)
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return 0;
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/* Everything ok, still connected */
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return 1;
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}
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/* Read data from memory */
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int
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dct_read (int dev, uint64 *data, int cnt)
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{
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int d = dev & 07;
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int u = (dev >> 3) & 07;
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DEVICE *dptr = &dct_dev;
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UNIT *uptr;
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/* Valid device? */
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if (u >= NUM_DEVS_DCT)
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return 0;
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uptr = &dct_unit[u];
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/* Is DCT pointed at this device? */
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if (((uptr->STATUS & DEV) >> 3) != d)
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return 0;
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/* Check if correct direction */
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if ((uptr->STATUS & IN_OUT) == 0)
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return 0;
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/* If we have data return it */
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if ((uptr->STATUS & DB_AC) == 0) {
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*data = dct_acc[u];
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sim_debug(DEBUG_DATA, dptr, "DCT Read %012llo, %d \n",
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*data, u);
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uptr->STATUS &= ~(NUM_CHARS);
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uptr->STATUS |= DB_AC | DB_MV | ((cnt & 7) << 13);
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sim_activate(uptr, 20);
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return 1;
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}
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return 0;
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}
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/* Write data to memory */
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int
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dct_write (int dev, uint64 *data, int cnt)
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{
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int d = dev & 07;
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int u = (dev >> 3) & 07;
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DEVICE *dptr = &dct_dev;
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UNIT *uptr;
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/* Valid device? */
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if (u >= NUM_DEVS_DCT)
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return 0;
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uptr = &dct_unit[u];
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/* Is DCT pointed at this device? */
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if (((uptr->STATUS & DEV) >> 3) != d)
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return 0;
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/* Check if correct direction */
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if ((uptr->STATUS & IN_OUT) != 0)
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return 0;
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/* If buffer is empty put data in it. */
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if ((uptr->STATUS & DB_AC) == 0) {
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dct_acc[u] = *data;
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sim_debug(DEBUG_DATA, dptr, "DCT Write %012llo, %d %06o\n", *data, u, uptr->STATUS);
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uptr->STATUS &= ~(NUM_CHARS);
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uptr->STATUS |= DB_AC | DB_MV | ((cnt & 7) << 13);
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sim_activate(uptr, 20);
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return 1;
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}
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return 0;
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}
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t_stat
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dct_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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fprintf (st, "Data Controller Type 136 is a data buffer between fast ");
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fprintf (st, "devices and the PDP6. Individual devices are hooked up to ports ");
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fprintf (st, "on each DCT.\n");
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fprint_set_help (st, dptr);
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fprint_show_help (st, dptr);
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return SCPE_OK;
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}
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const char *
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dct_description (DEVICE *dptr)
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{
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return "Data Controller Type 136";
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}
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#endif
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