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alpha, HP2100, ID16, ID32, PDP11 and VAX: Normalize array REG definitions
Array REGister definitions have been made consistent by passing the address of the whole array object. This allows proper sizing assessment to occur in the register validation logic.
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@@ -1197,8 +1197,8 @@ REG dmc_reg[] = {
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{ BRDATAD (SPEED, dmc_speed, DEV_RDX, 32, DMC_NUMDEVICE, "line speed") },
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{ BRDATAD (CORRUPT, dmc_corruption, DEV_RDX, 32, DMC_NUMDEVICE, "data corruption factor (0.1%)") },
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{ BRDATAD (DIAG, dmc_microdiag, DEV_RDX, 1, DMC_NUMDEVICE, "Microdiagnostic Enabled") },
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{ BRDATAD (PEER, dmc_peer, DEV_RDX, 8, DMC_NUMDEVICE*PEERSIZE, "peer address:port") },
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{ BRDATAD (PORT, dmc_port, DEV_RDX, 8, DMC_NUMDEVICE*PEERSIZE, "listen port") },
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{ BRDATAD (PEER, &dmc_peer, DEV_RDX, 8, DMC_NUMDEVICE*PEERSIZE, "peer address:port") },
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{ BRDATAD (PORT, &dmc_port, DEV_RDX, 8, DMC_NUMDEVICE*PEERSIZE, "listen port") },
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{ BRDATAD (BASEADDR, dmc_baseaddr, DEV_RDX, 32, DMC_NUMDEVICE, "program set base address") },
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{ BRDATAD (BASESIZE, dmc_basesize, DEV_RDX, 16, DMC_NUMDEVICE, "program set base size") },
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{ BRDATAD (MODEM, dmc_modem, DEV_RDX, 8, DMC_NUMDEVICE, "modem control bits") },
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@@ -988,7 +988,7 @@ REG rq_reg[] = {
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{ DRDATAD (I4TIME, rq_itime4, 24, "init stage 4 delay"), PV_LEFT + REG_NZ },
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{ DRDATAD (QTIME, rq_qtime, 24, "response time for 'immediate' packets"), PV_LEFT + REG_NZ },
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{ DRDATAD (XTIME, rq_xtime, 24, "response time for data transfers"), PV_LEFT + REG_NZ },
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{ BRDATAD (PKTS, rq_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
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{ BRDATAD (PKTS, &rq_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
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{ URDATAD (CPKT, rq_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
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{ URDATAD (UCNUM, rq_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
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{ URDATAD (PKTQ, rq_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
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@@ -1167,7 +1167,7 @@ REG rqb_reg[] = {
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{ FLDATA (PRGI, rqb_ctx.prgi, 0), REG_HIDDEN },
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{ FLDATA (PIP, rqb_ctx.pip, 0), REG_HIDDEN },
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{ BINRDATA(CTYPE, rqb_ctx.ctype, 32), REG_HIDDEN },
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{ BRDATAD (PKTS, rqb_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
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{ BRDATAD (PKTS, &rqb_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
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{ URDATAD (CPKT, rqb_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
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{ URDATAD (UCNUM, rqb_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
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{ URDATAD (PKTQ, rqb_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
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@@ -1240,7 +1240,7 @@ REG rqc_reg[] = {
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{ FLDATA (PRGI, rqc_ctx.prgi, 0), REG_HIDDEN },
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{ FLDATA (PIP, rqc_ctx.pip, 0), REG_HIDDEN },
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{ BINRDATA(CTYPE, rqc_ctx.ctype, 32), REG_HIDDEN },
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{ BRDATAD (PKTS, rqc_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
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{ BRDATAD (PKTS, &rqc_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
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{ URDATAD (CPKT, rqc_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
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{ URDATAD (UCNUM, rqc_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
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{ URDATAD (PKTQ, rqc_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
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@@ -1313,7 +1313,7 @@ REG rqd_reg[] = {
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{ FLDATA (PRGI, rqd_ctx.prgi, 0), REG_HIDDEN },
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{ FLDATA (PIP, rqd_ctx.pip, 0), REG_HIDDEN },
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{ BINRDATA(CTYPE, rqd_ctx.ctype, 32), REG_HIDDEN },
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{ BRDATAD (PKTS, rqd_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
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{ BRDATAD (PKTS, &rqd_ctx.pak, DEV_RDX, 16, sizeof(rq_ctx.pak)/2, "packet buffers, 33W each, 32 entries") },
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{ URDATAD (CPKT, rqd_unit[0].cpkt, 10, 5, 0, RQ_NUMDR, 0, "current packet, units 0 to 3") },
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{ URDATAD (UCNUM, rqd_unit[0].cnum, 10, 5, 0, RQ_NUMDR, 0, "ctrl number, units 0 to 3") },
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{ URDATAD (PKTQ, rqd_unit[0].pktq, 10, 5, 0, RQ_NUMDR, 0, "packet queue, units 0 to 3") },
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@@ -464,7 +464,7 @@ REG tq_reg[] = {
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{ DRDATAD (QTIME, tq_qtime, 24, "response time for 'immediate' packets"), PV_LEFT + REG_NZ },
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{ DRDATAD (XTIME, tq_xtime, 24, "response time for data transfers"), PV_LEFT + REG_NZ },
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{ DRDATAD (RWTIME, tq_rwtime, 32, "rewind time 2 sec (adjusted later)"), PV_LEFT + REG_NZ },
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{ BRDATAD (PKTS, tq_pkt, DEV_RDX, 16, TQ_NPKTS * (TQ_PKT_SIZE_W + 1), "packet buffers, 33W each, 32 entries") },
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{ BRDATAD (PKTS, &tq_pkt, DEV_RDX, 16, TQ_NPKTS * (TQ_PKT_SIZE_W + 1), "packet buffers, 33W each, 32 entries") },
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{ URDATAD (PLUG, tq_unit[0].unit_plug, 10, 32, 0, TQ_NUMDR, PV_LEFT | REG_RO, "unit plug value, units 0 to 3") },
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{ DRDATA (DEVTYPE, tq_typ, 2), REG_HRO },
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{ DRDATA (DEVCAP, drv_tab[TQU_TYPE].cap, T_ADDR_W), PV_LEFT | REG_HRO },
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