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https://github.com/simh/simh.git
synced 2026-05-03 14:38:45 +00:00
Intel-MDS: Update to the latest and fix inconsistent REGister declarations
This commit is contained in:
Bill Beech
@@ -53,6 +53,29 @@ int i8253_num = 0;
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int i8253_baseport[] = { -1, -1, -1, -1 }; //base port
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uint8 i8253_intnum[4] = { 0, 0, 0, 0 }; //interrupt number
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uint8 i8253_verb[4] = { 0, 0, 0, 0 }; //verbose flag
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uint8 i8253_T0_control_word[4];
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uint8 i8253_T0_flag[4];
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uint16 i8253_T0_load[4];
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uint16 i8253_T0_latch[4];
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uint16 i8253_T0_count[4];
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int i8253_T0_gate[4];
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int i8253_T0_out[4];
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uint8 i8253_T1_control_word[4];
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uint8 i8253_T1_flag[4];
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uint16 i8253_T1_load[4];
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uint16 i8253_T1_latch[4];
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uint16 i8253_T1_count[4];
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int i8253_T1_gate[4];
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int i8253_T1_out[4];
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uint8 i8253_T2_control_word[4];
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uint8 i8253_T2_flag[4];
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uint16 i8253_T2_load[4];
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uint16 i8253_T2_latch[4];
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uint16 i8253_T2_count[4];
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int i8253_T2_gate[4];
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int i8253_T2_out[4];
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/* function prototypes */
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t_stat i8253_cfg(uint16 base, uint16 devnum, uint8 dummy);
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@@ -76,14 +99,10 @@ UNIT i8253_unit[] = {
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};
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REG i8253_reg[] = {
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{ HRDATA (T0, i8253_unit[0].u3, 8) },
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{ HRDATA (T1, i8253_unit[0].u4, 8) },
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{ HRDATA (T2, i8253_unit[0].u5, 8) },
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{ HRDATA (CMD, i8253_unit[0].u6, 8) },
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{ HRDATA (T0, i8253_unit[1].u3, 8) },
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{ HRDATA (T1, i8253_unit[1].u4, 8) },
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{ HRDATA (T2, i8253_unit[1].u5, 8) },
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{ HRDATA (CMD, i8253_unit[1].u6, 8) },
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{ URDATAD(T0,i8253_unit[0].u3,16,8,0,4,0,"Timer 0") },
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{ URDATAD(T1,i8253_unit[0].u4,16,8,0,4,0,"Timer 1") },
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{ URDATAD(T2,i8253_unit[0].u5,16,8,0,4,0,"Timer 2") },
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{ URDATAD(CMD,i8253_unit[0].u6,16,8,0,4,0,"Command") },
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{ NULL }
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};
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@@ -92,14 +111,13 @@ DEBTAB i8253_debug[] = {
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ "XACK", DEBUG_xack },
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{ NULL }
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};
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MTAB i8253_mod[] = {
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{ MTAB_XTD | MTAB_VDV, 0, "PARAM", NULL, NULL, i8253_show_param, NULL,
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"show configured parametes for i8253" },
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"show configured parameters for i8253" },
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{ 0 }
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};
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@@ -110,7 +128,7 @@ DEVICE i8253_dev = {
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i8253_unit, //units
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i8253_reg, //registers
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i8253_mod, //modifiers
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I8253_NUM, //numunits
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4, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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@@ -140,17 +158,24 @@ DEVICE i8253_dev = {
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t_stat i8253_cfg(uint16 base, uint16 devnum, uint8 dummy)
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{
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i8253_baseport[devnum] = base & 0xff;
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UNIT *uptr;
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uptr = i8253_dev.units;
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i8253_baseport[devnum] = base & BYTEMASK;
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sim_printf(" i8253%d: installed at base port 0%02XH\n",
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devnum, i8253_baseport[devnum]);
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reg_dev(i8253t0, i8253_baseport[devnum], devnum, 0);
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reg_dev(i8253t1, i8253_baseport[devnum] + 1, devnum, 0);
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reg_dev(i8253t2, i8253_baseport[devnum] + 2, devnum, 0);
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reg_dev(i8253c, i8253_baseport[devnum] + 3, devnum, 0);
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uptr->u6 = i8253_num;
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i8253_num++;
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sim_activate (uptr, uptr->wait); /* start poll */
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return SCPE_OK;
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}
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// i8253 unconfiguration
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t_stat i8253_clr(void)
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{
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int i;
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@@ -189,11 +214,130 @@ t_stat i8253_show_param (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
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return SCPE_OK;
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}
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/* i8253_svc - actually gets char & places in buffer */
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/* i8253_svc - actually does timing */
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t_stat i8253_svc (UNIT *uptr)
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{
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sim_activate (&i8253_unit[0], i8253_unit[0].wait); /* continue poll */
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int devnum;
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if (uptr == NULL)
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return SCPE_ARG;
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devnum = uptr->u6; //get devnum for unit
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switch (i8253_T0_control_word[devnum]) {
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case 0: //mode 0
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break;
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case 1: //mode 1
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break;
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case 2: //mode 2 - rate generator
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if (i8253_T0_gate[devnum]) {
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i8253_T0_out[devnum] = 0;
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if (i8253_T0_flag[devnum] == 0x10) {
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i8253_T0_count[devnum]--; //decrement counter
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if (i8253_T0_count[devnum] == 0) { //if 0, do something
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i8253_T0_out[devnum] = 1;
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i8253_T0_count[devnum] = i8253_T0_load[devnum];
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} else {
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i8253_T0_out[devnum] = 1;
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}
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}
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}
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break;
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case 3: //mode 3 - square wave rate generator
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if (i8253_T0_gate[devnum]) {
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i8253_T0_out[devnum] = 0;
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if (i8253_T0_flag[devnum] == 0x10) {
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i8253_T0_count[devnum]--; //decrement counter
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if (i8253_T0_count[devnum] == 0) { //if 0, do something
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i8253_T0_out[devnum] = ~i8253_T0_out[devnum];
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i8253_T0_count[devnum] = i8253_T0_load[devnum];
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} else {
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i8253_T0_out[devnum] = 1;
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}
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}
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}
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break;
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case 4: //mode 4
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break;
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case 5: //mode 5
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break;
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}
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switch (i8253_T1_control_word[devnum]) {
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case 0: //mode 0
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break;
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case 1: //mode 1
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break;
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case 2: //mode 2 - rate generator
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if (i8253_T1_gate[devnum]) {
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i8253_T1_out[devnum] = 0;
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if (i8253_T0_flag[devnum] == 0x20) {
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i8253_T1_count[devnum]--; //decrement counter
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if (i8253_T1_count[devnum] == 0) { //if 0, do something
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i8253_T1_out[devnum] = 1;
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i8253_T1_count[devnum] = i8253_T1_load[devnum];
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} else {
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i8253_T1_out[devnum] = 1;
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}
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}
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}
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break;
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case 3: //mode 3 - square wave rate generator
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if (i8253_T1_gate[devnum]) {
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i8253_T1_out[devnum] = 0;
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if (i8253_T0_flag[devnum] == 0x20) {
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i8253_T1_count[devnum]--; //decrement counter
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if (i8253_T1_count[devnum] == 0) { //if 0, do something
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i8253_T1_out[devnum] = ~i8253_T1_out[devnum];
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i8253_T1_count[devnum] = i8253_T1_load[devnum];
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} else {
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i8253_T1_out[devnum] = 1;
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}
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}
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}
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break;
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case 4: //mode 4
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break;
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case 5: //mode 5
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break;
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}
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switch (i8253_T2_control_word[devnum]) {
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case 0: //mode 0
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break;
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case 1: //mode 1
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break;
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case 2: //mode 2 - rate generator
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if (i8253_T2_gate[devnum]) {
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i8253_T2_out[devnum] = 0;
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if (i8253_T0_flag[devnum] == 0x40) {
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i8253_T2_count[devnum]--; //decrement counter
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if (i8253_T2_count[devnum] == 0) { //if 0, do something
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i8253_T2_out[devnum] = 1;
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i8253_T2_count[devnum] = i8253_T2_load[devnum];
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} else {
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i8253_T2_out[devnum] = 1;
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}
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}
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}
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break;
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case 3: //mode 3 - square wave rate generator
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if (i8253_T2_gate[devnum]) {
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i8253_T2_out[devnum] = 0;
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if (i8253_T0_flag[devnum] == 0x40) {
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i8253_T2_count[devnum]--; //decrement counter
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if (i8253_T2_count[devnum] == 0) { //if 0, do something
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i8253_T2_out[devnum] = ~i8253_T2_out[devnum];
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i8253_T2_count[devnum] = i8253_T2_load[devnum];
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} else {
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i8253_T2_out[devnum] = 1;
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}
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}
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}
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break;
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case 4: //mode 4
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break;
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case 5: //mode 5
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break;
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}
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sim_activate (uptr, uptr->wait); /* continue poll */
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return SCPE_OK;
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}
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@@ -201,14 +345,15 @@ t_stat i8253_svc (UNIT *uptr)
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t_stat i8253_reset (DEVICE *dptr)
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{
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uint8 devnum;
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for (devnum=0; devnum<i8253_num+1; devnum++) {
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i8253_unit[devnum].u3 = 0; /* status */
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i8253_unit[devnum].u4 = 0; /* mode instruction */
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i8253_unit[devnum].u5 = 0; /* command instruction */
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i8253_unit[devnum].u6 = 0;
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}
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int i;
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for (i = 0; i < 4; i++)
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if (i < i8253_num)
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i8253_unit[i].flags = 0;
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else {
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sim_cancel (&i8253_unit[i]);
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i8253_unit[i].flags = UNIT_DIS;
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}
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return SCPE_OK;
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}
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@@ -218,48 +363,198 @@ t_stat i8253_reset (DEVICE *dptr)
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uint8 i8253t0(t_bool io, uint8 data, uint8 devnum)
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{
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uint8 rl;
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rl = (i8253_T1_control_word[devnum] >> 4) & 0x03;
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if (io == 0) { /* read data port */
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return i8253_unit[devnum].u3;
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switch (rl) {
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case 0: //counter latching
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i8253_T1_latch[devnum] = i8253_T1_count[devnum];
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break;
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case 1: //read/load msb
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i8253_T1_latch[devnum] = i8253_T1_count[devnum];
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return (i8253_T1_latch[devnum] >> 8);
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break;
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case 2: //read/load lsb
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i8253_T1_latch[devnum] = i8253_T1_count[devnum];
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return (i8253_T1_latch[devnum] & BYTEMASK);
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break;
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case 3: //read/load lsb then msb
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i8253_T1_latch[devnum] = i8253_T1_count[devnum];
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break;
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}
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if ((i8253_T1_flag[devnum] & 0x01) == 0) {
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i8253_T1_flag[devnum] |= 0x01;
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return (i8253_T1_latch[devnum] & BYTEMASK);
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} else {
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i8253_T1_flag[devnum] &= 0xfe;
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return (i8253_T1_latch[devnum] >> 8);
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}
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} else { /* write data port */
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i8253_unit[devnum].u3 = data;
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//sim_activate_after (&i8253_unit[devnum], );
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return 0;
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switch (rl) {
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case 0: //counter latching
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i8253_T1_latch[devnum] = i8253_T1_count[devnum];
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break;
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case 1: //read/load msb
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i8253_T1_load[devnum] = (data << 8);
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i8253_T1_flag[devnum] |= 0x10;
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break;
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case 2: //read/load lsb
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i8253_T1_load[devnum] = data;
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i8253_T1_flag[devnum] |= 0x10;
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break;
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case 3: //read/load lsb then msb
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if ((i8253_T1_flag[devnum] & 0x01) == 0) {
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i8253_T1_load[devnum] = data;
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i8253_T1_flag[devnum] |= 0x01;
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} else {
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i8253_T1_load[devnum] |= (data << 8);
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i8253_T1_flag[devnum] &= 0xfe;
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i8253_T1_flag[devnum] |= 0x10;
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}
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break;
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}
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}
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return 0;
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}
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//read routine:
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//sim_activate_time(&i8253_unit[devnum])/sim_inst_per_second()
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uint8 i8253t1(t_bool io, uint8 data, uint8 devnum)
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{
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uint8 rl;
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rl = (i8253_T1_control_word[devnum] >> 4) & 0x03;
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if (io == 0) { /* read data port */
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return i8253_unit[devnum].u4;
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switch (rl) {
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case 0: //counter latching
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i8253_T1_latch[devnum] = i8253_T1_count[devnum];
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break;
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case 1: //read/load msb
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i8253_T1_latch[devnum] = i8253_T1_count[devnum];
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return (i8253_T1_latch[devnum] >> 8);
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break;
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case 2: //read/load lsb
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i8253_T1_latch[devnum] = i8253_T1_count[devnum];
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return (i8253_T1_latch[devnum] & BYTEMASK);
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break;
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case 3: //read/load lsb then msb
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i8253_T1_latch[devnum] = i8253_T1_count[devnum];
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break;
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}
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if ((i8253_T1_flag[devnum] & 0x02) == 0) {
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i8253_T1_flag[devnum] |= 0x02;
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return (i8253_T1_latch[devnum] & BYTEMASK);
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} else {
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i8253_T1_flag[devnum] &= 0xfd;
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return (i8253_T1_latch[devnum] >> 8);
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}
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} else { /* write data port */
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i8253_unit[devnum].u4 = data;
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return 0;
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switch (rl) {
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case 0: //counter latching
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i8253_T1_latch[devnum] = i8253_T1_count[devnum];
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break;
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case 1: //read/load msb
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i8253_T1_load[devnum] = (data << 8);
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i8253_T1_flag[devnum] |= 0x20;
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break;
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case 2: //read/load lsb
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i8253_T1_load[devnum] = data;
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i8253_T1_flag[devnum] |= 0x20;
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break;
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case 3: //read/load lsb then msb
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if ((i8253_T1_flag[devnum] & 0x02) == 0) {
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i8253_T1_load[devnum] = data;
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i8253_T1_flag[devnum] |= 0x02;
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} else {
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i8253_T1_load[devnum] |= (data << 8);
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i8253_T1_flag[devnum] &= 0xfd;
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i8253_T1_flag[devnum] |= 0x20;
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}
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break;
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}
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}
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return 0;
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}
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uint8 i8253t2(t_bool io, uint8 data, uint8 devnum)
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{
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uint8 rl;
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rl = (i8253_T2_control_word[devnum] >> 4) & 0x03;
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if (io == 0) { /* read data port */
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return i8253_unit[devnum].u5;
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switch (rl) {
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case 0: //counter latching
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i8253_T2_latch[devnum] = i8253_T2_count[devnum];
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break;
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case 1: //read/load msb
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i8253_T2_latch[devnum] = i8253_T2_count[devnum];
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return (i8253_T2_latch[devnum] >> 8);
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break;
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case 2: //read/load lsb
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i8253_T2_latch[devnum] = i8253_T2_count[devnum];
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return (i8253_T2_latch[devnum] & BYTEMASK);
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break;
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case 3: //read/load lsb then msb
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i8253_T2_latch[devnum] = i8253_T2_count[devnum];
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break;
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}
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if ((i8253_T2_flag[devnum] & 0x04) == 0) {
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i8253_T2_flag[devnum] |= 0x04;
|
||||
return (i8253_T2_latch[devnum] & BYTEMASK);
|
||||
}
|
||||
else {
|
||||
i8253_T2_flag[devnum] &= 0xfb;
|
||||
return (i8253_T2_latch[devnum] >> 8);
|
||||
}
|
||||
} else { /* write data port */
|
||||
i8253_unit[devnum].u5 = data;
|
||||
return 0;
|
||||
switch (rl) {
|
||||
case 0: //counter latching
|
||||
i8253_T2_latch[devnum] = i8253_T2_count[devnum];
|
||||
break;
|
||||
case 1: //read/load msb
|
||||
i8253_T2_load[devnum] = (data << 8);
|
||||
i8253_T2_flag[devnum] |= 0x40;
|
||||
break;
|
||||
case 2: //read/load lsb
|
||||
i8253_T2_load[devnum] = data;
|
||||
i8253_T2_flag[devnum] |= 0x40;
|
||||
break;
|
||||
case 3: //read/load lsb then msb
|
||||
if ((i8253_T2_flag[devnum] & 0x04) == 0) {
|
||||
i8253_T2_load[devnum] = data;
|
||||
i8253_T2_flag[devnum] |= 0x04;
|
||||
} else {
|
||||
i8253_T2_load[devnum] |= (data << 8);
|
||||
i8253_T2_flag[devnum] &= 0xfb;
|
||||
i8253_T2_flag[devnum] |= 0x40;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8 i8253c(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
uint8 sc;
|
||||
|
||||
if (io == 0) { /* read status port */
|
||||
return i8253_unit[devnum].u6;
|
||||
return 0xff;
|
||||
} else { /* write data port */
|
||||
i8253_unit[devnum].u6 = data;
|
||||
return 0;
|
||||
sc = (data >> 6) & 0x03;
|
||||
switch (sc) {
|
||||
case 0:
|
||||
i8253_T0_control_word[devnum] = data;
|
||||
i8253_T0_flag[devnum] = 0;
|
||||
break;
|
||||
case 1:
|
||||
i8253_T1_control_word[devnum] = data;
|
||||
i8253_T1_flag[devnum] = 0;
|
||||
break;
|
||||
case 2:
|
||||
i8253_T2_control_word[devnum] = data;
|
||||
i8253_T2_flag[devnum] = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user