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PDP11: Fix EXAMINE and DEPOSIT of floating point 2 argument instructions
In https:://github.com/open-simh/simh PR number 154 nickd4 that 2 argument floating point instructions were displayed with the wrong argument order. This change fixes BOTH the instruction display and the input activities for these floating point instructions.
This commit is contained in:
committed by
Mark Pizzolato
parent
135e69c4a1
commit
9319f6027e
@@ -23,6 +23,7 @@
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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31-Dec-22 RMS Floating loads are src,dst (nickd4)
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23-May-18 RMS Changed UC15 simulator name
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14-Mar-16 RMS Added UC15 support
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02-Sep-13 RMS Added third Massbus, RS03/RS04
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@@ -346,6 +347,9 @@ return SCPE_CSUM;
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#define I_V_CCC 14 /* CC clear */
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#define I_V_CCS 15 /* CC set */
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#define I_V_SOPR 16 /* operand, reg */
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#define I_V_FOPA 17 /* flt operand, fac */
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#define I_V_SOPA 18 /* operand, fac */
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#define I_V_SMDA 19 /* moded int op, fac */
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#define I_NPN (I_V_NPN << I_V_CL)
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#define I_REG (I_V_REG << I_V_CL)
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#define I_3B (I_V_3B << I_V_CL)
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@@ -363,13 +367,17 @@ return SCPE_CSUM;
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#define I_CCC (I_V_CCC << I_V_CL)
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#define I_CCS (I_V_CCS << I_V_CL)
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#define I_SOPR (I_V_SOPR << I_V_CL)
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#define I_FOPA (I_V_FOPA << I_V_CL)
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#define I_SOPA (I_V_SOPA << I_V_CL)
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#define I_SMDA (I_V_SMDA << I_V_CL)
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static const int32 masks[] = {
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0177777, 0177770, 0177700, 0177770,
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0177700+I_D, 0177400+I_D, 0177700, 0177400,
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0177400, 0177000, 0177000, 0177400,
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0177400+I_D+I_L, 0170000, 0177777, 0177777,
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0177000
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0177700+I_D, 0177400+I_D, 0177700, 0177400,
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0177000, 0177700+I_D, 0177400, 0177400+I_D+I_L
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};
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static const char *opcode[] = {
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@@ -497,16 +505,16 @@ static const int32 opc_val[] = {
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0170100+I_SOP, 0170200+I_SOP, 0170300+I_SOP,
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0170400+I_FOP, 0170400+I_FOP+I_D, 0170500+I_FOP, 0170500+I_FOP+I_D,
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0170600+I_FOP, 0170600+I_FOP+I_D, 0170700+I_FOP, 0170700+I_FOP+I_D,
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0171000+I_AFOP, 0171000+I_AFOP+I_D, 0171400+I_AFOP, 0171400+I_AFOP+I_D,
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0172000+I_AFOP, 0172000+I_AFOP+I_D, 0172400+I_AFOP, 0172400+I_AFOP+I_D,
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0173000+I_AFOP, 0173000+I_AFOP+I_D, 0173400+I_AFOP, 0173400+I_AFOP+I_D,
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0174000+I_AFOP, 0174000+I_AFOP+I_D, 0174400+I_AFOP, 0174400+I_AFOP+I_D,
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0171000+I_FOPA, 0171000+I_FOPA+I_D, 0171400+I_FOPA, 0171400+I_FOPA+I_D,
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0172000+I_FOPA, 0172000+I_FOPA+I_D, 0172400+I_FOPA, 0172400+I_FOPA+I_D,
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0173000+I_FOPA, 0173000+I_FOPA+I_D, 0173400+I_FOPA, 0173400+I_FOPA+I_D,
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0174000+I_AFOP, 0174000+I_AFOP+I_D, 0174400+I_FOPA, 0174400+I_FOPA+I_D,
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0175000+I_ASOP,
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0175400+I_ASMD, 0175400+I_ASMD+I_D, 0175400+I_ASMD+I_L, 0175400+I_ASMD+I_D+I_L,
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0176000+I_AFOP, 0176000+I_AFOP+I_D,
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0176400+I_ASOP,
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0177000+I_ASMD, 0177000+I_ASMD+I_D, 0177000+I_ASMD+I_L, 0177000+I_ASMD+I_D+I_L,
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0177400+I_AFOP, 0177400+I_AFOP+I_D,
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0176400+I_SOPA,
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0177000+I_SMDA, 0177000+I_SMDA+I_D, 0177000+I_SMDA+I_L, 0177000+I_SMDA+I_D+I_L,
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0177400+I_FOPA, 0177400+I_FOPA+I_D,
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-1
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};
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@@ -749,6 +757,18 @@ for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
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wd2 = fprint_spec (of, addr - wd1 - wd1, dstm,
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val[1 - wd1], cflag, TRUE);
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break;
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case I_V_FOPA: /* fopa */
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fprintf (of, "%s ", opcode[i]);
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wd1 = fprint_spec (of, addr, dstm, val[1], cflag, FALSE);
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fprintf (of, ",%s", fname[fac]);
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break;
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case I_V_SOPA: case I_V_SMDA: /* sopa, smda */
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fprintf (of, "%s ", opcode[i]);
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wd1 = fprint_spec (of, addr, dstm, val[1], cflag, TRUE);
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fprintf (of, ",%s", fname[fac]);
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break;
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} /* end case */
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return ((wd1 + wd2) * 2) - 1;
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} /* end if */
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@@ -1139,6 +1159,20 @@ switch (j) { /* case on class */
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}
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break;
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case I_V_FOPA: case I_V_SOPA: case I_V_SMDA: /* (s)fop, fac */
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cptr = get_glyph (cptr, gbuf, ','); /* get glyph */
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if ((n1 = get_spec (gbuf, addr, 0, &spec, &val[1], cflag,
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(j == I_V_SOPA) || (j == I_V_SMDA))) > 0)
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return SCPE_ARG;
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val[0] = val[0] | spec;
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cptr = get_glyph (cptr, gbuf, 0); /* get glyph */
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if ((reg = get_reg (gbuf, fname, 0)) < 0)
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return SCPE_ARG;
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if (reg > 3)
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return SCPE_ARG;
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val[0] = val[0] | (reg << 6);
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break;
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default:
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return SCPE_ARG;
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}
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