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More General cleanup migrate to using sim_printf vs separate calls to printf and fprintf(sim_log).

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This commit is contained in:
Mark Pizzolato
2014-10-24 14:37:37 -07:00
parent ebf53c9cda
commit 995ab8f1e2
23 changed files with 118 additions and 117 deletions
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38
PDQ-3/pdq3_cpu.c
View File

@@ -236,7 +236,7 @@ static void AdjustRefCount(uint8 segno, int incr) {
uint16 sib = GetSIB(segno);
uint16 ref = Get(sib + OFF_SEGREFS);
Put(sib + OFF_SEGREFS, ref + incr);
//printf("ref(%x) %s = %d\n",segno,incr>0 ? "increment":"decrement", ref+incr);
//sim_printf("ref(%x) %s = %d\n",segno,incr>0 ? "increment":"decrement", ref+incr);
}
/* save CPU regs into TIB */
@@ -310,13 +310,13 @@ static t_stat rom_ignore(t_addr ea, uint16 data) {
t_stat cpu_boot(int32 unitnum, DEVICE *dptr) {
t_stat rc;
uint16 ctp, ssv, rq;
printf("BOOT CPU\n");
sim_printf("BOOT CPU\n");
cpu_reset(dptr);
dbg_init();
/* boot from external ROM? */
if (reg_fc68 != 0) {
// printf("Booting from HDT ROM\n");
// sim_printf("Booting from HDT ROM\n");
/* cf. WD9593_PasIII_OSRef_Jul82.pdf */
Read(reg_fc68, 0, &ctp, DBG_NONE);
Read(reg_fc68, 1, &ssv, DBG_NONE);
@@ -343,7 +343,7 @@ void cpu_finishAutoload() {
/* CPU reset */
t_stat cpu_reset (DEVICE *dptr) {
printf("CPU RESET\n");
sim_printf("CPU RESET\n");
sim_brk_types = SWMASK('E')|SWMASK('R')|SWMASK('W');
sim_brk_dflt = SWMASK('E');
@@ -368,10 +368,10 @@ t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw) {
if (seg==0) seg = NIL;
addr = MAKE_BADDR(seg,off);
// printf("Examine: addr=%x seg=%x off=%x\n",addr,seg,off);
// printf("sw=%x, isword=%d\n",sw, ADDR_ISWORD(addr));
// sim_printf("Examine: addr=%x seg=%x off=%x\n",addr,seg,off);
// sim_printf("sw=%x, isword=%d\n",sw, ADDR_ISWORD(addr));
if (ADDR_ISWORD(addr) || (sw & SWMASK('W'))) {
// printf("addr=%x seg=%x off=%x\n",addr,seg,off);
// sim_printf("addr=%x seg=%x off=%x\n",addr,seg,off);
if (off >= memorysize ||
ReadEx(off, 0, &data) != SCPE_OK) return SCPE_IOERR;
} else if (!ADDR_ISWORD(addr) || (sw & SWMASK('B'))) {
@@ -427,7 +427,7 @@ static t_stat ssr_write(t_addr ioaddr, uint16 data) {
sim_debug(DBG_CPU_INT2, &cpu_dev, DBG_PCFORMAT1 "Acknowledge INTVL\n", DBG_PC);
}
if (isbitset(data,SSR_BIT3))
printf("Warning: Attempt to set SSR bit 3\n");
sim_printf("Warning: Attempt to set SSR bit 3\n");
if (isbitset(data,SSR_PWRF)) {
clrbit(reg_ssr,SSR_PWRF);
sim_debug(DBG_CPU_INT2, &cpu_dev, DBG_PCFORMAT1 "Acknowledge PWRF\n", DBG_PC);
@@ -449,7 +449,7 @@ static t_stat ssr_write(t_addr ioaddr, uint16 data) {
static t_stat ses_read(t_addr ioaddr, uint16 *data)
{
*data = reg_ses;
// printf("ses is %x\n",reg_ses);
// sim_printf("ses is %x\n",reg_ses);
return SCPE_OK;
}
@@ -497,7 +497,7 @@ void cpu_assertInt(int level, t_bool tf) {
t_stat cpu_raiseInt(int level) {
if (level > 15) {
printf("Implementation error: raiseInt with level>15! Need fix\n");
sim_printf("Implementation error: raiseInt with level>15! Need fix\n");
exit(1);
}
@@ -661,14 +661,14 @@ static float PopF() {
T_FLCVT t;
t.i[1] = Pop();
t.i[0] = Pop();
// printf("POPF: %.6e\n",t.f);
// sim_printf("POPF: %.6e\n",t.f);
return t.f;
};
static void PushF(float f) {
T_FLCVT t;
t.f = f;
// printf("PUSHF: %.6e\n",t.f);
// sim_printf("PUSHF: %.6e\n",t.f);
Push(t.i[0]);
Push(t.i[1]);
}
@@ -703,11 +703,11 @@ static void DoCXG(uint8 segno, uint8 procno) {
uint8 osegno = (uint8)GetSegno(); /* obtain segment of caller to be set into MSCW */
uint16 osegb = reg_segb;
// printf("CXG: seg=%d proc=%d, osegno=%d\n",segno,procno,osegno);
// sim_printf("CXG: seg=%d proc=%d, osegno=%d\n",segno,procno,osegno);
ptbl = SetSEGB(segno); /* get ptbl of new segment */
AdjustRefCount(segno,1);
// printf("CXG: ptbl=%x, reg_segb=%x\n",ptbl,reg_segb);
// sim_printf("CXG: ptbl=%x, reg_segb=%x\n",ptbl,reg_segb);
reg_ipc = createMSCW(ptbl, procno, reg_bp, osegno, osegb); /* call new segment */
sim_interval -= 63; /* actually 63.2 */
}
@@ -744,10 +744,10 @@ static uint16 createMSCW(uint16 ptbl, uint8 procno, uint16 stat, uint8 segno, ui
uint16 procstart = Get(ptbl - procno); /* word index into segment */
uint16 datasz = Get(reg_segb + procstart); /* word index */
dbg_segtrack(reg_segb);
// printf("createMSCW: ptbl=%x procno=%d stat=%x segno=%x\n",ptbl,procno,stat,segno);
// sim_printf("createMSCW: ptbl=%x procno=%d stat=%x segno=%x\n",ptbl,procno,stat,segno);
if (reg_sp < reg_splow || (datasz+MSCW_SZ) > (reg_sp-reg_splow)) { /* verify enough space on stack */
// printf("Stk overflow in mscw: sp=%x spl=%x ds=%d dsm=%d sp-spl=%d\n",reg_sp,reg_splow,datasz,datasz+MSCW_SZ, reg_sp-reg_splow);
// sim_printf("Stk overflow in mscw: sp=%x spl=%x ds=%d dsm=%d sp-spl=%d\n",reg_sp,reg_splow,datasz,datasz+MSCW_SZ, reg_sp-reg_splow);
Raise(PASERROR_STKOVFL); return reg_ipc;
}
reg_sp = reg_sp - MSCW_SZ - datasz; /* allocate space on stack for local data and MSCW */
@@ -1626,10 +1626,10 @@ static t_stat DoInstr(void) {
} else if (w == -2) {
reg_ssv = t1;
} else if (w == -1) {
// printf("SPR Taskswitch reg_ctp=%x\n",t1);
// sim_printf("SPR Taskswitch reg_ctp=%x\n",t1);
reg_rq = t1;
taskswitch5();
// printf("SPR Taskswitch done reg_ctp=%x reg_rq=%x\n",reg_ctp,reg_rq);
// sim_printf("SPR Taskswitch done reg_ctp=%x reg_rq=%x\n",reg_ctp,reg_rq);
cyc = 53.2;
break; /* mustn't fall through reg_sp +=2 */
} else if (w >= 1) {
@@ -1726,7 +1726,7 @@ t_stat sim_instr(void)
reg_intpending |= reg_intlatch;
if (reg_intpending) {
if ((rc = cpu_processInt()) != SCPE_OK) {
printf("processint returns %d\n",rc); fflush(stdout);
sim_printf("processint returns %d\n",rc); fflush(stdout);
break;
}
}

2
PDQ-3/pdq3_debug.c
View File

@@ -197,7 +197,7 @@ t_stat dbg_dump_segtbl(FILE* fd) {
t_stat rc;
if (reg_ssv < 0x2030 || reg_ssv > 0xf000) {
printf("Cannot list segments in bootloader: incomplete tables\n");
sim_printf("Cannot list segments in bootloader: incomplete tables\n");
return SCPE_NXM;
}

44
PDQ-3/pdq3_fdc.c
View File

@@ -267,7 +267,7 @@ DEVICE fdc_dev = {
t_stat fdc_boot(int32 unitnum, DEVICE *dptr) {
if (unitnum < 0 || (uint32)unitnum > dptr->numunits)
return SCPE_NXUN;
// printf("BOOT FDC%d\n",unitnum);
// sim_printf("BOOT FDC%d\n",unitnum);
return fdc_autoload(unitnum);
}
@@ -288,14 +288,14 @@ t_stat fdc_attach(UNIT *uptr, char *cptr) {
if (uptr->capac > 0) {
fgets(header, 4, uptr->fileref);
if (strncmp(header, "IMD", 3) != 0) {
printf("FDC: Only IMD disk images are supported\n");
sim_printf("FDC: Only IMD disk images are supported\n");
fdc_drv[i].dr_unit = NULL;
return SCPE_OPENERR;
}
} else {
/* create a disk image file in IMD format. */
if (pdq3_diskCreate(uptr->fileref, "SIMH pdq3_fdc created") != SCPE_OK) {
printf("FDC: Failed to create IMD disk.\n");
sim_printf("FDC: Failed to create IMD disk.\n");
fdc_drv[i].dr_unit = NULL;
return SCPE_OPENERR;
}
@@ -305,7 +305,7 @@ t_stat fdc_attach(UNIT *uptr, char *cptr) {
DBG_PC, cptr, uptr->capac);
fdc_drv[i].dr_imd = diskOpenEx(uptr->fileref, isbitset(uptr->flags,UNIT_FDC_VERBOSE), &fdc_dev, DBG_FD_IMD, DBG_FD_IMD2);
if (fdc_drv[i].dr_imd == NULL) {
printf("FDC: IMD disk corrupt.\n");
sim_printf("FDC: IMD disk corrupt.\n");
fdc_drv[i].dr_unit = NULL;
return SCPE_OPENERR;
}
@@ -476,11 +476,11 @@ static t_bool dma_transfer_to_ram(uint8 *buf, int bufsize) {
}
if (isbitclr(reg_dma_ctrl,DMA_CTRL_IOM))
printf("Warning: wrong IOM direction for DMA transfer to RAM\n");
sim_printf("Warning: wrong IOM direction for DMA transfer to RAM\n");
for (i=0; i<bufsize; i++) {
data = buf[i];
// printf("addr=%04x data=%02x\n",_reg_dma_addr, data);
// sim_printf("addr=%04x data=%02x\n",_reg_dma_addr, data);
if (WriteB(0, _reg_dma_addr++, data, FALSE) != SCPE_OK) {
(void)dma_abort(FALSE);
@@ -514,7 +514,7 @@ static t_bool dma_transfer_from_ram(uint8 *buf, int bufsize) {
DBG_PC, _reg_dma_addr/2, (_reg_dma_addr + xfersz - 1)/2);
if (isbitset(reg_dma_ctrl,DMA_CTRL_IOM))
printf("Warning: wrong IOM direction for DMA transfer from RAM\n");
sim_printf("Warning: wrong IOM direction for DMA transfer from RAM\n");
for (i=0; i<bufsize; i++) {
if (ReadB(0, _reg_dma_addr++, &data, FALSE)) {
@@ -737,7 +737,7 @@ t_stat fdc_svc(UNIT *uptr) {
return fdc_restartmulti(curdrv,FDC_WAIT_WRITENEXT);
break;
default:
printf("fdc_svc: Fix me - command not yet implemented: cmd=0x%x\n", reg_fdc_cmd);
sim_printf("fdc_svc: Fix me - command not yet implemented: cmd=0x%x\n", reg_fdc_cmd);
}
clrbit(reg_fdc_status,FDC_ST1_BUSY);
@@ -773,7 +773,7 @@ t_stat fdc_binit() {
t_stat fdc_reset (DEVICE *dptr) {
int i;
DEVCTXT* ctxt = (DEVCTXT*)dptr->ctxt;
// printf("RESET FDC\n");
// sim_printf("RESET FDC\n");
if (dptr->flags & DEV_DIS)
del_ioh(ctxt->ioi);
@@ -904,7 +904,7 @@ static t_stat fdc_docmd(uint16 data) {
/* type III commands */
default:
printf("fdc_docmd: Fix me - command not yet implemented: cmd=0x%x\n", reg_fdc_cmd);
sim_printf("fdc_docmd: Fix me - command not yet implemented: cmd=0x%x\n", reg_fdc_cmd);
setbit(reg_fdc_status, FDC_ST2_BUSY);
return SCPE_NOFNC;
@@ -991,7 +991,7 @@ t_stat fdc_write(t_addr ioaddr, uint16 data) {
break;
case 9: /* dma status */
if (isbitset(reg_dma_status,DMA_ST_BUSY))
printf("Warning: DMA: write status while BUSY\n");
sim_printf("Warning: DMA: write status while BUSY\n");
reg_dma_status = data & 0x8f;
break;
case 0x0a: /* count low */
@@ -1088,7 +1088,7 @@ t_stat pdq3_diskCreate(FILE *fileref, char *ctlr_comment) {
}
if(sim_fsize(fileref) != 0) {
printf("PDQ3_IMD: Disk image already has data, do you want to overwrite it? ");
sim_printf("PDQ3_IMD: Disk image already has data, do you want to overwrite it? ");
answer = getchar();
if((answer != 'y') && (answer != 'Y')) {
@@ -1097,15 +1097,15 @@ t_stat pdq3_diskCreate(FILE *fileref, char *ctlr_comment) {
}
if((curptr = comment = calloc(1, MAX_COMMENT_LEN)) == 0) {
printf("PDQ3_IMD: Memory allocation failure.\n");
sim_printf("PDQ3_IMD: Memory allocation failure.\n");
return (SCPE_MEM);
}
printf("PDQ3_IMD: Enter a comment for this disk.\n"
sim_printf("PDQ3_IMD: Enter a comment for this disk.\n"
"PDQ3_IMD: Terminate with a '.' on an otherwise blank line.\n");
remaining = MAX_COMMENT_LEN;
do {
printf("IMD> ");
sim_printf("IMD> ");
fgets(curptr, remaining - 3, stdin);
if (strcmp(curptr, ".\n") == 0) {
remaining = 0;
@@ -1135,12 +1135,12 @@ t_stat pdq3_diskCreate(FILE *fileref, char *ctlr_comment) {
fflush(fileref);
if((myDisk = diskOpen(fileref, 0)) == NULL) {
printf("PDQ3_IMD: Error opening disk for format.\n");
sim_printf("PDQ3_IMD: Error opening disk for format.\n");
return(SCPE_OPENERR);
}
if(pdq3_diskFormat(myDisk) != SCPE_OK) {
printf("PDQ3_IMD: error formatting disk.\n");
sim_printf("PDQ3_IMD: error formatting disk.\n");
}
return diskClose(&myDisk);
@@ -1151,25 +1151,25 @@ t_stat pdq3_diskFormat(DISK_INFO *myDisk) {
uint8 sector_map[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26};
uint32 flags;
printf("PDQ3_IMD: Formatting disk in PDQ3 format.\n");
sim_printf("PDQ3_IMD: Formatting disk in PDQ3 format.\n");
/* format first track as 26 sectors with 128 bytes */
if((trackWrite(myDisk, 0, 0, 26, 128, sector_map, IMD_MODE_500K_FM, 0xE5, &flags)) != 0) {
printf("PDQ3_IMD: Error formatting track %d\n", i);
sim_printf("PDQ3_IMD: Error formatting track %d\n", i);
return SCPE_IOERR;
}
putchar('.');
sim_printf(".");
/* format the remaining tracks as 26 sectors with 256 bytes */
for(i=1;i<77;i++) {
if((trackWrite(myDisk, i, 0, 26, 256, sector_map, IMD_MODE_500K_MFM, 0xE5, &flags)) != 0) {
printf("PDQ3_IMD: Error formatting track %d\n", i);
sim_printf("PDQ3_IMD: Error formatting track %d\n", i);
return SCPE_IOERR;
} else {
putchar('.');
}
}
printf("\nPDQ3_IMD: Format Complete.\n");
sim_printf("\nPDQ3_IMD: Format Complete.\n");
return SCPE_OK;
}