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Code Releases Activity

Altair8800: Adds new MITS 88-ACR (ACR) cassette device

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BUS: Update formatting
SIO: Do not attach to BUS when disabled
Changed CONST to const
This commit is contained in:
Patrick Linstruth 2026-01-02 08:18:21 -05:00
parent c31ea266e2
commit 99a9a74e48
20 changed files with 521 additions and 156 deletions
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1
Altair8800/altair8800_sys.c
View File

@ -73,6 +73,7 @@ DEVICE *sim_devices[] = {
&mdsk_dev,
&m2sio0_dev,
&m2sio1_dev,
&acr_dev,
&sio_dev,
&sbc200_dev,
&tarbell_dev,

3
Altair8800/altair8800_sys.h
View File

@ -47,6 +47,7 @@ extern DEVICE po_dev;
extern DEVICE mdsk_dev;
extern DEVICE m2sio0_dev;
extern DEVICE m2sio1_dev;
extern DEVICE acr_dev;
extern DEVICE sio_dev;
extern DEVICE sbc200_dev;
extern DEVICE tarbell_dev;
@ -60,7 +61,7 @@ extern int32 sys_find_unit_index(UNIT* uptr);
extern void sys_set_cpu_instr(t_stat (*routine)(void));
extern void sys_set_cpu_pc(REG *reg);
extern void sys_set_cpu_pc_value(t_value (*routine)(void));
extern void sys_set_cpu_parse_sym(t_stat (*routine)(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw));
extern void sys_set_cpu_parse_sym(t_stat (*routine)(const char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw));
extern void sys_set_cpu_dasm(int32 (*routine)(char *S, const uint32 *val, const int32 addr));
extern void sys_set_cpu_is_subroutine_call(t_bool (*routine)(t_addr **ret_addrs));
extern char *sys_strupr(const char *str);

245
Altair8800/mits_acr.c Normal file
View File

@ -0,0 +1,245 @@
/* mits_acr.c: MITS Altair 8800 88-ACR
Copyright (c) 2025 Patrick A. Linstruth
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
PETER SCHORN BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Patrick Linstruth shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Patrick Linstruth.
History:
27-Dec-2025 Initial version
*/
#include "sim_defs.h"
#include "s100_bus.h"
#include "mits_acr.h"
#define DEVICE_NAME "ACR"
static int32 poc = TRUE; /* Power On Clear */
static int32 rdr = 0x00; /* Receive Data Register */
static int32 rdre = ACR_RDRE; /* Receive Data Register Empty Bit */
static t_stat acr_reset (DEVICE *dptr);
static t_stat acr_attach (UNIT *uptr, const char *cptr);
static t_stat acr_detach (UNIT *uptr);
static void acr_rdr ();
static int32 acr_io (const int32 addr, const int32 rw, const int32 data);
static int32 acr_data (const int32 addr, const int32 rw, const int32 data);
static t_stat acr_rewind (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
static t_stat acr_show_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
static t_stat acr_attach_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
static const char* acr_description(DEVICE *dptr) {
return "MITS 88-ACR";
}
static RES acr_res = { ACR_IOBASE, ACR_IOSIZE, 0, 0, NULL };
static UNIT acr_unit = {
UDATA (NULL, UNIT_ATTABLE | UNIT_ROABLE | UNIT_ACR_VERBOSE, 0)
};
static REG acr_reg[] = {
{ NULL }
};
static MTAB acr_mod[] = {
{ UNIT_ACR_VERBOSE, UNIT_ACR_VERBOSE, "VERBOSE", "VERBOSE", NULL, NULL, NULL, "Enable verbose messages" },
{ UNIT_ACR_VERBOSE, 0, "QUIET", "QUIET", NULL, NULL, NULL, "Disable verbose messages" },
{ MTAB_XTD | MTAB_VDV, 0, "IOBASE", "IOBASE", &set_iobase, &show_iobase, NULL, "Sets MITS ACR base I/O address" },
{ MTAB_XTD | MTAB_VUN, 0, NULL, "REWIND", &acr_rewind, NULL, NULL, "Rewind cassette" },
{ 0 }
};
/* Debug Flags */
static DEBTAB acr_dt[] = {
{ NULL, 0 }
};
DEVICE acr_dev = {
DEVICE_NAME, &acr_unit, acr_reg, acr_mod,
1, ADDRRADIX, ADDRWIDTH, 1, DATARADIX, DATAWIDTH,
NULL, NULL, &acr_reset, NULL,
&acr_attach, &acr_detach, &acr_res,
(DEV_DISABLE | DEV_DIS), 0,
acr_dt, NULL, NULL, &acr_show_help, &acr_attach_help, NULL, &acr_description
};
static t_stat acr_reset(DEVICE *dptr) {
if (dptr->flags & DEV_DIS) { /* Disable Device */
s100_bus_remio(acr_res.io_base, acr_res.io_size, &acr_io);
poc = TRUE;
return SCPE_OK;
}
if (poc) {
s100_bus_addio(acr_res.io_base, acr_res.io_size, &acr_io, DEVICE_NAME);
poc = FALSE;
}
rdre = ACR_RDRE; /* Receive Data Register Empty */
return SCPE_OK;
}
static t_stat acr_attach(UNIT *uptr, const char *cptr)
{
t_stat r;
rdre = ACR_RDRE;
if ((r = attach_unit(uptr, cptr)) == SCPE_OK) {
acr_rdr();
}
return r;
}
static t_stat acr_detach(UNIT *uptr)
{
return detach_unit(uptr);
}
static void acr_rdr()
{
t_stat ch;
if (acr_unit.fileref != NULL) { /* attached to a file? */
if (rdre) { /* receive data register empty? */
ch = getc(acr_unit.fileref);
if (ch == EOF) {
rdre = ACR_RDRE;
} else {
rdre = 0x00; /* indicate character available */
rdr = ch; /* store character in register */
}
}
}
}
static int32 acr_io(const int32 addr, const int32 rw, const int32 data)
{
if (addr & 0x01) {
return acr_data(addr, rw, data);
}
if (rw == S100_IO_READ) { /* Return status */
return rdre;
}
return 0xff;
}
static int32 acr_data(const int32 addr, const int32 rw, const int32 data)
{
t_stat ch;
if (rw == S100_IO_READ) {
ch = rdr;
rdre = ACR_RDRE; /* Receive data register empty */
acr_rdr(); /* Check for another character */
return ch;
}
if (acr_unit.fileref != NULL) { /* attached to a file? */
fputc(data, acr_unit.fileref);
}
else {
sim_putchar(data);
}
return 0xff;
}
static t_stat acr_rewind(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
{
if (acr_unit.fileref != NULL) {
rewind(acr_unit.fileref);
if (acr_unit.flags & UNIT_ACR_VERBOSE) {
sim_printf("TAPE is rewound\n");
}
}
else {
sim_printf("No file attached to %s device.\n", DEVICE_NAME);
}
return SCPE_OK;
}
static t_stat acr_show_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
{
fprintf(st, "\n88-ACR (%s)\n", DEVICE_NAME);
fprint_set_help(st, dptr);
fprint_show_help(st, dptr);
fprint_reg_help(st, dptr);
return SCPE_OK;
}
static t_stat acr_attach_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
{
fprintf(st, "\n88-ACR (%s)\n\n", DEVICE_NAME);
fprintf(st, "The %s device simulates the MITS ACR Audio Cassette Interface\n", DEVICE_NAME);
fprintf(st, "and cassette tape recorder.\n");
fprintf(st, "\nATTACH %s <filename>\n\n", DEVICE_NAME);
fprintf(st, " Inserts a tape into the cassette recorder. Files attached to\n");
fprintf(st, " the %s device are binary files that contain the contants of\n", DEVICE_NAME);
fprintf(st, " the data stored on the tape.\n");
fprintf(st, "\nDETACH %s\n\n", DEVICE_NAME);
fprintf(st, " Removes a tape from the cassette recorder.\n\n");
fprintf(st, "\nSHOW %s TAPE\n\n", DEVICE_NAME);
fprintf(st, " Shows the current status of the %s device.\n", DEVICE_NAME);
fprintf(st, "\nExample:\n\n");
fprintf(st, "SET %s ENA\n", DEVICE_NAME);
fprintf(st, "ATTACH %s BASIC Ver 1-0.tap\n", DEVICE_NAME);
fprintf(st, "HEXLOAD LOAD10.HEX\n");
fprintf(st, "SET SIO ENA\n");
fprintf(st, "SET SIO BOARD=SIO\n");
fprintf(st, "SET SIO CONSOLE\n");
fprintf(st, "BREAK -M 117F\n");
fprintf(st, "G 1800\n");
fprintf(st, "G 0\n\n");
fprintf(st, "This example loads ALTAIR BASIC 1.0 from tape using the %s device.\n", DEVICE_NAME);
fprintf(st, "The files are available from:\n\n");
fprintf(st, "https://deramp.com/downloads/altair/software/papertape_cassette/\n");
return SCPE_OK;
}

42
Altair8800/mits_acr.h Normal file
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@ -0,0 +1,42 @@
/* mits_acr.h
Copyright (c) 2025 Patrick A. Linstruth
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
PETER SCHORN BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Except as contained in this notice, the name of Patrick Linstruth shall not
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Patrick Linstruth.
History:
12/27/25 Initial version
*/
#ifndef MITS_ACR_H_
#define MITS_ACR_H_
#define UNIT_ACR_V_VERBOSE (UNIT_V_UF+0)
#define UNIT_ACR_VERBOSE (1 << UNIT_ACR_V_VERBOSE)
#define ACR_IOBASE 0x06
#define ACR_IOSIZE 2
#define ACR_RDRE 0x01
#endif

4
Altair8800/mits_dsk.c
View File

@ -137,7 +137,7 @@ static int32 mdsk12(const int32 port, const int32 io, const int32 data);
static t_stat mdsk_boot(int32 unitno, DEVICE *dptr);
static t_stat mdsk_reset(DEVICE *dptr);
static t_stat mdsk_attach(UNIT *uptr, CONST char *cptr);
static t_stat mdsk_attach(UNIT *uptr, const char *cptr);
static t_stat mdsk_show_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
static const char* mdsk_description(DEVICE *dptr);
@ -305,7 +305,7 @@ static t_stat mdsk_reset(DEVICE *dptr)
}
/* mdsk_attach - determine type of drive attached based on disk image size */
static t_stat mdsk_attach(UNIT *uptr, CONST char *cptr)
static t_stat mdsk_attach(UNIT *uptr, const char *cptr)
{
int32 thisUnitIndex;
int32 imageSize;

20
Altair8800/s100_bram.c
View File

@ -37,14 +37,14 @@ static t_stat bram_ex (t_value *vptr, t_addr addr, UNIT *uptr, in
static int32 bram_io (const int32 addr, const int32 rw, const int32 data);
static int32 bram_memio (const int32 addr, const int32 rw, const int32 data);
static t_stat bram_set_banks (int32 banks);
static t_stat bram_clear_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat bram_enable_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat bram_randomize_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat bram_banks_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat bram_clear_command (UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat bram_enable_command (UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat bram_randomize_command (UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat bram_banks_command (UNIT *uptr, int32 value, const char *cptr, void *desc);
static void bram_addio (int32 type);
static void bram_remio (int32 type);
static t_stat bram_set_type (int32 type);
static t_stat bram_type_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat bram_type_command (UNIT *uptr, int32 value, const char *cptr, void *desc);
static void bram_clear (void);
static void bram_randomize (void);
static t_stat bram_show_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
@ -363,7 +363,7 @@ static t_stat bram_set_type(int32 type)
return SCPE_OK;
}
static t_stat bram_type_command(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat bram_type_command(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
return bram_set_type(value);
}
@ -385,7 +385,7 @@ static t_stat bram_set_banks(int32 banks) {
return SCPE_OK;
}
static t_stat bram_banks_command(UNIT *uptr, int32 value, CONST char *cptr, void *desc) {
static t_stat bram_banks_command(UNIT *uptr, int32 value, const char *cptr, void *desc) {
int32 result, banks;
if (cptr == NULL) {
@ -402,7 +402,7 @@ static t_stat bram_banks_command(UNIT *uptr, int32 value, CONST char *cptr, void
return SCPE_ARG | SCPE_NOMESSAGE;
}
static t_stat bram_enable_command(UNIT *uptr, int32 value, CONST char *cptr, void *desc) {
static t_stat bram_enable_command(UNIT *uptr, int32 value, const char *cptr, void *desc) {
int32 size;
t_addr start, end;
@ -437,14 +437,14 @@ static t_stat bram_enable_command(UNIT *uptr, int32 value, CONST char *cptr, voi
return SCPE_OK;
}
static t_stat bram_clear_command(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat bram_clear_command(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
bram_clear();
return SCPE_OK;
}
static t_stat bram_randomize_command(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat bram_randomize_command(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
bram_randomize();

118
Altair8800/s100_bus.c
View File

@ -23,6 +23,9 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Patrick Linstruth.
History:
07-Nov-2025 PAL Initial version
*/
#include "sim_defs.h"
@ -33,12 +36,12 @@
static t_stat bus_reset (DEVICE *dptr);
static t_stat bus_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
static t_stat bus_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
static t_stat bus_cmd_memory (int32 flag, CONST char *cptr);
static t_stat bus_show_config (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat bus_show_console (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat bus_cmd_memory (int32 flag, const char *cptr);
static t_stat bus_show_config (FILE *st, UNIT *uptr, int32 val, const void *desc);
static t_stat bus_show_console (FILE *st, UNIT *uptr, int32 val, const void *desc);
static t_stat bus_show_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
static t_stat bus_hexload_command (int32 flag, CONST char *cptr);
static t_stat bus_hexsave_command (int32 flag, CONST char *cptr);
static t_stat bus_hexload_command (int32 flag, const char *cptr);
static t_stat bus_hexsave_command (int32 flag, const char *cptr);
static t_stat hexload (const char *filename, t_addr bias);
static t_stat hexsave (FILE *outFile, t_addr start, t_addr end);
@ -63,12 +66,12 @@ uint8 dataBus[MAX_INT_VECTORS]; /* Data bus value */
IDEV idev_in[MAXPAGE];
IDEV idev_out[MAXPAGE];
int32 nulldev(CONST int32 addr, CONST int32 io, CONST int32 data) { return 0xff; }
int32 nulldev(const int32 addr, const int32 io, const int32 data) { return 0xff; }
/* Which UNIT is the CONSOLE */
UNIT *bus_console = NULL;
static CONST char* bus_description(DEVICE *dptr) {
static const char* bus_description(DEVICE *dptr) {
return "S100 Bus";
}
@ -162,9 +165,9 @@ static t_stat bus_dep(t_value val, t_addr addr, UNIT *uptr, int32 sw)
return SCPE_OK;
}
static t_stat bus_show_config(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
static t_stat bus_show_config(FILE *st, UNIT *uptr, int32 val, const void *desc)
{
CONST char *last = NULL;
const char *last = NULL;
int i, spage, epage;
/* show memory */
@ -205,7 +208,7 @@ static t_stat bus_show_config(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
return SCPE_OK;
}
static t_stat bus_show_console(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
static t_stat bus_show_console(FILE *st, UNIT *uptr, int32 val, const void *desc)
{
/* show current CONSOLE unit */
fprintf(st, "CONSOLE Unit: %s\n", (bus_console == NULL) ? "NONE" : sim_uname(bus_console));
@ -225,7 +228,7 @@ void s100_bus_get_idev(int32 port, IDEV *idev_in, IDEV *idev_out)
}
}
t_stat s100_bus_addio(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32), CONST char *name)
t_stat s100_bus_addio(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32), const char *name)
{
s100_bus_addio_in(port, size, routine, name);
s100_bus_addio_out(port, size, routine, name);
@ -233,7 +236,7 @@ t_stat s100_bus_addio(int32 port, int32 size, int32 (*routine)(CONST int32, CONS
return SCPE_OK;
}
t_stat s100_bus_addio_in(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32), CONST char *name)
t_stat s100_bus_addio_in(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32), const char *name)
{
int i;
@ -249,7 +252,7 @@ t_stat s100_bus_addio_in(int32 port, int32 size, int32 (*routine)(CONST int32, C
return SCPE_OK;
}
t_stat s100_bus_addio_out(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32), CONST char *name)
t_stat s100_bus_addio_out(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32), const char *name)
{
int i;
@ -266,7 +269,7 @@ t_stat s100_bus_addio_out(int32 port, int32 size, int32 (*routine)(CONST int32,
}
t_stat s100_bus_remio(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32))
t_stat s100_bus_remio(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32))
{
s100_bus_remio_in(port, size, routine);
s100_bus_remio_out(port, size, routine);
@ -274,7 +277,7 @@ t_stat s100_bus_remio(int32 port, int32 size, int32 (*routine)(CONST int32, CONS
return SCPE_OK;
}
t_stat s100_bus_remio_in(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32))
t_stat s100_bus_remio_in(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32))
{
int i;
@ -292,7 +295,7 @@ t_stat s100_bus_remio_in(int32 port, int32 size, int32 (*routine)(CONST int32, C
return SCPE_OK;
}
t_stat s100_bus_remio_out(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32))
t_stat s100_bus_remio_out(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32))
{
int i;
@ -323,7 +326,7 @@ void s100_bus_get_mdev(int32 addr, MDEV *mdev)
}
t_stat s100_bus_addmem(int32 baseaddr, uint32 size,
int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data), CONST char *name)
int32 (*routine)(const int32 addr, const int32 rw, const int32 data), const char *name)
{
int32 page;
uint32 i;
@ -346,7 +349,7 @@ t_stat s100_bus_addmem(int32 baseaddr, uint32 size,
return SCPE_OK;
}
t_stat s100_bus_setmem_dflt(int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data), CONST char *name)
t_stat s100_bus_setmem_dflt(int32 (*routine)(const int32 addr, const int32 rw, const int32 data), const char *name)
{
mdev_dflt.routine = routine;
mdev_dflt.name = name;
@ -355,7 +358,7 @@ t_stat s100_bus_setmem_dflt(int32 (*routine)(CONST int32 addr, CONST int32 rw, C
}
t_stat s100_bus_remmem(int32 baseaddr, uint32 size,
int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data))
int32 (*routine)(const int32 addr, const int32 rw, const int32 data))
{
int32 page;
uint32 i;
@ -372,7 +375,7 @@ t_stat s100_bus_remmem(int32 baseaddr, uint32 size,
return SCPE_OK;
}
t_stat s100_bus_remmem_dflt(int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data))
t_stat s100_bus_remmem_dflt(int32 (*routine)(const int32 addr, const int32 rw, const int32 data))
{
if (mdev_dflt.routine == routine) {
mdev_dflt.routine = &nulldev;
@ -474,7 +477,7 @@ void s100_bus_clr_nmi()
nmiInterrupt = FALSE;
}
static t_stat bus_cmd_memory(int32 flag, CONST char *cptr)
static t_stat bus_cmd_memory(int32 flag, const char *cptr)
{
char abuf[16];
t_addr lo, hi, last;
@ -536,12 +539,12 @@ static t_stat bus_cmd_memory(int32 flag, CONST char *cptr)
ALTAIRROM/NOALTAIRROM settings are ignored.
*/
t_stat sim_load(FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)
t_stat sim_load(FILE *fileref, const char *cptr, const char *fnam, int flag)
{
int32 i;
uint32 addr, cnt = 0, org;
t_addr j, lo, hi;
CONST char *result;
const char *result;
char gbuf[CBUFSIZE];
if (flag) { /* dump ram to file */
@ -593,7 +596,7 @@ t_stat sim_load(FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)
return SCPE_OK;
}
static t_stat bus_hexload_command(int32 flag, CONST char *cptr)
static t_stat bus_hexload_command(int32 flag, const char *cptr)
{
char filename[4*CBUFSIZE];
t_addr lo = 0, hi = 0;
@ -618,7 +621,7 @@ static t_stat bus_hexload_command(int32 flag, CONST char *cptr)
return SCPE_OK;
}
static t_stat bus_hexsave_command(int32 flag, CONST char *cptr)
static t_stat bus_hexsave_command(int32 flag, const char *cptr)
{
char filename[4*CBUFSIZE];
FILE *sfile;
@ -810,39 +813,46 @@ static t_stat hexsave(FILE *outFile, t_addr start, t_addr end)
*/
/* Set Memory Base Address routine */
t_stat set_membase(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
t_stat set_membase(UNIT *uptr, int32 val, const char *cptr, void *desc)
{
DEVICE *dptr;
RES *res;
uint32 newba;
t_stat r;
if (cptr == NULL)
if (cptr == NULL) {
return SCPE_ARG;
}
if (uptr == NULL)
if (uptr == NULL) {
return SCPE_IERR;
}
if ((dptr = find_dev_from_unit(uptr)) == NULL)
if ((dptr = find_dev_from_unit(uptr)) == NULL) {
return SCPE_IERR;
}
res = (RES *) dptr->ctxt;
if (res == NULL)
if (res == NULL) {
return SCPE_IERR;
}
newba = get_uint (cptr, 16, 0xFFFF, &r);
if (r != SCPE_OK)
if (r != SCPE_OK) {
return r;
}
if ((newba > 0xFFFF) || (newba % res->mem_size))
if ((newba > 0xFFFF) || (newba % res->mem_size)) {
return SCPE_ARG;
}
if (dptr->flags & DEV_DIS) {
sim_printf("device not enabled yet.\n");
res->mem_base = newba & ~(res->mem_size-1);
} else {
}
else {
dptr->flags |= DEV_DIS;
dptr->reset(dptr);
res->mem_base = newba & ~(res->mem_size-1);
@ -854,21 +864,24 @@ t_stat set_membase(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
}
/* Show Base Address routine */
t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
t_stat show_membase(FILE *st, UNIT *uptr, int32 val, const void *desc)
{
DEVICE *dptr;
RES *res;
if (uptr == NULL)
if (uptr == NULL) {
return SCPE_IERR;
}
if ((dptr = find_dev_from_unit(uptr)) == NULL)
if ((dptr = find_dev_from_unit(uptr)) == NULL) {
return SCPE_IERR;
}
res = (RES *) dptr->ctxt;
if (res == NULL)
if (res == NULL) {
return SCPE_IERR;
}
fprintf(st, "MEM=0x%04X-0x%04X", res->mem_base, res->mem_base + res->mem_size-1);
@ -876,34 +889,40 @@ t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
}
/* Set Memory Base Address routine */
t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
t_stat set_iobase(UNIT *uptr, int32 val, const char *cptr, void *desc)
{
DEVICE *dptr;
RES *res;
uint32 newba;
t_stat r;
if (cptr == NULL)
if (cptr == NULL) {
return SCPE_ARG;
}
if (uptr == NULL)
if (uptr == NULL) {
return SCPE_IERR;
}
if ((dptr = find_dev_from_unit(uptr)) == NULL)
if ((dptr = find_dev_from_unit(uptr)) == NULL) {
return SCPE_IERR;
}
res = (RES *) dptr->ctxt;
if (res == NULL)
if (res == NULL) {
return SCPE_IERR;
}
newba = get_uint (cptr, 16, 0xFF, &r);
if (r != SCPE_OK)
if (r != SCPE_OK) {
return r;
}
if ((newba > 0xFF) || (newba % res->io_size))
if ((newba > 0xFF) || (newba % res->io_size)) {
return SCPE_ARG;
}
if (dptr->flags & DEV_DIS) {
sim_printf("device not enabled yet.\n");
@ -920,21 +939,24 @@ t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
}
/* Show I/O Base Address routine */
t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, const void *desc)
{
DEVICE *dptr;
RES *res;
if (uptr == NULL)
if (uptr == NULL) {
return SCPE_IERR;
}
if ((dptr = find_dev_from_unit(uptr)) == NULL)
if ((dptr = find_dev_from_unit(uptr)) == NULL) {
return SCPE_IERR;
}
res = (RES *) dptr->ctxt;
if (res == NULL)
if (res == NULL) {
return SCPE_IERR;
}
fprintf(st, "I/O=0x%02X-0x%02X", res->io_base, res->io_base + res->io_size-1);

38
Altair8800/s100_bus.h
View File

@ -91,31 +91,31 @@ typedef struct {
/* data structure for IN/OUT instructions */
typedef struct idev {
int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data);
CONST char *name;
int32 (*routine)(const int32 addr, const int32 rw, const int32 data);
const char *name;
} IDEV;
typedef struct { /* Structure to describe memory device address space */
int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data);
CONST char *name; /* name of handler routine */
int32 (*routine)(const int32 addr, const int32 rw, const int32 data);
const char *name; /* name of handler routine */
} MDEV;
extern t_stat s100_bus_addio(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32), CONST char* name);
extern t_stat s100_bus_addio_in(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32), CONST char* name);
extern t_stat s100_bus_addio_out(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32), CONST char* name);
extern t_stat s100_bus_remio(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32));
extern t_stat s100_bus_remio_in(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32));
extern t_stat s100_bus_remio_out(int32 port, int32 size, int32 (*routine)(CONST int32, CONST int32, CONST int32));
extern t_stat s100_bus_addio(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32), const char* name);
extern t_stat s100_bus_addio_in(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32), const char* name);
extern t_stat s100_bus_addio_out(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32), const char* name);
extern t_stat s100_bus_remio(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32));
extern t_stat s100_bus_remio_in(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32));
extern t_stat s100_bus_remio_out(int32 port, int32 size, int32 (*routine)(const int32, const int32, const int32));
extern t_stat s100_bus_addmem(int32 baseaddr, uint32 size,
int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data), CONST char *name);
int32 (*routine)(const int32 addr, const int32 rw, const int32 data), const char *name);
extern t_stat s100_bus_remmem(int32 baseaddr, uint32 size,
int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data));
extern t_stat s100_bus_setmem_dflt(int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data), CONST char *name);
extern t_stat s100_bus_remmem_dflt(int32 (*routine)(CONST int32 addr, CONST int32 rw, CONST int32 data));
int32 (*routine)(const int32 addr, const int32 rw, const int32 data));
extern t_stat s100_bus_setmem_dflt(int32 (*routine)(const int32 addr, const int32 rw, const int32 data), const char *name);
extern t_stat s100_bus_remmem_dflt(int32 (*routine)(const int32 addr, const int32 rw, const int32 data));
extern void s100_bus_get_idev(int32 port, IDEV *idev_in, IDEV *idev_out);
extern void s100_bus_get_mdev(int32 addr, MDEV *mdev);
extern int32 nulldev(CONST int32 addr, CONST int32 io, CONST int32 data);
extern int32 nulldev(const int32 addr, const int32 io, const int32 data);
extern uint32 s100_bus_set_addr(uint32 pc);
extern uint32 s100_bus_get_addr(void);
@ -147,10 +147,10 @@ extern void s100_bus_clr_nmi(void);
#define sim_map_resource(a,b,c,d,e,f) s100_map_resource(a,b,c,d,e,f)
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat set_membase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat set_iobase(UNIT *uptr, int32 val, const char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, const void *desc);
extern t_stat set_membase(UNIT *uptr, int32 val, const char *cptr, void *desc);
extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, const void *desc);
extern void cpu_raise_interrupt(uint32 irq);
#endif

8
Altair8800/s100_cpu.c
View File

@ -46,14 +46,14 @@ static char *cpu_chipname[] = {
};
static t_stat (*cpu_instr)(void) = NULL;
static t_stat (*cpu_parse_sym)(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw) = NULL;
static t_stat (*cpu_parse_sym)(const char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw) = NULL;
static int32 (*cpu_dasm)(char *S, const uint32 *val, const int32 addr) = NULL;
static t_stat cpu_reset(DEVICE *dptr);
static void cpu_set_instr(t_stat (*routine)(void));
static void cpu_set_pc(REG *reg);
static void cpu_set_pc_value(t_value (*routine)(void));
static void cpu_set_parse_sym(t_stat (*routine)(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw));
static void cpu_set_parse_sym(t_stat (*routine)(const char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw));
static void cpu_set_dasm(int32 (*routine)(char *S, const uint32 *val, const int32 addr));
static void cpu_set_is_subroutine_call(t_bool (*routine)(t_addr **ret_addrs));
@ -190,7 +190,7 @@ static void cpu_set_pc_value(t_value (*routine)(void))
sim_vm_pc_value = routine;
}
static void cpu_set_parse_sym(t_stat (*routine)(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw))
static void cpu_set_parse_sym(t_stat (*routine)(const char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw))
{
cpu_parse_sym = routine;
}
@ -227,7 +227,7 @@ t_stat fprint_sym(FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw)
return 1 - r;
}
t_stat parse_sym(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
t_stat parse_sym(const char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
{
while (isspace(*cptr)) {
cptr++; /* absorb spaces */

2
Altair8800/s100_cpu.h
View File

@ -49,7 +49,7 @@ typedef struct {
ChipType *chiptype;
t_stat (*instr)(void);
t_value (*pc_val)(void);
t_stat (*parse_sym)(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw);
t_stat (*parse_sym)(const char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw);
int32 (*dasm)(char *S, const uint32 *val, const int32 addr);
t_bool (*isc)(t_addr **ret_addrs);
t_stat (*help)(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);

24
Altair8800/s100_ram.c
View File

@ -36,13 +36,13 @@ static t_stat ram_reset (DEVICE *dptr);
static t_stat ram_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
static t_stat ram_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
static int32 ram_memio (const int32 addr, const int32 rw, const int32 data);
static t_stat ram_default_ena (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat ram_default_dis (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat ram_default_ena (UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat ram_default_dis (UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat ram_set_memsize (int32 value);
static t_stat ram_clear_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat ram_enable_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat ram_randomize_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat ram_size_command (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat ram_clear_command (UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat ram_enable_command (UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat ram_randomize_command (UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat ram_size_command (UNIT *uptr, int32 value, const char *cptr, void *desc);
static void ram_clear (void);
static void ram_randomize (void);
static t_stat ram_show_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
@ -185,14 +185,14 @@ static uint32 GetBYTE(register uint32 Addr)
return M[Addr & ADDRMASK] & DATAMASK; /* RAM */
}
static t_stat ram_default_ena(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat ram_default_ena(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
s100_bus_setmem_dflt(&ram_memio, "RAM"); /* Set RAM as default memory device */
return SCPE_OK;
}
static t_stat ram_default_dis(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat ram_default_dis(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
s100_bus_remmem_dflt(&ram_memio); /* Remove RAM as default memory device */
@ -246,7 +246,7 @@ static void ram_randomize()
}
}
static t_stat ram_size_command(UNIT *uptr, int32 value, CONST char *cptr, void *desc) {
static t_stat ram_size_command(UNIT *uptr, int32 value, const char *cptr, void *desc) {
int32 size, result;
if (cptr == NULL) {
@ -263,7 +263,7 @@ static t_stat ram_size_command(UNIT *uptr, int32 value, CONST char *cptr, void *
return SCPE_ARG | SCPE_NOMESSAGE;
}
static t_stat ram_enable_command(UNIT *uptr, int32 value, CONST char *cptr, void *desc) {
static t_stat ram_enable_command(UNIT *uptr, int32 value, const char *cptr, void *desc) {
int32 size;
t_addr start, end;
@ -298,14 +298,14 @@ static t_stat ram_enable_command(UNIT *uptr, int32 value, CONST char *cptr, void
return SCPE_OK;
}
static t_stat ram_clear_command(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat ram_clear_command(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
ram_clear();
return SCPE_OK;
}
static t_stat ram_randomize_command(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat ram_randomize_command(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
ram_randomize();

24
Altair8800/s100_rom.c
View File

@ -44,12 +44,12 @@ static const char* rom_description (DEVICE *dptr);
static uint32 GetBYTE(register uint32 Addr);
static t_stat rom_enadis(int32 value, int32 ena);
static t_stat rom_ena(UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat rom_dis_dbl(UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat rom_dis_hdsk(UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat rom_dis_altmon(UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat rom_dis_turmon(UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat rom_show_list(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat rom_ena(UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat rom_dis_dbl(UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat rom_dis_hdsk(UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat rom_dis_altmon(UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat rom_dis_turmon(UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat rom_show_list(FILE *st, UNIT *uptr, int32 val, const void *desc);
static t_stat rom_show_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
static int32 M[MAXBANKSIZE];
@ -193,32 +193,32 @@ static t_stat rom_enadis(int32 value, int32 ena)
return SCPE_OK;
}
static t_stat rom_ena(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat rom_ena(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
return rom_enadis(value, TRUE);
}
static t_stat rom_dis_dbl(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat rom_dis_dbl(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
return rom_enadis(UNIT_ROM_DBL, FALSE);
}
static t_stat rom_dis_hdsk(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat rom_dis_hdsk(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
return rom_enadis(UNIT_ROM_HDSK, FALSE);
}
static t_stat rom_dis_turmon(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat rom_dis_turmon(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
return rom_enadis(UNIT_ROM_TURMON, FALSE);
}
static t_stat rom_dis_altmon(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat rom_dis_altmon(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
return rom_enadis(UNIT_ROM_ALTMON, FALSE);
}
static t_stat rom_show_list(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
static t_stat rom_show_list(FILE *st, UNIT *uptr, int32 val, const void *desc)
{
ROM *r = rom_table;

81
Altair8800/s100_sio.c
View File

@ -24,7 +24,8 @@
in this Software without prior written authorization from Patrick Linstruth.
History:
07-Nov-2025 Initial version
07-Nov-2025 PAL Initial version
23-Nov-2025 PAL Do not add IO to the BUS if device is disabled
*/
@ -73,15 +74,17 @@ static int32 sio_rdre; /* Receive Data Register Empty Flag */
static int32 sio_tdre; /* Transmit Buffer Full Empty */
static t_stat sio_reset(DEVICE *dptr);
static t_stat sio_addio(UNIT *uptr);
static t_stat sio_remio();
static int32 sio_io(const int32 addr, const int32 rw, const int32 data);
static int32 sio_io_in(const int32 addr);
static void sio_io_out(const int32 addr, int32 data);
static t_stat sio_set_board(UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat sio_set_type (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat sio_set_val(UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat sio_set_board(UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat sio_set_type (UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat sio_set_val(UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat sio_set_console(UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat sio_show_config(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat sio_show_list(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat sio_show_config(FILE *st, UNIT *uptr, int32 val, const void *desc);
static t_stat sio_show_list(FILE *st, UNIT *uptr, int32 val, const void *desc);
static t_stat sio_show_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
static const char* sio_description(DEVICE *dptr) {
@ -161,8 +164,9 @@ static t_stat sio_reset(DEVICE *dptr)
{
if (dptr->flags & DEV_DIS) { /* Disable Device */
if (sio_type != SIO_TYPE_NONE) {
s100_bus_remio(sio.stat, 1, &sio_io);
s100_bus_remio(sio.data, 1, &sio_io);
sio_remio();
sio_type = SIO_TYPE_NONE;
s100_bus_noconsole(&dptr->units[0]);
}
@ -188,11 +192,44 @@ static t_stat sio_reset(DEVICE *dptr)
sio_rdre = TRUE;
sio_tdre = TRUE;
sio_addio(&dptr->units[0]);
sim_debug(STATUS_MSG, dptr, "reset adapter.\n");
return SCPE_OK;
}
static t_stat sio_remio()
{
s100_bus_remio(sio.base + sio.stat, 1, &sio_io);
s100_bus_remio(sio.base + sio.data, 1, &sio_io);
return SCPE_OK;
}
static t_stat sio_addio(UNIT *uptr)
{
DEVICE *dptr;
if (uptr == NULL) {
return SCPE_IERR;
}
if ((dptr = find_dev_from_unit(uptr)) == NULL) {
return SCPE_IERR;
}
if (dptr->flags & DEV_DIS) {
sim_printf("%s device not enabled yet.\n", dptr->name);
}
else if (sio_type != SIO_TYPE_NONE) {
s100_bus_addio(sio.base + sio.stat, 1, &sio_io, SIO_SNAME"S");
s100_bus_addio(sio.base + sio.data, 1, &sio_io, SIO_SNAME"D");
}
return SCPE_OK;
}
static int32 sio_io(const int32 addr, const int32 rw, const int32 data)
{
int32 c;
@ -242,7 +279,7 @@ static void sio_io_out(const int32 addr, int32 data)
}
}
static t_stat sio_set_type(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat sio_set_type(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
int32 result, base;
@ -251,8 +288,7 @@ static t_stat sio_set_type(UNIT *uptr, int32 value, CONST char *cptr, void *desc
}
if (sio_type != SIO_TYPE_NONE) {
s100_bus_remio(sio.base + sio.stat, 1, &sio_io);
s100_bus_remio(sio.base + sio.data, 1, &sio_io);
sio_remio();
}
sio_type = value;
@ -277,14 +313,15 @@ static t_stat sio_set_type(UNIT *uptr, int32 value, CONST char *cptr, void *desc
}
}
s100_bus_addio(sio.base + sio.stat, 1, &sio_io, SIO_SNAME"S");
s100_bus_addio(sio.base + sio.data, 1, &sio_io, SIO_SNAME"D");
if (!(uptr->flags & UNIT_DIS)) {
sio_addio(uptr);
}
}
return SCPE_OK;
}
static t_stat sio_set_board(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat sio_set_board(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
char cbuf[10];
int i = 0;
@ -303,7 +340,7 @@ static t_stat sio_set_board(UNIT *uptr, int32 value, CONST char *cptr, void *des
return SCPE_ARG;
}
static t_stat sio_set_val(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat sio_set_val(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
uint32 val;
@ -311,6 +348,9 @@ static t_stat sio_set_val(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
return SCPE_ARG;
}
/* Remove current configuration */
sio_remio();
val &= DATAMASK;
switch (value) {
@ -351,12 +391,17 @@ static t_stat sio_set_val(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
sio.type = SIO_TYPE_CUST;
sio_type = SIO_TYPE_CUST;
/* Add new configuration */
if (!(uptr->flags & UNIT_DIS)) {
sio_addio(uptr);
}
return SCPE_OK;
}
static t_stat sio_set_console(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
if (value == UNIT_SIO_CONSOLE) {
if (value == UNIT_SIO_CONSOLE && !(uptr->flags & UNIT_DIS)) {
s100_bus_console(uptr);
}
else {
@ -366,7 +411,7 @@ static t_stat sio_set_console(UNIT *uptr, int32 value, const char *cptr, void *d
return SCPE_OK;
}
static t_stat sio_show_config(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
static t_stat sio_show_config(FILE *st, UNIT *uptr, int32 val, const void *desc)
{
if (sio_type != SIO_TYPE_NONE) {
sim_printf("SIO Base Address: %02X\n\n", sio.base);
@ -388,7 +433,7 @@ static t_stat sio_show_config(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
return SCPE_OK;
}
static t_stat sio_show_list(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
static t_stat sio_show_list(FILE *st, UNIT *uptr, int32 val, const void *desc)
{
int i;

26
Altair8800/s100_z80.c
View File

@ -131,11 +131,11 @@ static int32 poc = TRUE; /* Power On Clear */
#define INCR(val) IR_S = (IR_S & ~0x7f) | ((IR_S + (val)) & 0x7f)
/* function prototypes */
static t_stat z80_set_chiptype (UNIT *uptr, int32 value, CONST char *cptr, void *desc);
static t_stat z80_set_hist (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
static t_stat z80_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat z80_show (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat chip_show (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat z80_set_chiptype (UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat z80_set_hist (UNIT *uptr, int32 val, const char *cptr, void *desc);
static t_stat z80_show_hist (FILE *st, UNIT *uptr, int32 val, const void *desc);
static t_stat z80_show (FILE *st, UNIT *uptr, int32 val, const void *desc);
static t_stat chip_show (FILE *st, UNIT *uptr, int32 val, const void *desc);
static t_stat z80_reset(DEVICE *dptr);
static const char* z80_description(DEVICE *dptr);
@ -5732,7 +5732,7 @@ t_bool z80_is_pc_a_subroutine_call (t_addr **ret_addrs)
return FALSE;
}
static t_stat chip_show(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
static t_stat chip_show(FILE *st, UNIT *uptr, int32 val, const void *desc)
{
fprintf(st, z80_unit.flags & UNIT_Z80_OPSTOP ? "ITRAP, " : "NOITRAP, ");
if ((z80_chiptype >= 0) && (z80_chiptype < NUM_CHIP_TYPE)) {
@ -5742,7 +5742,7 @@ static t_stat chip_show(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
return SCPE_OK;
}
static t_stat z80_show(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
static t_stat z80_show(FILE *st, UNIT *uptr, int32 val, const void *desc)
{
if (z80_unit.flags & UNIT_CPU_VERBOSE) {
fprintf(st, "VERBOSE");
@ -5751,7 +5751,7 @@ static t_stat z80_show(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
return SCPE_OK;
}
static t_stat z80_set_chiptype(UNIT *uptr, int32 value, CONST char *cptr, void *desc)
static t_stat z80_set_chiptype(UNIT *uptr, int32 value, const char *cptr, void *desc)
{
if (z80_chiptype != value) {
if (z80_unit.flags & UNIT_CPU_VERBOSE) {
@ -5764,7 +5764,7 @@ static t_stat z80_set_chiptype(UNIT *uptr, int32 value, CONST char *cptr, void *
return SCPE_OK;
}
static t_stat z80_set_hist(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
static t_stat z80_set_hist(UNIT *uptr, int32 val, const char *cptr, void *desc)
{
uint32 i, lnt;
t_stat r;
@ -5828,10 +5828,10 @@ static t_stat z80_set_hist(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
return SCPE_OK;
}
t_stat z80_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
t_stat z80_show_hist (FILE *st, UNIT *uptr, int32 val, const void *desc)
{
int32 k, di, lnt;
CONST char *cptr = (CONST char *) desc;
const char *cptr = (const char *) desc;
t_stat r;
insthist_t *h;
@ -5910,7 +5910,7 @@ t_value z80_pc_value (void) {
return (t_value) PCX;
}
t_stat z80_cmd_reg(int32 flag, CONST char *cptr)
t_stat z80_cmd_reg(int32 flag, const char *cptr)
{
t_value op[INST_MAX_BYTES];
int i;
@ -6531,7 +6531,7 @@ static int32 parse_X80(const char *cptr, const int32 addr, uint32 *val, const ch
return SCPE_ARG;
}
t_stat z80_parse_sym(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
t_stat z80_parse_sym(const char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
{
return (parse_X80(cptr, addr, val, z80_chiptype == CHIP_TYPE_Z80 ? MnemonicsZ80 : Mnemonics8080));
}

4
Altair8800/s100_z80.h
View File

@ -60,10 +60,10 @@ extern REG *z80_pc_reg;
extern t_stat z80_instr(void);
extern t_value z80_pc_value(void);
extern t_stat z80_parse_sym(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw);
extern t_stat z80_parse_sym(const char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw);
extern t_bool z80_is_pc_a_subroutine_call (t_addr **ret_addrs);
extern int32 z80_dasm(char *S, const uint32 *val, const int32 addr);
extern t_stat z80_cmd_reg(int32 flag, CONST char *cptr);
extern t_stat z80_cmd_reg(int32 flag, const char *cptr);
extern t_bool z80_is_pc_a_subroutine_call(t_addr **ret_addrs);
extern t_stat z80_show_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);

4
Altair8800/sds_sbc200.c
View File

@ -639,7 +639,7 @@ typedef struct {
static const char* sbc200_description(DEVICE *dptr);
static t_stat sbc200_svc(UNIT *uptr);
static t_stat sbc200_reset(DEVICE *dptr);
static t_stat sbc200_attach(UNIT *uptr, CONST char *cptr);
static t_stat sbc200_attach(UNIT *uptr, const char *cptr);
static t_stat sbc200_detach(UNIT *uptr);
static t_stat sbc200_set_console(UNIT *uptr, int32 value, const char *cptr, void *desc);
static t_stat sbc200_set_baud(UNIT *uptr, int32 value, const char *cptr, void *desc);
@ -941,7 +941,7 @@ static t_stat sbc200_svc(UNIT *uptr)
/* Attach routine */
static t_stat sbc200_attach(UNIT *uptr, CONST char *cptr)
static t_stat sbc200_attach(UNIT *uptr, const char *cptr)
{
t_stat r;

4
Altair8800/sds_vfii.c
View File

@ -50,7 +50,7 @@ static RES vfii_res = { VFII_IO_BASE, VFII_IO_SIZE, 0x0000, 0x0000 };
static DSK_INFO dsk_info[VFII_NUM_DRIVES];
static t_stat vfii_reset(DEVICE *vfii_dev);
static t_stat vfii_attach(UNIT *uptr, CONST char *cptr);
static t_stat vfii_attach(UNIT *uptr, const char *cptr);
static t_stat vfii_detach(UNIT *uptr);
static t_stat vfii_boot(int32 unitno, DEVICE *dptr);
static int32 vfii_io(const int32 port, const int32 io, const int32 data);
@ -188,7 +188,7 @@ static t_stat vfii_boot(int32 unitno, DEVICE *dptr)
}
/* Attach routine */
static t_stat vfii_attach(UNIT *uptr, CONST char *cptr)
static t_stat vfii_attach(UNIT *uptr, const char *cptr)
{
t_stat r;
int d;

20
Altair8800/tarbell_fdc.c
View File

@ -69,13 +69,13 @@ static uint8 tarbell_prom[TARBELL_PROM_SIZE] = {
};
static t_stat tarbell_reset(DEVICE *tarbell_dev);
static t_stat tarbell_attach(UNIT *uptr, CONST char *cptr);
static t_stat tarbell_attach(UNIT *uptr, const char *cptr);
static t_stat tarbell_detach(UNIT *uptr);
static t_stat tarbell_boot(int32 unitno, DEVICE *dptr);
static t_stat tarbell_set_model(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
static t_stat tarbell_show_model(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat tarbell_set_prom(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
static t_stat tarbell_show_prom(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
static t_stat tarbell_set_model(UNIT *uptr, int32 val, const char *cptr, void *desc);
static t_stat tarbell_show_model(FILE *st, UNIT *uptr, int32 val, const void *desc);
static t_stat tarbell_set_prom(UNIT *uptr, int32 val, const char *cptr, void *desc);
static t_stat tarbell_show_prom(FILE *st, UNIT *uptr, int32 val, const void *desc);
static void tarbell_enable_prom(void);
static void tarbell_disable_prom(void);
static int32 tarbell_io(const int32 port, const int32 io, const int32 data);
@ -216,7 +216,7 @@ static t_stat tarbell_boot(int32 unitno, DEVICE *dptr)
}
/* Attach routine */
static t_stat tarbell_attach(UNIT *uptr, CONST char *cptr)
static t_stat tarbell_attach(UNIT *uptr, const char *cptr)
{
t_stat r;
int d;
@ -377,7 +377,7 @@ static int32 tarbell_memio(const int32 addr, const int32 rw, const int32 data)
return 0xff;
}
static t_stat tarbell_set_model(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
static t_stat tarbell_set_model(UNIT *uptr, int32 val, const char *cptr, void *desc)
{
if (!cptr) return SCPE_IERR;
@ -401,14 +401,14 @@ static t_stat tarbell_set_model(UNIT *uptr, int32 val, CONST char *cptr, void *d
return SCPE_OK;
}
static t_stat tarbell_show_model(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
static t_stat tarbell_show_model(FILE *st, UNIT *uptr, int32 val, const void *desc)
{
fprintf(st, "MODEL=%s", (ddfdc_enabled) ? "2022DD" : "1011SD");
return SCPE_OK;
}
static t_stat tarbell_set_prom(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
static t_stat tarbell_set_prom(UNIT *uptr, int32 val, const char *cptr, void *desc)
{
if (!cptr) return SCPE_IERR;
if (!strlen(cptr)) return SCPE_ARG;
@ -451,7 +451,7 @@ static void tarbell_disable_prom(void)
prom_enabled = FALSE;
}
static t_stat tarbell_show_prom(FILE *st, UNIT *uptr, int32 val, CONST void *desc)
static t_stat tarbell_show_prom(FILE *st, UNIT *uptr, int32 val, const void *desc)
{
fprintf(st, "%s (%sactive)", (prom_enabled) ? "PROM" : "NOPROM", (prom_active) ? "" : "in");

8
Visual Studio Projects/Altair8800.vcproj
View File

@ -207,6 +207,10 @@
RelativePath="..\Altair8800\mits_2sio.c"
>
</File>
<File
RelativePath="..\Altair8800\mits_acr.c"
>
</File>
<File
RelativePath="..\Altair8800\mits_dsk.c"
>
@ -336,6 +340,10 @@
RelativePath="..\Altair8800\mits_2sio.h"
>
</File>
<File
RelativePath="..\Altair8800\mits_acr.h"
>
</File>
<File
RelativePath="..\Altair8800\mits_dsk.h"
>

1
makefile
View File

@ -2243,6 +2243,7 @@ ALTAIR8800 = \
${ALTAIR8800D}/s100_rom.c \
${ALTAIR8800D}/s100_z80.c \
${ALTAIR8800D}/mits_2sio.c \
${ALTAIR8800D}/mits_acr.c \
${ALTAIR8800D}/mits_dsk.c \
${ALTAIR8800D}/sds_sbc200.c \
${ALTAIR8800D}/sds_vfii.c \