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PDP11: Add initial UC15 support from Bob Supnik

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This commit is contained in:
Mark Pizzolato
2016-12-04 15:51:22 -08:00
parent fa1fba5bd5
commit 99bbc5f8cf
8 changed files with 171 additions and 81 deletions
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64
PDP11/pdp11_cpu.c
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@@ -25,6 +25,9 @@
cpu PDP-11 CPU
04-Dec-16 RMS Removed duplicate IDLE entries in MTAB
30-Aug-16 RMS Fixed overloading of -d in ex/mod
14-Mar-16 RMS Added UC15 support
06-Mar-16 RMS Fixed bug in history virtual addressing
30-Dec-15 RMS Added NOBEVENT option for 11/03, 11/23
29-Dec-15 RMS Call build_dib_tab during reset (Mark Pizzolato)
@@ -294,9 +297,9 @@ int32 stop_vecabort = 1; /* stop on vec abort */
int32 stop_spabort = 1; /* stop on SP abort */
int32 wait_enable = 0; /* wait state enable */
int32 autcon_enb = 1; /* autoconfig enable */
uint32 cpu_model = MOD_1173; /* CPU model */
uint32 cpu_type = 1u << MOD_1173; /* model as bit mask */
uint32 cpu_opt = SOP_1173; /* CPU options */
uint32 cpu_model = INIMODEL; /* CPU model */
uint32 cpu_type = 1u << INIMODEL; /* model as bit mask */
uint32 cpu_opt = INIOPTNS; /* CPU options */
uint16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
int32 pcq_p = 0; /* PC queue ptr */
REG *pcq_r = NULL; /* PC queue reg ptr */
@@ -305,7 +308,6 @@ int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
int32 dsmask[4] = { MMR3_KDS, MMR3_SDS, 0, MMR3_UDS }; /* dspace enables */
t_addr cpu_memsize = INIMEMSIZE; /* last mem addr */
extern int32 CPUERR, MAINT;
extern CPUTAB cpu_tab[];
@@ -556,6 +558,7 @@ REG cpu_reg[] = {
MTAB cpu_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "TYPE", NULL,
NULL, &cpu_show_model },
#if !defined (UC15)
{ MTAB_XTD|MTAB_VDV, MOD_1103, NULL, "11/03", &cpu_set_model },
{ MTAB_XTD|MTAB_VDV, MOD_1104, NULL, "11/04", &cpu_set_model },
{ MTAB_XTD|MTAB_VDV, MOD_1105, NULL, "11/05", &cpu_set_model },
@@ -592,8 +595,6 @@ MTAB cpu_mod[] = {
{ MTAB_XTD|MTAB_VDV, OPT_MMU, NULL, "NOMMU", &cpu_clr_opt },
{ MTAB_XTD|MTAB_VDV, OPT_BVT, NULL, "BEVENT", &cpu_set_opt },
{ MTAB_XTD|MTAB_VDV, OPT_BVT, NULL, "NOBEVENT", &cpu_clr_opt },
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size},
{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size},
{ UNIT_MSIZE, 49152, NULL, "48K", &cpu_set_size},
@@ -614,12 +615,22 @@ MTAB cpu_mod[] = {
{ UNIT_MSIZE, 2097152, NULL, "2M", &cpu_set_size},
{ UNIT_MSIZE, 3145728, NULL, "3M", &cpu_set_size},
{ UNIT_MSIZE, 4186112, NULL, "4M", &cpu_set_size},
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
&set_autocon, NULL },
#else
{ MTAB_XTD|MTAB_VDV, MOD_1104, NULL, "11/04", &cpu_set_model },
{ MTAB_XTD|MTAB_VDV, MOD_1105, NULL, "11/05", &cpu_set_model },
{ MTAB_XTD|MTAB_VDV, MOD_1120, NULL, "11/20", &cpu_set_model },
{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size},
{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size},
{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size},
#endif
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
&cpu_set_hist, &cpu_show_hist },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
@@ -654,9 +665,8 @@ t_stat reason;
reason = build_dib_tab (); /* build, chk dib_tab */
if (reason != SCPE_OK)
return reason;
if (MEMSIZE < cpu_tab[cpu_model].maxm) /* mem size < max? */
cpu_memsize = MEMSIZE; /* then okay */
else cpu_memsize = cpu_tab[cpu_model].maxm - IOPAGESIZE;/* max - io page */
if (MEMSIZE >= (cpu_tab[cpu_model].maxm - IOPAGESIZE)) /* mem size >= max - io page? */
MEMSIZE = cpu_tab[cpu_model].maxm - IOPAGESIZE; /* max - io page */
cpu_type = 1u << cpu_model; /* reset type mask */
cpu_bme = (MMR3 & MMR3_BME) && (cpu_opt & OPT_UBM); /* map enabled? */
PC = saved_PC;
@@ -2291,7 +2301,7 @@ if ((va & 1) && CPUT (HAS_ODD)) { /* odd address? */
}
pa = relocR (va); /* relocate */
if (ADDR_IS_MEM (pa)) /* memory address? */
return (M[pa >> 1]);
return RdMemW (pa);
if ((pa < IOPAGEBASE) || /* not I/O address */
(CPUT (CPUT_J) && (pa >= IOBA_CPU))) { /* or J11 int reg? */
setCPUERR (CPUE_NXM);
@@ -2314,7 +2324,7 @@ if ((va & 1) && CPUT (HAS_ODD)) { /* odd address? */
}
pa = relocR (va); /* relocate */
if (ADDR_IS_MEM (pa)) /* memory address? */
return (M[pa >> 1]);
return RdMemW (pa);
if (pa < IOPAGEBASE) { /* not I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM);
@@ -2331,8 +2341,8 @@ int32 ReadB (int32 va)
int32 pa, data;
pa = relocR (va); /* relocate */
if (ADDR_IS_MEM (pa))
return (va & 1? M[pa >> 1] >> 8: M[pa >> 1]) & 0377;
if (ADDR_IS_MEM (pa)) /* memory address? */
return RdMemB (pa);
if (pa < IOPAGEBASE) { /* not I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM);
@@ -2354,7 +2364,7 @@ if ((va & 1) && CPUT (HAS_ODD)) { /* odd address? */
}
last_pa = relocW (va); /* reloc, wrt chk */
if (ADDR_IS_MEM (last_pa)) /* memory address? */
return (M[last_pa >> 1]);
return RdMemW (last_pa);
if (last_pa < IOPAGEBASE) { /* not I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM);
@@ -2372,7 +2382,7 @@ int32 data;
last_pa = relocW (va); /* reloc, wrt chk */
if (ADDR_IS_MEM (last_pa))
return (va & 1? M[last_pa >> 1] >> 8: M[last_pa >> 1]) & 0377;
return RdMemB (last_pa);
if (last_pa < IOPAGEBASE) { /* not I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM);
@@ -2403,7 +2413,7 @@ if ((va & 1) && CPUT (HAS_ODD)) { /* odd address? */
}
pa = relocW (va); /* relocate */
if (ADDR_IS_MEM (pa)) { /* memory address? */
M[pa >> 1] = data;
WrMemW (pa, data);
return;
}
if (pa < IOPAGEBASE) { /* not I/O address? */
@@ -2423,9 +2433,7 @@ int32 pa;
pa = relocW (va); /* relocate */
if (ADDR_IS_MEM (pa)) { /* memory address? */
if (va & 1)
M[pa >> 1] = (M[pa >> 1] & 0377) | (data << 8);
else M[pa >> 1] = (M[pa >> 1] & ~0377) | data;
WrMemB (pa, data);
return;
}
if (pa < IOPAGEBASE) { /* not I/O address? */
@@ -2442,7 +2450,7 @@ return;
void PWriteW (int32 data, int32 pa)
{
if (ADDR_IS_MEM (pa)) { /* memory address? */
M[pa >> 1] = data;
WrMemW (pa, data);
return;
}
if (pa < IOPAGEBASE) { /* not I/O address? */
@@ -2459,9 +2467,7 @@ return;
void PWriteB (int32 data, int32 pa)
{
if (ADDR_IS_MEM (pa)) { /* memory address? */
if (pa & 1)
M[pa >> 1] = (M[pa >> 1] & 0377) | (data << 8);
else M[pa >> 1] = (M[pa >> 1] & ~0377) | data;
WrMemB (pa, data);
return;
}
if (pa < IOPAGEBASE) { /* not I/O address? */
@@ -3045,8 +3051,8 @@ if (sw & SWMASK ('V')) { /* -v */
if (addr >= MAXMEMSIZE)
return SCPE_REL;
}
if (addr < MEMSIZE) {
*vptr = M[addr >> 1] & 0177777;
if (ADDR_IS_MEM (addr)) {
*vptr = RdMemW (addr) & 0177777;
return SCPE_OK;
}
if (addr < IOPAGEBASE)
@@ -3067,8 +3073,8 @@ if (sw & SWMASK ('V')) { /* -v */
if (addr >= MAXMEMSIZE)
return SCPE_REL;
}
if (addr < MEMSIZE) {
M[addr >> 1] = val & 0177777;
if (ADDR_IS_MEM (addr)) {
WrMemW (addr, val & 0177777);
return SCPE_OK;
}
if (addr < IOPAGEBASE)