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PDP11, all VAX: Add TU58 device simulator with support for 32 drives plus the VAX 730 and 750 console devices
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@@ -106,6 +106,7 @@
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) (((t_addr) (x)) < cpu_memsize) /* use only in sim! */
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#define DMASK 0177777
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#define BMASK 0377
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/* CPU models */
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@@ -633,6 +634,8 @@ typedef struct pdp_dib DIB;
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#define INT_V_VTCH 15
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#define INT_V_VTNM 16
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#define INT_V_LK 17
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#define INT_V_TDRX 18
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#define INT_V_TDTX 19
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#define INT_V_PIR3 0 /* BR3 */
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#define INT_V_PIR2 0 /* BR2 */
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@@ -690,6 +693,8 @@ typedef struct pdp_dib DIB;
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#define INT_PIR3 (1u << INT_V_PIR3)
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#define INT_PIR2 (1u << INT_V_PIR2)
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#define INT_PIR1 (1u << INT_V_PIR1)
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#define INT_TDRX (1u << INT_V_TDRX)
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#define INT_TDTX (1u << INT_V_TDTX)
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#define INT_INTERNAL7 (INT_PIR7)
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#define INT_INTERNAL6 (INT_PIR6 | INT_CLK)
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@@ -744,6 +749,8 @@ typedef struct pdp_dib DIB;
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#define IPL_VTCH 4
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#define IPL_VTNM 4
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#define IPL_LK 4 /* XXX just a guess */
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#define IPL_TDRX 4
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#define IPL_TDTX 4
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#define IPL_PIR7 7
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#define IPL_PIR6 6
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@@ -591,7 +591,7 @@ AUTO_CON auto_tab[] = {/*c #v am vm fxa fxv */
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014240, 014250, 014260, 014270,
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014300, 014310, 014320, 014330,
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014340, 014350, 014360, 014370} }, /* DC11 - fx CSRs */
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{ { NULL }, 1, 2, 0, 8,
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{ { "TDC" }, 1, 2, 0, 8,
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{016500, 016510, 016520, 016530,
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016540, 016550, 016560, 016570,
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016600, 016610, 016620, 016630,
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@@ -82,6 +82,7 @@ extern DEVICE dli_dev;
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extern DEVICE dlo_dev;
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extern DEVICE dci_dev;
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extern DEVICE dco_dev;
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extern DEVICE tdc_dev;
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extern DEVICE dz_dev;
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extern DEVICE vh_dev;
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extern DEVICE dt_dev;
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@@ -145,6 +146,7 @@ DEVICE *sim_devices[] = {
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&ptp_dev,
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&tti_dev,
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&tto_dev,
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&tdc_dev,
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&cr_dev,
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&lpt_dev,
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&dli_dev,
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1455
PDP11/pdp11_td.c
Normal file
1455
PDP11/pdp11_td.c
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File diff suppressed because it is too large
Load Diff
85
PDP11/pdp11_td.h
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85
PDP11/pdp11_td.h
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@@ -0,0 +1,85 @@
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/* pdp11_td.h: TU58 cartridge controller API
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------------------------------------------------------------------------------
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Copyright (c) 2015, Mark Pizzolato
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of the author shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author.
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------------------------------------------------------------------------------
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Modification history:
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20-Sep-15 MP Initial Version
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------------------------------------------------------------------------------
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*/
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#ifndef PDP11_TD_H
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#define PDP11_TD_H
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#include "sim_defs.h"
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typedef struct CTLR CTLR;
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t_stat td_connect_console_device (DEVICE *dptr,
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void (*rx_set_int) (int32 ctlr_num, t_bool val),
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void (*tx_set_int) (int32 ctlr_num, t_bool val));
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t_stat td_rd_i_csr (CTLR *ctlr, int32 *data);
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t_stat td_rd_i_buf (CTLR *ctlr, int32 *data);
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t_stat td_rd_o_csr (CTLR *ctlr, int32 *data);
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t_stat td_rd_o_buf (CTLR *ctlr, int32 *data);
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t_stat td_wr_i_csr (CTLR *ctlr, int32 data);
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t_stat td_wr_i_buf (CTLR *ctlr, int32 data);
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t_stat td_wr_o_csr (CTLR *ctlr, int32 data);
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t_stat td_wr_o_buf (CTLR *ctlr, int32 data);
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/* Debug detail levels */
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#define TDDEB_OPS 00001 /* transactions */
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#define TDDEB_IRD 00002 /* input reg reads */
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#define TDDEB_ORD 00004 /* output reg reads */
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#define TDDEB_RRD 00006 /* reg reads */
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#define TDDEB_IWR 00010 /* input reg writes */
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#define TDDEB_OWR 00020 /* output reg writes */
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#define TDDEB_RWR 00030 /* reg writes */
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#define TDDEB_TRC 00040 /* trace */
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#define TDDEB_INT 00100 /* interrupts */
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#define TDDEB_PKT 00200 /* packet */
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static DEBTAB td_deb[] = {
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{ "OPS", TDDEB_OPS, "transactions" },
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{ "PKT", TDDEB_PKT, "packet" },
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{ "RRD", TDDEB_RRD, "reg reads"},
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{ "IRD", TDDEB_IRD, "input reg reads" },
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{ "ORD", TDDEB_ORD, "output reg reads" },
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{ "RWR", TDDEB_RWR, "reg writes" },
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{ "IWR", TDDEB_IWR, "input reg writes" },
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{ "OWR", TDDEB_OWR, "output reg writes" },
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{ "INT", TDDEB_INT, "interrupts" },
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{ "TRC", TDDEB_TRC, "trace" },
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{ NULL, 0 }
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};
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#endif /* _PDP11_TD_H */
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@@ -2301,6 +2301,11 @@ void xq_start_receiver(CTLR* xq)
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if (!xq->var->etherface)
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return;
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/* clear read queue */
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ethq_clear(&xq->var->ReadQ);
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/* start the read service timer or enable asynch reading as appropriate */
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if (xq->var->must_poll) {
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if (sim_idle_enab)
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