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Finish migration for simulators to use generic clock co-scheduling and sim_activate_after for scheduled delays

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This commit is contained in:
Mark Pizzolato
2013-01-22 05:41:27 -08:00
parent 83c1d80194
commit 9fc6aa73d6
21 changed files with 35 additions and 46 deletions
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2
PDP11/pdp11_cpu.c
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@@ -253,8 +253,6 @@ typedef struct {
/* Global state */
extern FILE *sim_log;
uint16 *M = NULL; /* memory */
int32 REGFILE[6][2] = { {0} }; /* R0-R5, two sets */
int32 STACKFILE[4] = { 0 }; /* SP, four modes */

5
PDP11/pdp11_rq.c
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@@ -699,7 +699,6 @@ static struct ctlrtyp ctlr_tab[] = {
};
extern int32 int_req[IPL_HLVL];
extern int32 tmr_poll, clk_tps;
int32 rq_itime = 200; /* init time, except */
int32 rq_itime4 = 10; /* stage 4 */
@@ -1429,7 +1428,7 @@ if (cp->csta < CST_UP) { /* still init? */
sim_debug (DBG_REQ, dptr, "initialization complete\n");
cp->csta = CST_UP; /* we're up */
cp->sa = 0; /* clear SA */
sim_activate (dptr->units + RQ_TIMER, tmr_poll * clk_tps);
sim_activate_after (dptr->units + RQ_TIMER, 1000000);
if ((cp->saw & SA_S4H_LF)
&& cp->perr) rq_plf (cp, cp->perr);
cp->perr = 0;
@@ -1495,7 +1494,7 @@ MSC *cp = rq_ctxmap[uptr->cnum];
DEVICE *dptr = rq_devmap[uptr->cnum];
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_tmrsvc\n");
sim_activate (uptr, tmr_poll * clk_tps); /* reactivate */
sim_activate_after (uptr, 1000000); /* reactivate */
for (i = 0; i < RQ_NUMDR; i++) { /* poll */
nuptr = dptr->units + i;
if ((nuptr->flags & UNIT_ATP) && /* ATN pending? */

2
PDP11/pdp11_stddev.c
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@@ -444,7 +444,7 @@ clk_csr = clk_csr | CSR_DONE; /* set done */
if ((clk_csr & CSR_IE) || clk_fie)
SET_INT (CLK);
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate (&clk_unit, t); /* reactivate unit */
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmr_poll = t; /* set timer poll */
tmxr_poll = t; /* set mux poll */
return SCPE_OK;

8
PDP11/pdp11_tq.c
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@@ -245,7 +245,6 @@ static struct drvtyp drv_tab[] = {
/* Data */
extern int32 int_req[IPL_HLVL];
extern int32 tmr_poll, clk_tps;
uint32 tq_sa = 0; /* status, addr */
uint32 tq_saw = 0; /* written data */
@@ -713,7 +712,7 @@ if (tq_csta < CST_UP) { /* still init? */
sim_debug (DBG_REQ, &tq_dev, "initialization complete\n");
tq_csta = CST_UP; /* we're up */
tq_sa = 0; /* clear SA */
sim_activate (&tq_unit[TQ_TIMER], tmr_poll * clk_tps);
sim_activate_after (&tq_unit[TQ_TIMER], 1000000);
if ((tq_saw & SA_S4H_LF) && tq_perr)
tq_plf (tq_perr);
tq_perr = 0;
@@ -786,7 +785,7 @@ UNIT *nuptr;
sim_debug(DBG_TRC, &tq_dev, "tq_tmrsvc\n");
sim_activate (uptr, tmr_poll * clk_tps); /* reactivate */
sim_activate_after (uptr, 1000000); /* reactivate */
for (i = 0; i < TQ_NUMDR; i++) { /* poll */
nuptr = tq_dev.units + i;
if ((nuptr->flags & UNIT_ATP) && /* ATN pending? */
@@ -1193,10 +1192,9 @@ if ((uptr = tq_getucb (lu))) { /* unit exist? */
sts = tq_mot_valid (uptr, OP_POS); /* validity checks */
if (sts == ST_SUC) { /* ok? */
uptr->cpkt = pkt; /* op in progress */
tq_rwtime = 2 * tmr_poll * clk_tps; /* 2 second rewind time */
if ((tq_pkt[pkt].d[CMD_MOD] & MD_RWD) && /* rewind? */
(!(tq_pkt[pkt].d[CMD_MOD] & MD_IMM))) /* !immediate? */
sim_activate (uptr, tq_rwtime); /* use 2 sec rewind execute time */
sim_activate_after (uptr, 2000000); /* use 2 sec rewind execute time */
else { /* otherwise */
uptr->iostarttime = sim_grtime();
sim_activate (uptr, 0); /* use normal execute time */

4
PDP11/pdp11_xq.c
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@@ -2483,7 +2483,7 @@ t_stat xq_reset(DEVICE* dptr)
xq_csr_set_clr(xq, XQ_CSR_OK, 0);
/* start service timer */
sim_activate_abs(&xq->unit[1], (tmr_poll * clk_tps) / 4);
sim_activate_after(&xq->unit[1], 250000);
/* stop the receiver */
eth_clr_async(xq->var->etherface);
@@ -2672,7 +2672,7 @@ t_stat xq_tmrsvc(UNIT* uptr)
}
/* resubmit service timer */
sim_activate(uptr, (tmr_poll * clk_tps) / 4);
sim_activate_after(uptr, 250000);
return SCPE_OK;
}

8
PDP11/pdp11_xu.c
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@@ -99,8 +99,7 @@
#include "pdp11_xu.h"
extern int32 tmxr_poll, tmr_poll, clk_tps, cpu_astop;
extern FILE *sim_log;
extern int32 tmxr_poll;
t_stat xu_rd(int32* data, int32 PA, int32 access);
t_stat xu_wr(int32 data, int32 PA, int32 access);
@@ -583,7 +582,6 @@ t_stat xu_tmrsvc(UNIT* uptr)
{
CTLR* xu = xu_unit2ctlr(uptr);
const ETH_MAC mop_multicast = {0xAB, 0x00, 0x00, 0x02, 0x00, 0x00};
const int one_second = clk_tps * tmr_poll;
/* send identity packet when timer expires */
if (--xu->var->idtmr <= 0) {
@@ -596,7 +594,7 @@ t_stat xu_tmrsvc(UNIT* uptr)
upd_stat16 (&xu->var->stats.secs, 1);
/* resubmit service timer */
sim_activate(uptr, one_second);
sim_activate_after(uptr, 1000000);
return SCPE_OK;
}
@@ -677,7 +675,7 @@ t_stat xu_sw_reset (CTLR* xu)
sim_clock_coschedule (&xu->unit[0], tmxr_poll);
/* start service timer */
sim_activate_abs(&xu->unit[1], tmr_poll * clk_tps);
sim_activate_after (&xu->unit[1], 1000000);
}
/* clear load_server address */