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Intel-Systems, IBMPC: Standardize to CRLF line endings and spaces for tabs
This commit is contained in:
Bill Beech
committed by
Mark Pizzolato
Mark Pizzolato
parent
18efafe927
commit
a221ac4055
@@ -1,193 +1,193 @@
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/* i8255.c: Intel i8255 PIO adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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These functions support a simulated i8255 interface device on an iSBC.
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The device has threee physical 8-bit I/O ports which could be connected
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to any parallel I/O device.
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All I/O is via programmed I/O. The i8255 has a control port (PIOS)
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and three data ports (PIOA, PIOB, and PIOC).
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The simulated device supports a select from I/O space and two address lines.
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The data ports are at the lower addresses and the control port is at
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the highest.
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A write to the control port can configure the device:
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Control Word
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+---+---+---+---+---+---+---+---+
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| D7 D6 D5 D4 D3 D2 D1 D0|
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+---+---+---+---+---+---+---+---+
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Group B
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D0 Port C (lower) 1-Input, 0-Output
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D1 Port B 1-Input, 0-Output
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D2 Mode Selection 0-Mode 0, 1-Mode 1
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Group A
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D3 Port C (upper) 1-Input, 0-Output
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D4 Port A 1-Input, 0-Output
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D5-6 Mode Selection 00-Mode 0, 01-Mode 1, 1X-Mode 2
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D7 Mode Set Flag 1=Active, 0=Bit Set
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Mode 0 - Basic Input/Output
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Mode 1 - Strobed Input/Output
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Mode 2 - Bidirectional Bus
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Bit Set - D7=0, D3:1 select port C bit, D0 1=set, 0=reset
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A read to the data ports gets the current port value, a write
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to the data ports writes the character to the device.
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?? ??? 10 - Original file.
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16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size.
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*/
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#include "system_defs.h"
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extern int32 reg_dev(int32 (*routine)(int32, int32), int32 port);
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/* function prototypes */
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t_stat pata_reset (DEVICE *dptr, int32 base);
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/* i8255 Standard I/O Data Structures */
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UNIT pata_unit[] = {
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{ UDATA (0, 0, 0) }
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};
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REG pata_reg[] = {
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{ HRDATA (CONTROL0, pata_unit[0].u3, 8) },
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{ HRDATA (PORTA0, pata_unit[0].u4, 8) },
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{ HRDATA (PORTB0, pata_unit[0].u5, 8) },
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{ HRDATA (PORTC0, pata_unit[0].u6, 8) },
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{ NULL }
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};
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DEVICE pata_dev = {
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"PATA", //name
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pata_unit, //units
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pata_reg, //registers
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NULL, //modifiers
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1, //numunits
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16, //aradix
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32, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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// &pata_reset, //reset
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NULL, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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0, //flags
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0, //dctrl
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NULL, //debflags
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NULL, //msize
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NULL //lname
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};
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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int32 patas(int32 io, int32 data)
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{
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int32 bit;
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if (io == 0) { /* read status port */
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return pata_unit[0].u3;
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} else { /* write status port */
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if (data & 0x80) { /* mode instruction */
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pata_unit[0].u3 = data;
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sim_printf("PATA: 8255 Mode Instruction=%02X\n", data);
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if (data & 0x64)
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sim_printf(" Mode 1 and 2 not yet implemented\n");
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} else { /* bit set */
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bit = (data & 0x0E) >> 1; /* get bit number */
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if (data & 0x01) { /* set bit */
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pata_unit[0].u6 |= (0x01 << bit);
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} else { /* reset bit */
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pata_unit[0].u6 &= ~(0x01 << bit);
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}
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}
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}
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return 0;
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}
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int32 pataa(int32 io, int32 data)
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{
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if (io == 0) { /* read data port */
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return (pata_unit[0].u4);
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} else { /* write data port */
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pata_unit[0].u4 = data;
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sim_printf("PATA: 8255 Port A = %02X\n", data);
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}
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return 0;
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}
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int32 patab(int32 io, int32 data)
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{
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if (io == 0) { /* read data port */
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return (pata_unit[0].u5);
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} else { /* write data port */
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pata_unit[0].u5 = data;
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sim_printf("PATA: 8255 Port B = %02X\n", data);
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}
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return 0;
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}
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int32 patac(int32 io, int32 data)
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{
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if (io == 0) { /* read data port */
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return (pata_unit[0].u6);
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} else { /* write data port */
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pata_unit[0].u6 = data;
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sim_printf("PATA: 8255 Port C = %02X\n", data);
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}
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return 0;
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}
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/* Reset routine */
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t_stat pata_reset (DEVICE *dptr, int32 base)
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{
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pata_unit[0].u3 = 0x9B; /* control */
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pata_unit[0].u4 = 0xFF; /* Port A */
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pata_unit[0].u5 = 0xFF; /* Port B */
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pata_unit[0].u6 = 0xFF; /* Port C */
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reg_dev(pataa, base);
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reg_dev(patab, base + 1);
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reg_dev(patac, base + 2);
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reg_dev(patas, base + 3);
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sim_printf(" PATA: Reset\n");
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return SCPE_OK;
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}
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/* i8255.c: Intel i8255 PIO adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
|
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to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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and/or sell copies of the Software, and to permit persons to whom the
|
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Software is furnished to do so, subject to the following conditions:
|
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The above copyright notice and this permission notice shall be included in
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||||
all copies or substantial portions of the Software.
|
||||
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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These functions support a simulated i8255 interface device on an iSBC.
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The device has threee physical 8-bit I/O ports which could be connected
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to any parallel I/O device.
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All I/O is via programmed I/O. The i8255 has a control port (PIOS)
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and three data ports (PIOA, PIOB, and PIOC).
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The simulated device supports a select from I/O space and two address lines.
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The data ports are at the lower addresses and the control port is at
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the highest.
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A write to the control port can configure the device:
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Control Word
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+---+---+---+---+---+---+---+---+
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| D7 D6 D5 D4 D3 D2 D1 D0|
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+---+---+---+---+---+---+---+---+
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Group B
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D0 Port C (lower) 1-Input, 0-Output
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D1 Port B 1-Input, 0-Output
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D2 Mode Selection 0-Mode 0, 1-Mode 1
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Group A
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D3 Port C (upper) 1-Input, 0-Output
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D4 Port A 1-Input, 0-Output
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D5-6 Mode Selection 00-Mode 0, 01-Mode 1, 1X-Mode 2
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D7 Mode Set Flag 1=Active, 0=Bit Set
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Mode 0 - Basic Input/Output
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Mode 1 - Strobed Input/Output
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Mode 2 - Bidirectional Bus
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Bit Set - D7=0, D3:1 select port C bit, D0 1=set, 0=reset
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A read to the data ports gets the current port value, a write
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to the data ports writes the character to the device.
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?? ??? 10 - Original file.
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16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size.
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*/
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#include "system_defs.h"
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extern int32 reg_dev(int32 (*routine)(int32, int32), int32 port);
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/* function prototypes */
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t_stat pata_reset (DEVICE *dptr, int32 base);
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/* i8255 Standard I/O Data Structures */
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UNIT pata_unit[] = {
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{ UDATA (0, 0, 0) }
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};
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REG pata_reg[] = {
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{ HRDATA (CONTROL0, pata_unit[0].u3, 8) },
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{ HRDATA (PORTA0, pata_unit[0].u4, 8) },
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{ HRDATA (PORTB0, pata_unit[0].u5, 8) },
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{ HRDATA (PORTC0, pata_unit[0].u6, 8) },
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{ NULL }
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};
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DEVICE pata_dev = {
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"PATA", //name
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pata_unit, //units
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pata_reg, //registers
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NULL, //modifiers
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1, //numunits
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16, //aradix
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32, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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// &pata_reset, //reset
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NULL, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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0, //flags
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0, //dctrl
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NULL, //debflags
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NULL, //msize
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NULL //lname
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};
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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int32 patas(int32 io, int32 data)
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{
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int32 bit;
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if (io == 0) { /* read status port */
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return pata_unit[0].u3;
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} else { /* write status port */
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if (data & 0x80) { /* mode instruction */
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pata_unit[0].u3 = data;
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sim_printf("PATA: 8255 Mode Instruction=%02X\n", data);
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if (data & 0x64)
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sim_printf(" Mode 1 and 2 not yet implemented\n");
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} else { /* bit set */
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bit = (data & 0x0E) >> 1; /* get bit number */
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if (data & 0x01) { /* set bit */
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pata_unit[0].u6 |= (0x01 << bit);
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} else { /* reset bit */
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pata_unit[0].u6 &= ~(0x01 << bit);
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}
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}
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}
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return 0;
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}
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int32 pataa(int32 io, int32 data)
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{
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if (io == 0) { /* read data port */
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return (pata_unit[0].u4);
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} else { /* write data port */
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pata_unit[0].u4 = data;
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sim_printf("PATA: 8255 Port A = %02X\n", data);
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}
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return 0;
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}
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int32 patab(int32 io, int32 data)
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{
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if (io == 0) { /* read data port */
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return (pata_unit[0].u5);
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} else { /* write data port */
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pata_unit[0].u5 = data;
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sim_printf("PATA: 8255 Port B = %02X\n", data);
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}
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return 0;
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}
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int32 patac(int32 io, int32 data)
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{
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if (io == 0) { /* read data port */
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return (pata_unit[0].u6);
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} else { /* write data port */
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pata_unit[0].u6 = data;
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sim_printf("PATA: 8255 Port C = %02X\n", data);
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}
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return 0;
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}
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/* Reset routine */
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t_stat pata_reset (DEVICE *dptr, int32 base)
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{
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pata_unit[0].u3 = 0x9B; /* control */
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pata_unit[0].u4 = 0xFF; /* Port A */
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pata_unit[0].u5 = 0xFF; /* Port B */
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pata_unit[0].u6 = 0xFF; /* Port C */
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reg_dev(pataa, base);
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reg_dev(patab, base + 1);
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reg_dev(patac, base + 2);
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reg_dev(patas, base + 3);
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sim_printf(" PATA: Reset\n");
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return SCPE_OK;
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}
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