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CDC1700: Update to add help and descriptions from John Forecast
- add internal help entries - add descriptions to the register, modifier and debug tables. - changed device CD name to CDD to avoid name conflict with the CD command
This commit is contained in:
Mark Pizzolato
@@ -83,7 +83,7 @@ uint8 P[MAXMEMSIZE];
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t_uint64 Instructions;
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uint16 Preg, Areg, Qreg, Mreg, CAenable, OrigPreg, Pending, IOAreg, IOQreg;
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uint8 Pfault, Protected, lastP, Oflag, PARflag, INTflag, DEFERflag;
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uint8 Pfault, Protected, lastP, Oflag, INTflag, DEFERflag;
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t_bool ExecutionStarted = FALSE;
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uint16 CharAddrMode[16];
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@@ -110,6 +110,8 @@ t_stat cpu_set_size(UNIT *, int32, CONST char *, void *);
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t_stat cpu_ex(t_value *, t_addr, UNIT *, int32);
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t_stat cpu_dep(t_value, t_addr, UNIT *uptr, int32 sw);
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t_stat cpu_help(FILE *, DEVICE *, UNIT *, int32, const char *);
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#define UNIT_V_STOPSW (UNIT_V_UF + 1) /* Selective STOP switch */
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#define UNIT_STOPSW (1 << UNIT_V_STOPSW)
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#define UNIT_V_SKIPSW (UNIT_V_UF + 2) /* Selective SKIP switch */
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@@ -123,7 +125,7 @@ t_stat cpu_dep(t_value, t_addr, UNIT *uptr, int32 sw);
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#define UNIT_V_MSIZE (UNIT_V_UF + 6) /* Memory size */
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#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
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IO_DEVICE CPUdev = IODEV(NULL, "1704", CPU, 0, 0xFF, 0,
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IO_DEVICE CPUdev = IODEV(NULL, "1714", CPU, 0, 0xFF, 0,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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0, 0, 0, 0, 0, 0, 0, 0, NULL);
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@@ -137,39 +139,53 @@ IO_DEVICE CPUdev = IODEV(NULL, "1704", CPU, 0, 0xFF, 0,
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UNIT cpu_unit = { UDATA(NULL, UNIT_FIX+UNIT_BINK, DEFAULTMEMSIZE) };
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REG cpu_reg[] = {
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{ HRDATA(P, Preg, 16) },
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{ HRDATA(A, Areg, 16) },
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{ HRDATA(Q, Qreg, 16) },
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{ HRDATA(M, Mreg, 16) },
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{ HRDATA(O, Oflag, 1) },
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{ HRDATA(CH, CAenable, 1) },
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{ HRDATA(PAR, PARflag, 1) },
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{ HRDATA(INT, INTflag, 1) },
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{ HRDATA(DEFER, DEFERflag, 1) },
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{ HRDATA(PENDING, Pending, 1) },
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{ HRDATA(PFAULT, Pfault, 1) },
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{ HRDATAD(P, Preg, 16, "Program address counter") },
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{ HRDATAD(A, Areg, 16, "Principal arithmetic register") },
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{ HRDATAD(Q, Qreg, 16, "Index register") },
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{ HRDATAD(M, Mreg, 16, "Interrupt mask register") },
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{ HRDATAD(O, Oflag, 1, "Overflow flag") },
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{ HRDATAD(CH, CAenable, 1, "Character addressing enable flag") },
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{ HRDATAD(INT, INTflag, 1, "Interrupt enable flag") },
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{ HRDATAD(DEFER, DEFERflag, 1, "Interrupt deferred flag") },
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{ HRDATAD(PENDING, Pending, 16, "Pending interrupt flags") },
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{ HRDATAD(PFAULT, Pfault, 1, "Protect fault pending flag") },
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{ NULL }
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};
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MTAB cpu_mod[] = {
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{ UNIT_STOPSW, UNIT_STOPSW, "Selective Stop", "SSTOP", NULL },
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{ UNIT_STOPSW, 0, "No Selective Stop", "NOSSTOP", NULL },
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{ UNIT_SKIPSW, UNIT_SKIPSW, "Selective Skip", "SSKIP", NULL },
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{ UNIT_SKIPSW, 0, "No Selective Skip", "NOSSKIP", NULL },
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{ UNIT_MODE65K, UNIT_MODE65K, "65K Addressing Mode", "MODE65K", NULL },
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{ UNIT_MODE65K, 0, "32K Addressing Mode", "MODE32K", NULL },
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{ UNIT_CHAR, UNIT_CHAR, "Character Addressing", "CHAR", NULL },
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{ UNIT_CHAR, 0, "No Character Addressing", "NOCHAR", NULL },
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{ UNIT_PROT, UNIT_PROT, "Program Protect", "PROTECT", NULL },
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{ UNIT_PROT, 0, "", "NOPROTECT", NULL },
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{ UNIT_MSIZE, 4096, NULL, "4K", &cpu_set_size },
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{ UNIT_MSIZE, 8192, NULL, "8K", &cpu_set_size },
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{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size },
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{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size },
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{ MTAB_XTD|MTAB_VDV, 0, "1714 CDC 1700 series CPU", NULL, NULL, NULL },
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{ UNIT_STOPSW, UNIT_STOPSW, "Selective Stop", "SSTOP",
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NULL, NULL, NULL, "Enable Selective Stop" },
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{ UNIT_STOPSW, 0, "No Selective Stop", "NOSSTOP",
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NULL, NULL, NULL, "Disable Selective Stop" },
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{ UNIT_SKIPSW, UNIT_SKIPSW, "Selective Skip", "SSKIP",
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NULL, NULL, NULL, "Enable Selective Skip" },
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{ UNIT_SKIPSW, 0, "No Selective Skip", "NOSSKIP",
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NULL, NULL, NULL, "Disable Selective Skip" },
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{ UNIT_MODE65K, UNIT_MODE65K, "65K Addressing Mode", "MODE65K",
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NULL, NULL, NULL, "Enable 65K Indirect Addressing Mode" },
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{ UNIT_MODE65K, 0, "32K Addressing Mode", "MODE32K",
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NULL, NULL, NULL, "Enable 32K Indirect Addressing Mode" },
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{ UNIT_CHAR, UNIT_CHAR, "Character Addressing", "CHAR",
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NULL, NULL, NULL, "Enable Character Addressing Mode" },
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{ UNIT_CHAR, 0, "No Character Addressing", "NOCHAR",
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NULL, NULL, NULL, "Disable Character Addressing Mode" },
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{ UNIT_PROT, UNIT_PROT, "Program Protect", "PROTECT",
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NULL, NULL, NULL, "Enable Protect Mode Operation" },
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{ UNIT_PROT, 0, "", "NOPROTECT",
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NULL, NULL, NULL, "Disable Protect Mode Operation" },
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{ UNIT_MSIZE, 4096, NULL, "4K",
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&cpu_set_size, NULL, NULL, "Set Memory Size to 4KW" },
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{ UNIT_MSIZE, 8192, NULL, "8K",
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&cpu_set_size, NULL, NULL, "Set Memory Size to 8KW" },
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{ UNIT_MSIZE, 16384, NULL, "16K",
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&cpu_set_size, NULL, NULL, "Set Memory Size to 16KW" },
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{ UNIT_MSIZE, 32768, NULL, "32K",
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&cpu_set_size, NULL, NULL, "Set Memory Size to 32KW" },
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#if MAXMEMSIZE > 32768
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{ UNIT_MSIZE, 65536, NULL, "64K", &cpu_set_size },
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{ UNIT_MSIZE, 65536, NULL, "64K",
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&cpu_set_size, NULL, NULL, "Set Memory Size to 64KW" },
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#endif
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{ MTAB_XTD | MTAB_VDV, 0, "1714", NULL, NULL, NULL },
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{ 0 }
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};
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@@ -177,18 +193,18 @@ MTAB cpu_mod[] = {
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(DBG_DISASS | DBG_TRACE | DBG_TARGET | DBG_INPUT | DBG_OUTPUT | DBG_FULL)
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DEBTAB cpu_deb[] = {
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{ "DISASSEMBLE", DBG_DISASS },
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{ "IDISASSEMBLE", DBG_IDISASS },
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{ "INTERRUPT", DBG_INTR },
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{ "TRACE", DBG_TRACE },
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{ "ITRACE", DBG_ITRACE },
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{ "TARGET", DBG_TARGET },
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{ "INPUT", DBG_INPUT },
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{ "OUTPUT", DBG_OUTPUT },
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{ "IO", DBG_INPUT | DBG_OUTPUT },
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{ "INTLVL", DBG_INTLVL },
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{ "PROTECT", DBG_PROTECT },
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{ "MISSING", DBG_MISSING },
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{ "DISASSEMBLE", DBG_DISASS, "Disassemble instructions while tracing" },
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{ "IDISASSEMBLE", DBG_IDISASS, "Disassemble while interrupts active" },
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{ "INTERRUPT", DBG_INTR, "Display interrupt entry/exit" },
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{ "TRACE", DBG_TRACE, "Trace instruction execution" },
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{ "ITRACE", DBG_ITRACE, "Trace while interrupts active" },
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{ "TARGET", DBG_TARGET, "Display target address of instructions" },
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{ "INPUT", DBG_INPUT, "Display INP instruction execution" },
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{ "OUTPUT", DBG_OUTPUT, "Display OUT instruction execution" },
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{ "IO", DBG_INPUT | DBG_OUTPUT, "Display INP and OUT execution" },
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{ "INTLVL", DBG_INTLVL, "Add interrupt level to all displays" },
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{ "PROTECT", DBG_PROTECT, "Display protect faults" },
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{ "MISSING", DBG_MISSING, "Display info about missing devices" },
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{ "FULL", DBG_ALL },
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{ NULL }
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};
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@@ -200,8 +216,7 @@ DEVICE cpu_dev = {
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NULL, NULL, NULL,
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&CPUdev,
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DEV_DEBUG | DEV_NOEQUIP, 0, cpu_deb,
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NULL,
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NULL
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NULL, NULL, &cpu_help, NULL, NULL, NULL
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};
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/*
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@@ -1546,3 +1561,76 @@ t_stat sim_instr(void)
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}
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return reason;
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}
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t_stat cpu_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
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{
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const char helpString[] =
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/****************************************************************************/
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" The %D device is a 1714 central processing unit.\n"
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"1 Hardware Description\n"
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" The 1714 can access up to 64KW of memory (4KW, 8KW, 16KW, 32KW and 64KW\n"
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" are supported). A 1705 multi-level interrupt system with a direct\n"
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" storage access bus and 3 1706-A buffered data channels are included.\n\n"
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" The amount of memory available to the system can be changed with:\n\n"
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"+sim> SET CPU nK\n\n"
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" The original 1700 series CPU (the 1704) only allowed up to 32KW to be\n"
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" attached to the CPU and indirect memory references would continue to\n"
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" loop through memory if bit 15 of the target address was set. When 64KW\n"
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" support was added indirect addressing was limited to a single level\n"
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" so that the entire 16-bits of address could be used. The indirect\n"
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" addressing mode may be changed by:\n\n"
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"+sim> SET CPU MODE32K\n"
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"+sim> SET CPU MODE65K\n\n"
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" In 32KW addressing mode, the number of indirect address chaining\n"
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" operations is limited to 10000 to avoid infinite loops.\n"
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"2 Equipment Address\n"
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" The CPU is not directly accessible via an equipment address but it does\n"
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" reserve interrupt 0 (and therefore equipment address 0) for parity\n"
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" errors (never detected by the simulator), protect faults and power fail\n"
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" (not supported by the simulator).\n"
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"2 $Registers\n"
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"2 Front Panel Switches\n"
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" The 1714 front panel includes a number of switches which control the\n"
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" operation of the CPU. Note that selective stop and selective skip are\n"
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" used extensively to control execution of the System Maintenance\n"
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" Monitor.\n"
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"3 Selective Stop\n"
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" The selective stop switch controls how the 'Selective Stop' (SLS)\n"
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" instruction executes. If the switch is off, SLS executes as a\n"
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" no-operation. If the switch is on, SLS executes as a halt instruction.\n"
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" Continuing after the halt causes the CPU to resume execution at the\n"
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" instruction following the SLS.\n\n"
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"+sim> SET CPU SSTOP\n"
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"+sim> SET CPU NOSSTOP\n\n"
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"3 Selective Skip\n"
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" The selective skip switch controls how the SWS and SWN skip\n"
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" instructions execute. SWS will skip if the switch is set and SWN will\n"
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" skip if the switch is not set.\n\n"
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"+sim> SET CPU SSKIP\n"
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"+sim> SET CPU NOSSKIP\n\n"
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"3 Protect\n"
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" Each word of memory on the CDC 1700 series consists of 18-bits; 16-bits\n"
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" of data/instruction, a parity bit (which is not implemented in the\n"
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" simulator) and a program bit. If the protect switch is off, any program\n"
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" may reference any word of memory. If the protect switch is on, there are\n"
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" a set of rules which control how memory accesses work and when to\n"
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" generate a program protect violation - see one of the 1700 reference\n"
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" manuals on bitsavers.org for exact details. This means that the\n"
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" operating system can be protected from modification by application\n"
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" programs but there is no isolation between application programs.\n\n"
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"+sim> SET CPU PROTECT\n"
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"+sim> SET CPU NOPROTECT\n\n"
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" The Simulator fully implements CPU protect mode allowing protected\n"
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" operating systems such as MSOS 5 to execute. It does not implement\n"
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" peripheral protect operation which allows unprotected applications to\n"
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" directly access some unprotected peripherals.\n\n"
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" Operating systems and other programs which run with the protect switch\n"
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" on usually start up with the protect switch off, manipulate the\n"
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" protect bits in memory (using the CPB/SPB instructions) and then ask\n"
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" the operator to set the protect switch on.\n"
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"1 Configuration\n"
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" The CPU is configured with various simh SET commands.\n"
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"2 $Set commands\n";
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return scp_help(st, dptr, uptr, flag, helpString, cptr);
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}
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