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isys8010, isys8020, isys8024, isys8030, imds-225: Coverity identified problems
Corrected disk controller behaviors.
This commit is contained in:
Bill Beech
@@ -1,134 +1,134 @@
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/* system_defs.h: Intel iSBC simulator definitions
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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?? ??? 10 - Original file.
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*/
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#include <stdio.h>
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#include <ctype.h>
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#include "sim_defs.h" /* simulator defns */
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#define SET_XACK(VAL) (xack = VAL)
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//chip definitions for the iSBC-80/20
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/* set the base I/O address for the 8251 */
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#define I8251_BASE 0xEC
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#define I8251_NUM 1
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/* set the base I/O address for the 8255 */
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#define I8255_BASE_0 0xE4
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#define I8255_BASE_1 0xE8
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#define I8255_NUM 2
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/* set the base I/O address for the 8259 */
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#define I8259_BASE 0xD8
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#define I8259_NUM 1
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/* set the base and size for the EPROM on the iSBC 80/20 */
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#define ROM_BASE 0x0000
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#define ROM_SIZE 0x1000
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#define ROM_DISABLE 1
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/* set the base and size for the RAM on the iSBC 80/20 */
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#define RAM_BASE 0x3C00
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#define RAM_SIZE 0x0400
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#define RAM_DISABLE 1
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/* set INTR for CPU */
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#define INTR INT_1
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//board definitions for the multibus
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/* set the base I/O address for the iSBC 201 */
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#define SBC201_BASE 0x78
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#define SBC201_INT INT_1
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#define SBC201_NUM 0
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/* set the base I/O address for the iSBC 202 */
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#define SBC202_BASE 0x78
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#define SBC202_INT INT_1
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#define SBC202_NUM 1
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/* set the base I/O address for the iSBC 208 */
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#define SBC208_BASE 0x40
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#define SBC208_INT INT_1
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#define SBC208_NUM 0
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/* set the base for the zx-200a disk controller */
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#define ZX200A_BASE_DD 0x78
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#define ZX200A_BASE_SD 0x88
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#define ZX200A_NUM 0
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/* set the base and size for the iSBC 064 */
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#define SBC064_BASE 0x0000
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#define SBC064_SIZE 0x10000
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#define SBC064_NUM 1
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/* multibus interrupt definitions */
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#define INT_0 0x01
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#define INT_1 0x02
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#define INT_2 0x04
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#define INT_3 0x08
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#define INT_4 0x10
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#define INT_5 0x20
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#define INT_6 0x40
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#define INT_7 0x80
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/* CPU interrupts definitions */
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#define INT_R 0x200
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#define I75 0x40
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#define I65 0x20
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#define I55 0x10
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/* Memory */
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#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
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#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
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#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
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#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
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/* debug definitions */
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#define DEBUG_flow 0x0001
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#define DEBUG_read 0x0002
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#define DEBUG_write 0x0004
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#define DEBUG_level1 0x0008
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#define DEBUG_level2 0x0010
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#define DEBUG_reg 0x0020
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#define DEBUG_asm 0x0040
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#define DEBUG_xack 0x0080
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#define DEBUG_all 0xFFFF
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/* Simulator stop codes */
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#define STOP_RSRV 1 /* must be 1 */
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#define STOP_HALT 2 /* HALT */
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#define STOP_IBKPT 3 /* breakpoint */
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#define STOP_OPCODE 4 /* Invalid Opcode */
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#define STOP_IO 5 /* I/O error */
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#define STOP_MEM 6 /* Memory error */
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#define STOP_XACK 7 /* XACK error */
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/* system_defs.h: Intel iSBC simulator definitions
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
|
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to deal in the Software without restriction, including without limitation
|
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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and/or sell copies of the Software, and to permit persons to whom the
|
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Software is furnished to do so, subject to the following conditions:
|
||||
|
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The above copyright notice and this permission notice shall be included in
|
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all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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||||
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?? ??? 10 - Original file.
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*/
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#include <stdio.h>
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#include <ctype.h>
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#include "sim_defs.h" /* simulator defns */
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#define SET_XACK(VAL) (xack = VAL)
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//chip definitions for the iSBC-80/20
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/* set the base I/O address for the 8251 */
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#define I8251_BASE 0xEC
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#define I8251_NUM 1
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/* set the base I/O address for the 8255 */
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#define I8255_BASE_0 0xE4
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#define I8255_BASE_1 0xE8
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#define I8255_NUM 2
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/* set the base I/O address for the 8259 */
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#define I8259_BASE 0xD8
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#define I8259_NUM 1
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/* set the base and size for the EPROM on the iSBC 80/20 */
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#define ROM_BASE 0x0000
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#define ROM_SIZE 0x1000
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#define ROM_DISABLE 1
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/* set the base and size for the RAM on the iSBC 80/20 */
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#define RAM_BASE 0x3C00
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#define RAM_SIZE 0x0400
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#define RAM_DISABLE 1
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/* set INTR for CPU */
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#define INTR INT_1
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//board definitions for the multibus
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/* set the base I/O address for the iSBC 201 */
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#define SBC201_BASE 0x78
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#define SBC201_INT INT_1
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#define SBC201_NUM 0
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/* set the base I/O address for the iSBC 202 */
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#define SBC202_BASE 0x78
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#define SBC202_INT INT_1
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#define SBC202_NUM 1
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/* set the base I/O address for the iSBC 208 */
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#define SBC208_BASE 0x40
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#define SBC208_INT INT_1
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#define SBC208_NUM 0
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/* set the base for the zx-200a disk controller */
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#define ZX200A_BASE 0x78
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#define ZX200A_INT INT_1
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#define ZX200A_NUM 0
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/* set the base and size for the iSBC 064 */
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#define SBC064_BASE 0x0000
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#define SBC064_SIZE 0x10000
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#define SBC064_NUM 1
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/* multibus interrupt definitions */
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#define INT_0 0x01
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#define INT_1 0x02
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#define INT_2 0x04
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#define INT_3 0x08
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#define INT_4 0x10
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#define INT_5 0x20
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#define INT_6 0x40
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#define INT_7 0x80
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/* CPU interrupts definitions */
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#define INT_R 0x200
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#define I75 0x40
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#define I65 0x20
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#define I55 0x10
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/* Memory */
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#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
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#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
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#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
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#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
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/* debug definitions */
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#define DEBUG_flow 0x0001
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#define DEBUG_read 0x0002
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#define DEBUG_write 0x0004
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#define DEBUG_level1 0x0008
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#define DEBUG_level2 0x0010
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#define DEBUG_reg 0x0020
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#define DEBUG_asm 0x0040
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#define DEBUG_xack 0x0080
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#define DEBUG_all 0xFFFF
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/* Simulator stop codes */
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#define STOP_RSRV 1 /* must be 1 */
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#define STOP_HALT 2 /* HALT */
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#define STOP_IBKPT 3 /* breakpoint */
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#define STOP_OPCODE 4 /* Invalid Opcode */
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#define STOP_IO 5 /* I/O error */
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#define STOP_MEM 6 /* Memory error */
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#define STOP_XACK 7 /* XACK error */
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