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https://github.com/simh/simh.git
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Notes For V3.8
The makefile now works for Linux and most Unix's. However, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.8-0 1.1.1 SCP and Libraries - BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and show (respectively) a breakpoint at the current PC. 1.1.2 GRI - Added support for the GRI-99 processor. 1.1.3 HP2100 - Added support for the BACI terminal interface. - Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions. 1.1.4 Nova - Added support for 64KW memory (implemented in third-party CPU's). 1.1.5 PDP-11 - Added support for DC11, RC11, KE11A, KG11A. - Added modem control support for DL11. - Added ASCII character support for all 8b devices. 1.2 3.8-1 1.2.1 SCP and libraries - Added capability to set line connection order for terminal multiplexers. 1.2.2 HP2100 - Added support for 12620A/12936A privileged interrupt fence. - Added support for 12792C eight-channel asynchronous multiplexer. 1.3 3.8-2 1.3.1 SCP and libraries - Added line history capability for *nix hosts. - Added "SHOW SHOW" and "SHOW <dev> SHOW" commands. 1.3.2 1401 - Added "no rewind" option to magtape boot. 1.3.3 PDP-11 - Added RD32 support to RQ - Added debug support to RL 1.3.4 PDP-8 - Added FPP support (many thanks to Rick Murphy for debugging the code) 1.3.5 VAX-11/780 - Added AUTORESTART switch support, and VMS REBOOT command support 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
This commit is contained in:
committed by
Mark Pizzolato
parent
35eac703c3
commit
a9fd3dd518
@@ -124,21 +124,21 @@
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/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */
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#define ML_LR_TEST(r) if ((uint32)((r) & 0xFFFFFF) > 0x200000) RSVD_OPND_FAULT
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#define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT
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/* 780 microcode patch 38 - only test PxBR<31>=1 and xBR<1:0> = 0 */
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/* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */
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#define ML_PXBR_TEST(r) if ((((r) & 0x80000000) == 0) || \
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((r) & 0x00000003)) RSVD_OPND_FAULT
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#define ML_SBR_TEST(r) if ((r) & 0x00000003) RSVD_OPND_FAULT
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#define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \
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((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT
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#define ML_SBR_TEST(r) if ((((uint32)(r)) & 0xC0000003) != 0) RSVD_OPND_FAULT
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/* 780 microcode patch 78 - only test xCBB<1:0> = 0 */
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#define ML_PA_TEST(r) if ((r) & 0x00000003) RSVD_OPND_FAULT
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#define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
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#define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT
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#define LP_MBZ84_TEST(r) if ((r) & 0xF8C00000) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((r) & 0x7FC00000) RSVD_OPND_FAULT
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#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
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#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
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/* Memory */
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@@ -1,6 +1,6 @@
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/* vax780_sbi.c: VAX 11/780 SBI
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Copyright (c) 2004-2008, Robert M Supnik
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Copyright (c) 2004-2011, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -27,9 +27,10 @@
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sbi bus controller
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21-Mar-2011 RMS Added autoreboot capability (from Mark Pizzalato)
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31-May-2008 RMS Fixed machine_check calling sequence (found by Peter Schorn)
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03-May-2006 RMS Fixed writes to ACCS
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28-May-08 RMS Inlined physical memory routines
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28-May-2008 RMS Inlined physical memory routines
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*/
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#include "vax_defs.h"
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@@ -100,6 +101,7 @@ uint32 sbi_sc = 0; /* SBI silo comparator *
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uint32 sbi_mt = 0; /* SBI maintenance */
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uint32 sbi_er = 0; /* SBI error status */
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uint32 sbi_tmo = 0; /* SBI timeout addr */
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char cpu_boot_cmd[CBUFSIZE] = { 0 }; /* boot command */
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static t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
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static t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);
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@@ -132,6 +134,8 @@ t_stat sbi_reset (DEVICE *dptr);
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void sbi_set_tmo (int32 pa);
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void uba_eval_int (void);
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t_stat vax780_boot (int32 flag, char *ptr);
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t_stat vax780_boot_parse (int32 flag, char *ptr);
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t_stat cpu_boot (int32 unitno, DEVICE *dptr);
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extern t_stat vax780_fload (int flag, char *cptr);
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extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
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@@ -175,6 +179,7 @@ REG sbi_reg[] = {
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{ HRDATA (SBIMT, sbi_mt, 32) },
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{ HRDATA (SBIER, sbi_er, 32) },
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{ HRDATA (SBITMO, sbi_tmo, 32) },
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{ BRDATA (BOOTCMD, cpu_boot_cmd, 16, 8, CBUFSIZE), REG_HRO },
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{ NULL }
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};
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@@ -246,7 +251,7 @@ if ((ipl < IPL_TTINT) && (tti_int || tto_int)) /* console int */
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if (ipl >= IPL_SMAX) /* ipl >= sw max? */
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return 0;
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if ((t = SISR & sw_int_mask[ipl]) == 0)
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return 0; /* eligible req */
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return 0; /* eligible req */
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for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */
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if ((t >> i) & 1) /* req != 0? int */
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return i;
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@@ -587,11 +592,18 @@ sbi_er = sbi_er & ~SBIER_TMOW1C; /* clr SBIER<tmo> etc */
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return cc;
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}
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/* Console entry */
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/* Console entry - only reached if CONHALT is set (AUTORESTART is set */
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int32 con_halt (int32 code, int32 cc)
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{
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ABORT (STOP_HALT);
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if ((cpu_boot_cmd[0] == 0) || /* saved boot cmd? */
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(vax780_boot_parse (0, cpu_boot_cmd) != SCPE_OK) || /* reparse the boot cmd */
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(reset_all (0) != SCPE_OK) || /* reset the world */
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(cpu_boot (0, NULL) != SCPE_OK)) /* set up boot code */
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ABORT (STOP_BOOT); /* any error? */
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printf ("Rebooting...\n");
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if (sim_log)
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fprintf (sim_log, "Rebooting...\n");
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return cc;
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}
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@@ -604,6 +616,19 @@ return cc;
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t_stat vax780_boot (int32 flag, char *ptr)
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{
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t_stat r;
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r = vax780_boot_parse (flag, ptr); /* parse the boot cmd */
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if (r != SCPE_OK) /* error? */
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return r;
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strncpy (cpu_boot_cmd, ptr, CBUFSIZE); /* save for reboot */
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return run_cmd (flag, "CPU");
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}
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/* Parse boot command, set up registers - also used on reset */
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t_stat vax780_boot_parse (int32 flag, char *ptr)
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{
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char gbuf[CBUFSIZE];
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char *slptr, *regptr;
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int32 i, r5v, unitno;
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@@ -649,7 +674,7 @@ for (i = 0; boot_tab[i].name != NULL; i++) {
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R[3] = unitno;
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R[4] = 0;
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R[5] = r5v;
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return run_cmd (flag, "CPU");
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return SCPE_OK;
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}
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}
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return SCPE_NOFNC;
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@@ -662,8 +687,8 @@ t_stat cpu_boot (int32 unitno, DEVICE *dptr)
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t_stat r;
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printf ("Loading boot code from vmb.exe\n");
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if (sim_log) fprintf (sim_log,
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"Loading boot code from vmb.exe\n");
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if (sim_log)
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fprintf (sim_log, "Loading boot code from vmb.exe\n");
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r = load_cmd (0, "-O vmb.exe 200");
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if (r != SCPE_OK)
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return r;
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@@ -1,6 +1,6 @@
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/* vax780_stddev.c: VAX 11/780 standard I/O devices
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Copyright (c) 1998-2008, Robert M Supnik
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Copyright (c) 1998-2011, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -29,6 +29,7 @@
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todr TODR clock
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tmr interval timer
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21-Mar-11 RMS Added reboot capability
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17-Aug-08 RMS Resync TODR on any clock reset
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18-Jun-07 RMS Added UNIT_IDLE flag to console input, clock
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29-Oct-06 RMS Added clock coscheduler function
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@@ -207,6 +208,8 @@ t_stat fl_wr_txdb (int32 data);
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t_bool fl_test_xfr (UNIT *uptr, t_bool wr);
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void fl_protocol_error (void);
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extern int32 con_halt (int32 code, int32 cc);
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/* TTI data structures
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tti_dev TTI device descriptor
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@@ -778,16 +781,20 @@ else {
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}
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else if (sel == TXDB_MISC) { /* misc function? */
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switch (data & MISC_MASK) { /* case on function */
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case MISC_CLWS:
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comm_region[COMM_WRMS] = 0;
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case MISC_CLCS:
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comm_region[COMM_CLDS] = 0;
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break;
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case MISC_SWDN:
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ABORT (STOP_SWDN);
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break;
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case MISC_BOOT:
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ABORT (STOP_BOOT);
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con_halt (0, 0); /* set up reboot */
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break;
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}
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}
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@@ -619,7 +619,7 @@ for (i = 0; i < bc; i = i + pbc) { /* loop by pages */
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if (!uba_map_addr (ba + i, &ma)) /* page inv or NXM? */
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return (bc - i);
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pbc = VA_PAGSIZE - VA_GETOFF (ma); /* left in page */
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if (pbc > (bc - i)) /* limit to rem xfr */
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if (pbc > (bc - i)) /* limit to rem xfr */
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pbc = bc - i;
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if (DEBUG_PRI (uba_dev, UBA_DEB_XFR))
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fprintf (sim_deb, ">>UBA: 8b read, ma = %X, bc = %X\n", ma, pbc);
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106
VAX/vax_cpu.c
106
VAX/vax_cpu.c
@@ -1,6 +1,6 @@
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/* vax_cpu.c: VAX CPU
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Copyright (c) 1998-2010, Robert M Supnik
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Copyright (c) 1998-2011, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -25,6 +25,7 @@
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cpu VAX central processor
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23-Mar-11 RMS Revised for new idle design (from Mark Pizzolato)
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24-Apr-10 RMS Added OLDVMS idle timer option
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Fixed bug in SET CPU IDLE
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21-May-08 RMS Removed inline support
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@@ -175,8 +176,9 @@
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#define UNIT_CONH (1u << UNIT_V_CONH)
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#define UNIT_MSIZE (1u << UNIT_V_MSIZE)
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#define GET_CUR acc = ACC_MASK (PSL_GETCUR (PSL))
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#define VAX_IDLE_DFLT 1000
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#define OLD_IDLE_DFLT 200
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#define VAX_IDLE_VMS 0x1
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#define VAX_IDLE_ULT 0x2
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#define VAX_IDLE_QUAD 0x3
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#define OPND_SIZE 16
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#define INST_SIZE 52
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@@ -261,9 +263,8 @@ int32 cpu_astop = 0;
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int32 mchk_va, mchk_ref; /* mem ref param */
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int32 ibufl, ibufh; /* prefetch buf */
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int32 ibcnt, ppc; /* prefetch ctl */
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uint32 cpu_idle_ipl_mask = 0x8; /* idle if on IPL 3 */
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uint32 cpu_idle_type = 1; /* default to VMS */
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int32 cpu_idle_wait = VAX_IDLE_DFLT; /* for these cycles */
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uint32 cpu_idle_mask = VAX_IDLE_VMS; /* idle mask */
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uint32 cpu_idle_type = 1; /* default VMS */
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jmp_buf save_env;
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REG *pcq_r = NULL; /* PC queue reg ptr */
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int32 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
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@@ -387,8 +388,8 @@ int32 cpu_get_vsw (int32 sw);
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SIM_INLINE int32 get_istr (int32 lnt, int32 acc);
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int32 ReadOcta (int32 va, int32 *opnd, int32 j, int32 acc);
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t_bool cpu_show_opnd (FILE *st, InstHistory *h, int32 line);
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int32 cpu_psl_ipl_idle (int32 newpsl);
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t_stat cpu_idle_svc (UNIT *uptr);
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void cpu_idle (void);
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/* CPU data structures
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@@ -445,9 +446,8 @@ REG cpu_reg[] = {
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{ FLDATA (CRDERR, crd_err, 0) },
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{ FLDATA (MEMERR, mem_err, 0) },
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{ FLDATA (HLTPIN, hlt_pin, 0) },
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{ HRDATA (IDLE_IPL, cpu_idle_ipl_mask, 16), REG_HIDDEN },
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{ DRDATA (IDLE_TYPE, cpu_idle_type, 4), REG_HRO },
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{ DRDATA (IDLE_WAIT, cpu_idle_wait, 16), REG_HIDDEN },
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{ HRDATA (IDLE_MASK, cpu_idle_mask, 16), REG_HIDDEN },
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{ DRDATA (IDLE_INDX, cpu_idle_type, 4), REG_HRO },
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{ BRDATA (PCQ, pcq, 16, 32, PCQ_SIZE), REG_RO+REG_CIRC },
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{ HRDATA (PCQP, pcq_p, 6), REG_HRO },
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{ HRDATA (BADABO, badabo, 32), REG_HRO },
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@@ -1571,6 +1571,16 @@ for ( ;; ) {
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case TSTL:
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CC_IIZZ_L (op0); /* set cc's */
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if ((cc == CC_Z) &&
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((((PSL & PSL_IS) != 0) && /* on IS? */
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(PSL_GETIPL (PSL) == 0x1) && /* at IPL 1? */
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((cpu_idle_mask & VAX_IDLE_ULT) != 0))|| /* running Ultrix or friends? */
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((PSL_GETIPL (PSL) == 0x0) && /* at IPL 0? */
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((fault_PC & 0x80000000) != 0) && /* in system space? */
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((PC - fault_PC) == 6) && /* 6 byte instruction? */
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((fault_PC & 0x7fffffff) < 0x4000) && /* in low system space? */
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((cpu_idle_mask & VAX_IDLE_QUAD) != 0)))) /* running Quad or friends? */
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cpu_idle(); /* idle loop */
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break;
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/* Single operand instructions with source, read/write - op src.mx
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@@ -2109,14 +2119,20 @@ for ( ;; ) {
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case BRB:
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BRANCHB (brdisp); /* branch */
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if ((PC == fault_PC) && (PSL_GETIPL (PSL) == 0x1F))
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ABORT (STOP_LOOP);
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if (PC == fault_PC) { /* to self? */
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if (PSL_GETIPL (PSL) == 0x1F) /* int locked out? */
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ABORT (STOP_LOOP); /* infinite loop */
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cpu_idle (); /* idle loop */
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}
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break;
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case BRW:
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BRANCHW (brdisp); /* branch */
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if ((PC == fault_PC) && (PSL_GETIPL (PSL) == 0x1F))
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ABORT (STOP_LOOP);
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if (PC == fault_PC) { /* to self? */
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if (PSL_GETIPL (PSL) == 0x1F) /* int locked out? */
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ABORT (STOP_LOOP); /* infinite loop */
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cpu_idle (); /* idle loop */
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}
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break;
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case BSBB:
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@@ -2348,8 +2364,13 @@ for ( ;; ) {
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*/
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case BBS:
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if (op_bb_n (opnd, acc)) /* br if bit set */
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if (op_bb_n (opnd, acc)) { /* br if bit set */
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BRANCHB (brdisp);
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if (((PSL & PSL_IS) != 0) && /* on IS? */
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(PSL_GETIPL (PSL) == 0x3) && /* at IPL 3? */
|
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((cpu_idle_mask & VAX_IDLE_VMS) != 0)) /* running VMS? */
|
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cpu_idle (); /* idle loop */
|
||||
}
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break;
|
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case BBC:
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@@ -3071,24 +3092,15 @@ opnd[j++] = Read (va + 12, L_LONG, acc);
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return j;
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}
|
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|
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/* Check new PSL IPL for idle start
|
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Checked only on exception or REI, not on MTPR #IPL,
|
||||
to allow for local locking within the idle loop */
|
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/* Schedule idle before the next instruction */
|
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|
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int32 cpu_psl_ipl_idle (int32 newpsl)
|
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void cpu_idle (void)
|
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{
|
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if (((newpsl ^ PSL) & PSL_IPL) != 0) {
|
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sim_cancel (&cpu_unit);
|
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if (sim_idle_enab && ((newpsl & PSL_CUR) == 0)) {
|
||||
uint32 newipl = PSL_GETIPL (newpsl);
|
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if (cpu_idle_ipl_mask & (1u << newipl))
|
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sim_activate (&cpu_unit, cpu_idle_wait);
|
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}
|
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}
|
||||
return newpsl;
|
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sim_activate_abs (&cpu_unit, 0);
|
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return;
|
||||
}
|
||||
|
||||
/* Idle timer has expired with no PSL change */
|
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/* Idle service */
|
||||
|
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t_stat cpu_idle_svc (UNIT *uptr)
|
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{
|
||||
@@ -3108,15 +3120,17 @@ PSL = PSL_IS | PSL_IPL1F;
|
||||
SISR = 0;
|
||||
ASTLVL = 4;
|
||||
mapen = 0;
|
||||
if (M == NULL)
|
||||
M = (uint32 *) calloc (((uint32) MEMSIZE) >> 2, sizeof (uint32));
|
||||
if (M == NULL)
|
||||
return SCPE_MEM;
|
||||
pcq_r = find_reg ("PCQ", NULL, dptr);
|
||||
if (pcq_r)
|
||||
FLUSH_ISTR; /* init I-stream */
|
||||
if (M == NULL) { /* first time init? */
|
||||
sim_brk_types = sim_brk_dflt = SWMASK ('E');
|
||||
pcq_r = find_reg ("PCQ", NULL, dptr);
|
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if (pcq_r == NULL)
|
||||
return SCPE_IERR;
|
||||
pcq_r->qptr = 0;
|
||||
else return SCPE_IERR;
|
||||
sim_brk_types = sim_brk_dflt = SWMASK ('E');
|
||||
M = (uint32 *) calloc (((uint32) MEMSIZE) >> 2, sizeof (uint32));
|
||||
if (M == NULL)
|
||||
return SCPE_MEM;
|
||||
}
|
||||
return build_dib_tab ();
|
||||
}
|
||||
|
||||
@@ -3381,17 +3395,16 @@ return more;
|
||||
struct os_idle {
|
||||
char *name;
|
||||
uint32 mask;
|
||||
int32 value;
|
||||
};
|
||||
|
||||
static struct os_idle os_tab[] = {
|
||||
{ "VMS", 0x8, VAX_IDLE_DFLT },
|
||||
{ "NETBSD", 0x2, VAX_IDLE_DFLT },
|
||||
{ "ULTRIX", 0x2, VAX_IDLE_DFLT },
|
||||
{ "OPENBSD", 0x1, VAX_IDLE_DFLT },
|
||||
{ "32V", 0x1, VAX_IDLE_DFLT },
|
||||
{ "OLDVMS", 0xB, OLD_IDLE_DFLT },
|
||||
{ NULL, 0, 0 }
|
||||
{ "VMS", VAX_IDLE_VMS },
|
||||
{ "NETBSD", VAX_IDLE_ULT },
|
||||
{ "ULTRIX", VAX_IDLE_ULT },
|
||||
{ "OPENBSD", VAX_IDLE_QUAD },
|
||||
{ "32V", VAX_IDLE_QUAD },
|
||||
{ "ALL", VAX_IDLE_VMS|VAX_IDLE_ULT|VAX_IDLE_QUAD },
|
||||
{ NULL, 0 }
|
||||
};
|
||||
|
||||
/* Set and show idle */
|
||||
@@ -3404,8 +3417,7 @@ if (cptr != NULL) {
|
||||
for (i = 0; os_tab[i].name != NULL; i++) {
|
||||
if (strcmp (os_tab[i].name, cptr) == 0) {
|
||||
cpu_idle_type = i + 1;
|
||||
cpu_idle_ipl_mask = os_tab[i].mask;
|
||||
cpu_idle_wait = os_tab[i].value;
|
||||
cpu_idle_mask = os_tab[i].mask;
|
||||
return sim_set_idle (uptr, val, NULL, desc);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* vax_cpu1.c: VAX complex instructions
|
||||
|
||||
Copyright (c) 1998-2008, Robert M Supnik
|
||||
Copyright (c) 1998-2011, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -23,6 +23,7 @@
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
23-Mar-11 RMS Revised idle design (from Mark Pizzolato)
|
||||
28-May-08 RMS Inlined physical memory routines
|
||||
29-Apr-07 RMS Separated base register access checks for 11/780
|
||||
10-May-06 RMS Added access check on system PTE for 11/780
|
||||
@@ -109,7 +110,6 @@ extern t_bool chk_tb_ent (uint32 va);
|
||||
extern int32 ReadIPR (int32 rg);
|
||||
extern void WriteIPR (int32 rg, int32 val);
|
||||
extern t_bool BadCmPSL (int32 newpsl);
|
||||
extern int32 cpu_psl_ipl_idle (int32 newpsl);
|
||||
|
||||
extern jmp_buf save_env;
|
||||
|
||||
@@ -1137,9 +1137,9 @@ else {
|
||||
}
|
||||
}
|
||||
if (ei > 0) /* if int, new IPL */
|
||||
PSL = cpu_psl_ipl_idle (newpsl | (ipl << PSL_V_IPL));
|
||||
else PSL = cpu_psl_ipl_idle (newpsl | /* exc, old IPL/1F */
|
||||
((newpc & 1)? PSL_IPL1F: (oldpsl & PSL_IPL)) | (oldcur << PSL_V_PRV));
|
||||
PSL = newpsl | (ipl << PSL_V_IPL);
|
||||
else PSL = newpsl | /* exc, old IPL/1F */
|
||||
((newpc & 1)? PSL_IPL1F: (oldpsl & PSL_IPL)) | (oldcur << PSL_V_PRV);
|
||||
if (DEBUG_PRI (cpu_dev, LOG_CPU_I))
|
||||
fprintf (sim_deb, ">>IEX: PC=%08x, PSL=%08x, SP=%08x, VEC=%08x, nPSL=%08x, nSP=%08x\n",
|
||||
PC, oldpsl, oldsp, vec, PSL, SP);
|
||||
@@ -1249,7 +1249,7 @@ else STK[oldcur] = SP;
|
||||
if (DEBUG_PRI (cpu_dev, LOG_CPU_R))
|
||||
fprintf (sim_deb, ">>REI: PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x\n",
|
||||
PC, PSL, SP - 8, newpc, newpsl, ((newpsl & IS)? IS: STK[newcur]));
|
||||
PSL = cpu_psl_ipl_idle ((PSL & PSL_TP) | (newpsl & ~CC_MASK)); /* set PSL */
|
||||
PSL = (PSL & PSL_TP) | (newpsl & ~CC_MASK); /* set PSL */
|
||||
if (PSL & PSL_IS) /* set new stack */
|
||||
SP = IS;
|
||||
else {
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* vax_sys.c: VAX simulator interface
|
||||
|
||||
Copyright (c) 1998-2008, Robert M Supnik
|
||||
Copyright (c) 1998-2011, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -23,6 +23,7 @@
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
21-Mar-11 RMS Modified string for STOP_BOOT message
|
||||
19-Nov-08 RMS Moved bad block routine to I/O library
|
||||
03-Nov-05 RMS Added 780 stop codes
|
||||
04-Sep-05 RMS Fixed missing assignment (found by Peter Schorn)
|
||||
@@ -100,7 +101,7 @@ const char *sim_stop_messages[] = {
|
||||
"Infinite loop",
|
||||
"Sanity timer expired",
|
||||
"Software done",
|
||||
"Reboot requested",
|
||||
"Reboot request failed",
|
||||
"Unknown error",
|
||||
"Unknown abort code"
|
||||
};
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* vax_syscm.c: PDP-11 compatibility mode symbolic decode and parse
|
||||
|
||||
Copyright (c) 1993-2008, Robert M Supnik
|
||||
Copyright (c) 1993-2010, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -23,6 +23,8 @@
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
22-May-10 RMS Fixed t_addr printouts for 64b big-endian systems
|
||||
(found by Mark Pizzolato)
|
||||
12-Nov-06 RMS Fixed operand order in EIS instructions (found by W.F.J. Mueller)
|
||||
27-Sep-05 RMS Fixed warnings compiling with 64b addresses
|
||||
15-Sep-04 RMS Cloned from pdp11_sys.c
|
||||
@@ -242,13 +244,13 @@ switch (mode) {
|
||||
case 6:
|
||||
if (reg != 7)
|
||||
fprintf (of, "%-X(%s)", nval, rname[reg]);
|
||||
else fprintf (of, "%-X", (nval + addr + 4) & 0177777);
|
||||
else fprintf (of, "%-X", (int32)((nval + addr + 4) & 0177777));
|
||||
break;
|
||||
|
||||
case 7:
|
||||
if (reg != 7)
|
||||
fprintf (of, "@%-X(%s)", nval, rname[reg]);
|
||||
else fprintf (of, "@%-X", (nval + addr + 4) & 0177777);
|
||||
else fprintf (of, "@%-X", (int32)((nval + addr + 4) & 0177777));
|
||||
break;
|
||||
} /* end case */
|
||||
|
||||
@@ -326,7 +328,7 @@ for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
||||
case I_V_BR: /* cond branch */
|
||||
fprintf (of, "%s ", opcode[i]);
|
||||
brdisp = (l8b + l8b + ((l8b & 0200)? 0177002: 2)) & 0177777;
|
||||
fprintf (of, "%-X", (addr + brdisp) & 0177777);
|
||||
fprintf (of, "%-X", (int32)((addr + brdisp) & 0177777));
|
||||
break;
|
||||
|
||||
case I_V_8B: /* 8b */
|
||||
@@ -336,7 +338,7 @@ for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
|
||||
case I_V_SOB: /* sob */
|
||||
fprintf (of, "%s %s,", opcode[i], rname[srcr]);
|
||||
brdisp = (dstm * 2) - 2;
|
||||
fprintf (of, "%-X", (addr - brdisp) & 0177777);
|
||||
fprintf (of, "%-X", (int32)((addr - brdisp) & 0177777));
|
||||
break;
|
||||
|
||||
case I_V_RSOP: /* rsop */
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* vax_sysdev.c: VAX 3900 system-specific logic
|
||||
|
||||
Copyright (c) 1998-2008, Robert M Supnik
|
||||
Copyright (c) 1998-2011, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -32,6 +32,7 @@
|
||||
cso console storage output
|
||||
sysd system devices (SSC miscellany)
|
||||
|
||||
23-Dec-10 RMS Added power clear call to boot routine (from Mark Pizzolato)
|
||||
25-Oct-05 RMS Automated CMCTL extended memory
|
||||
16-Aug-05 RMS Fixed C++ declaration and cast problems
|
||||
10-Mar-05 RMS Fixed bug in timer schedule routine (from Mark Hittinger)
|
||||
@@ -275,6 +276,7 @@ extern void txcs_wr (int32 dat);
|
||||
extern void txdb_wr (int32 dat);
|
||||
extern void ioreset_wr (int32 dat);
|
||||
extern uint32 sim_os_msec();
|
||||
extern void cpu_idle (void);
|
||||
|
||||
/* ROM data structures
|
||||
|
||||
@@ -1556,6 +1558,7 @@ if (*rom == 0) { /* no boot? */
|
||||
if (r != SCPE_OK)
|
||||
return r;
|
||||
}
|
||||
sysd_powerup ();
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user