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PDP11: 11/70 read-only registers must not return NXM on write

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17 777 740 - 17 777 742, read-only error address registers,
and 17 777 764, a read-only System ID register,

and are not handled in the CPU70_wr() routine, which means for these
addresses the routine returns NXM, which then translates to "bus timeout"
(no response to address), and then, as a result, trap to vector 4.

That is incorrect, IMO.

These locations are read-only yet the address gets decoded, and even
though writing does not have any effect, the write routine for these
addresses should return SCPE_OK.
This commit is contained in:
Tony Lawrence
2023-10-08 20:48:28 -04:00
committed by Mark Pizzolato
parent 68e071407e
commit abd1834380
1 changed files with 6 additions and 0 deletions
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6
PDP11/pdp11_cpumod.c
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@@ -685,6 +685,9 @@ return SCPE_NXM; /* unimplemented */
t_stat CPU70_wr (int32 data, int32 pa, int32 access) t_stat CPU70_wr (int32 data, int32 pa, int32 access)
{ {
switch ((pa >> 1) & 017) { /* decode pa<4:1> */ switch ((pa >> 1) & 017) { /* decode pa<4:1> */
case 000:
case 001:
return SCPE_OK; /* error addr */
case 002: /* MEMERR */ case 002: /* MEMERR */
ODD_SHF (data); ODD_SHF (data);
@@ -708,6 +711,9 @@ switch ((pa >> 1) & 017) { /* decode pa<4:1> */
case 011: /* high size */ case 011: /* high size */
return SCPE_OK; return SCPE_OK;
case 012: /* system ID */
return SCPE_OK;
case 013: /* CPUERR */ case 013: /* CPUERR */
CPUERR = 0; CPUERR = 0;
return SCPE_OK; return SCPE_OK;