Notes For V3.3

RESTRICTION: The HP DS disk is not debugged.  DO NOT enable this
feature for normal operations.
WARNING: Massive changes in the PDP-11 make all previous SAVEd
file obsolete.  Do not attempt to use a PDP-11 SAVE file from a
prior release with V3.3!

1. New Features in 3.3

1.1 SCP

- Added -p (powerup) qualifier to RESET
- Changed SET <unit> ONLINE/OFFLINE to SET <unit> ENABLED/DISABLED
- Moved SET DEBUG under SET CONSOLE hierarchy
- Added optional parameter value to SHOW command
- Added output file option to SHOW command

1.2 PDP-11

- Separated RH Massbus adapter from RP controller
- Added TU tape support
- Added model emulation framework
- Added model details

1.3 VAX

- Separated out CVAX-specific features from core instruction simulator
- Implemented capability for CIS, octaword, compatibility mode instructions
- Added instruction display and parse for compatibility mode
- Changed SET CPU VIRTUAL=n to SHOW CPU VIRTUAL=n
- Added =n optional parameter to SHOW CPU HISTORY

1.4 Unibus/Qbus simulators (PDP-11, VAX, PDP-10)

- Simplified DMA API's
- Modified DMA peripherals to use simplified API's

1.5 HP2100 (all changes from Dave Bryan)

CPU	- moved MP into its own device; added MP option jumpers
	- modified DMA to allow disabling
	- modified SET CPU 2100/2116 to truncate memory > 32K
	- added -F switch to SET CPU to force memory truncation
	- modified WRU to be REG_HRO
	- added BRK and DEL to save console settings

DR	- provided protected tracks and "Writing Enabled" status bit
	- added "parity error" status return on writes for 12606
	- added track origin test for 12606
	- added SCP test for 12606
	- added "Sector Flag" status bit
	- added "Read Inhibit" status bit for 12606
	- added TRACKPROT modifier

LPS	- added SET OFFLINE/ONLINE, POWEROFF/POWERON
	- added fast/realistic timing
	- added debug printouts

LPT	- added SET OFFLINE/ONLINE, POWEROFF/POWERON

PTR	- added paper tape loop mode, DIAG/READER modifiers to PTR
	- added PV_LEFT to PTR TRLLIM register

CLK	- modified CLK to permit disable

1.6 IBM 1401, IBM 1620, Interdata 16b, SDS 940, PDP-10

- Added instruction history

1.7 H316, PDP-15, PDP-8

- Added =n optional value to SHOW CPU HISTORY

2. Bugs Fixed in 3.3

2.1 SCP

- Fixed comma-separated SET options (from Dave Bryan)
- Fixed duplicate HELP displays with user-specified commands

2.2 PDP-10

- Replicated RP register state per drive
- Fixed TU to set FCE on short record
- Fixed TU to return bit<15> in drive type
- Fixed TU format specification, 1:0 are don't cares
- Fixed TU handling of TMK status
- Fixed TU handling of DONE, ATA at end of operation
- Implemented TU write check

2.3 PDP-11

- Replicated RP register state per drive
- Fixed RQ, TQ to report correct controller type and stage 1 configuration
  flags on a Unibus system
- Fixed HK CS2<output_ready> flag

2.4 VAX

- Fixed parsing of indirect displacement modes in instruction input

2.5 HP2100 (all fixes from Dave Bryan)

CPU	- fixed S-register behavior on 2116
	- fixed LIx/MIx behavior for DMA on 2116 and 2100
	- fixed LIx/MIx behavior for empty I/O card slots

DP	- fixed enable/disable from either device
	- fixed ANY ERROR status for 12557A interface
	- fixed unattached drive status for 12557A interface
	- status cmd without prior STC DC now completes (12557A)
	- OTA/OTB CC on 13210A interface also does CLC CC
	- fixed RAR model
	- fixed seek check on 13210 if sector out of range

DQ	- fixed enable/disable from either device
	- shortened xtime from 5 to 3 (drive avg 156KW/second)
	- fixed not ready/any error status
	- fixed RAR model

DR	- fixed enable/disable from either device
	- fixed sector return in status word
	- fixed DMA last word write, incomplete sector fill value
	- fixed 12610 SFC operation
	- fixed current-sector determination

IPL	- fixed enable/disable from either device

LPS	- fixed status returns for error conditions
	- fixed handling of non-printing characters
	- fixed handling of characters after column 80
	- improved timing model accuracy for RTE

LPT	- fixed status returns for error conditions
	- fixed TOF handling so form remains on line 0

SYS	- fixed display of CCA/CCB/CCE instructions

2.5 PDP-15

FPP	- fixed URFST to mask low 9b of fraction
	- fixed exception PC setting

Interdata/id16_cpu.c

@@ -25,6 +25,7 @@
 
    cpu			Interdata 16b CPU
 
+   07-Nov-04	RMS	Added instruction history
    22-Sep-03	RMS	Added additional instruction decode types
    07-Feb-03	RMS	Fixed bug in SETM, SETMR (found by Mark Pizzolato)
 
@@ -151,6 +152,17 @@
 #define UNIT_816E	(1 << UNIT_V_816E)
 #define UNIT_TYPE	(UNIT_ID4 | UNIT_716 | UNIT_816 | UNIT_816E)
 
+#define HIST_MIN	64
+#define HIST_MAX	65536
+struct InstHistory {
+	uint16		vld;
+	uint16		pc;
+	uint16		ir1;
+	uint16		ir2;
+	uint16		r1;
+	uint16		ea;
+	uint16		opnd; };
+
 #define SEXT16(x)	(((x) & SIGN16)? ((int32) ((x) | 0xFFFF8000)): \
 			 ((int32) ((x) & 0x7FFF)))
 #define CC_GL_16(x)	if ((x) & SIGN16) cc = CC_L; \
@@ -190,7 +202,9 @@ REG *pcq_r = NULL;					/* PC queue reg ptr */
 uint32 dec_flgs = 0;					/* decode flags */
 uint32 fp_in_hwre = 0;					/* ucode/hwre fp */
 uint32 pawidth = PAWIDTH16;				/* phys addr mask */
-uint32 cpu_log = 0;					/* debug logging */
+uint32 hst_p = 0;					/* history pointer */
+uint32 hst_lnt = 0;					/* history length */
+struct InstHistory *hst = NULL;				/* instruction history */
 struct BlockIO blk_io;					/* block I/O status */
 uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL };
 
@@ -216,6 +230,8 @@ t_stat cpu_reset (DEVICE *dptr);
 t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
 t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc);
 t_stat cpu_set_consint (UNIT *uptr, int32 val, char *cptr, void *desc);
+t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc);
+t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc);
 
 extern t_bool devtab_init (void);
 extern void int_eval (void);
@@ -478,7 +494,6 @@ REG cpu_reg[] = {
 	{ BRDATA (PCQ, pcq, 16, 16, PCQ_SIZE), REG_RO+REG_CIRC },
 	{ HRDATA (PCQP, pcq_p, 6), REG_HRO },
 	{ HRDATA (WRU, sim_int_char, 8) },
-	{ HRDATA (DBGLOG, cpu_log, 16), REG_HIDDEN },
 	{ HRDATA (BLKIOD, blk_io.dfl, 16), REG_HRO },
 	{ HRDATA (BLKIOC, blk_io.cur, 16), REG_HRO },
 	{ HRDATA (BLKIOE, blk_io.end, 16), REG_HRO },
@@ -500,6 +515,8 @@ MTAB cpu_mod[] = {
 	{ UNIT_TYPE, UNIT_816E, "8/16E", "816E", &cpu_set_model },
 	{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, NULL, "CONSINT",
 		&cpu_set_consint, NULL, NULL },
+	{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
+	  &cpu_set_hist, &cpu_show_hist },
 	{ 0 }  };
 
 DEVICE cpu_dev = {
@@ -659,6 +676,17 @@ case OP_RXH:						/* reg-mem halfword */
 default:
 	return SCPE_IERR;  }
 
+if (hst_lnt) {						/* instruction history? */
+	hst[hst_p].vld = 1;
+	hst[hst_p].pc = oPC;
+	hst[hst_p].ir1 = ir1;
+	hst[hst_p].ir2 = ir2;
+	hst[hst_p].r1 = R[r1];
+	hst[hst_p].ea = ea;
+	hst[hst_p].opnd = opnd;
+	hst_p = hst_p + 1;
+	if (hst_p >= hst_lnt) hst_p = 0;  }
+
 PC = (PC + 2) & VAMASK;					/* increment PC */
 switch (op) {						/* case on opcode */
 
@@ -1736,3 +1764,66 @@ if ((uptr->flags & (UNIT_716 | UNIT_816 | UNIT_816E)) == 0)
 if (PSW & PSW_AIO) SET_INT (v_DS);
 return SCPE_OK;
 }
+
+/* Set history */
+
+t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc)
+{
+uint32 i, lnt;
+t_stat r;
+
+if (cptr == NULL) {
+	for (i = 0; i < hst_lnt; i++) hst[i].vld = 0;
+	hst_p = 0;
+	return SCPE_OK;  }
+lnt = (uint32) get_uint (cptr, 10, HIST_MAX, &r);
+if ((r != SCPE_OK) || (lnt && (lnt < HIST_MIN))) return SCPE_ARG;
+hst_p = 0;
+if (hst_lnt) {
+	free (hst);
+	hst_lnt = 0;
+	hst = NULL;  }
+if (lnt) {
+	hst = calloc (sizeof (struct InstHistory), lnt);
+	if (hst == NULL) return SCPE_MEM;
+	hst_lnt = lnt;  }
+return SCPE_OK;
+}
+
+/* Show history */
+
+t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc)
+{
+uint32 op, k, di, lnt;
+char *cptr = (char *) desc;
+t_value sim_eval[4];
+t_stat r;
+struct InstHistory *h;
+extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
+	UNIT *uptr, int32 sw);
+
+if (hst_lnt == 0) return SCPE_NOFNC;			/* enabled? */
+if (cptr) {
+	lnt = (int32) get_uint (cptr, 10, hst_lnt, &r);
+	if ((r != SCPE_OK) || (lnt == 0)) return SCPE_ARG;  }
+else lnt = hst_lnt;
+di = hst_p - lnt;					/* work forward */
+if (di < 0) di = di + hst_lnt;
+fprintf (st, "PC    r1    opnd  ea    IR\n\n");
+for (k = 0; k < lnt; k++) {				/* print specified */
+	h = &hst[(di++) % hst_lnt];			/* entry pointer */
+	if (h->vld) {					/* instruction? */
+	    fprintf (st, "%04X  %04X  %04X  ", h->pc, h->r1, h->opnd);
+	    sim_eval[0] = op = (h->ir1 >> 8) & 0xFF;
+	    sim_eval[1] = h->ir1 & 0xFF;
+	    sim_eval[2] = (h->ir2 >> 8) & 0xFF;
+	    sim_eval[3] = h->ir2 & 0xFF;
+	    if (OP_TYPE (op) >= OP_RX) fprintf (st, "%04X  ", h->ea);
+	    else fprintf (st, "      ");
+	    if ((fprint_sym (st, h->pc, sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
+		fprintf (st, "(undefined) %04X", h->ir1);
+	    fputc ('\n', st);				/* end line */
+	    }						/* end if instruction */
+	}						/* end for */
+return SCPE_OK;
+}

Interdata/id32_cpu.c

@@ -25,6 +25,7 @@
 
    cpu			Interdata 32b CPU
 
+   06-Nov-04	RMS	Added =n to SHOW HISTORY
    25-Jan-04	RMS	Revised for device debug support
    31-Dec-03	RMS	Fixed bug in cpu_set_hist
    22-Sep-03	RMS	Added additional instruction decode types
@@ -561,7 +562,7 @@ MTAB cpu_mod[] = {
 	{ UNIT_TYPE, UNIT_DPFP | UNIT_832, "8/32", "832", NULL },
 	{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, NULL, "CONSINT",
 		&cpu_set_consint, NULL, NULL },
-	{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "HISTORY", "HISTORY",
+	{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
 	  &cpu_set_hist, &cpu_show_hist },
 	{ 0 }  };
 
@@ -2106,16 +2107,23 @@ return SCPE_OK;
 
 t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc)
 {
-uint32 op, k, di;
+uint32 op, k, di, lnt;
+char *cptr = (char *) desc;
 t_value sim_eval[6];
+t_stat r;
 struct InstHistory *h;
 extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
 	UNIT *uptr, int32 sw);
 
 if (hst_lnt == 0) return SCPE_NOFNC;			/* enabled? */
+if (cptr) {
+	lnt = (int32) get_uint (cptr, 10, hst_lnt, &r);
+	if ((r != SCPE_OK) || (lnt == 0)) return SCPE_ARG;  }
+else lnt = hst_lnt;
+di = hst_p - lnt;					/* work forward */
+if (di < 0) di = di + hst_lnt;
 fprintf (st, "PC     r1       operand  ea     IR\n\n");
-di = hst_p;						/* work forward */
-for (k = 0; k < hst_lnt; k++) {				/* print specified */
+for (k = 0; k < lnt; k++) {				/* print specified */
 	h = &hst[(di++) % hst_lnt];			/* entry pointer */
 	if (h->pc & HIST_PC) {				/* instruction? */
 	    fprintf (st, "%06X %08X %08X ", h->pc & VAMASK32, h->r1, h->opnd);

Interdata/id_defs.h

@@ -73,8 +73,8 @@
 /* Double precision floating point registers */
 
 struct dpr {
-	unsigned int32	h;				/* high 32b */
-	unsigned int32	l;				/* low 32b */
+	uint32		h;				/* high 32b */
+	uint32		l;				/* low 32b */
 };
 
 typedef struct dpr dpr_t;

Interdata/id_doc.txt

@@ -1,7 +1,7 @@
 To:	Users
 From:	Bob Supnik
 Subj:	Interdata 16b/32b Simulator Usage
-Date:	15-Feb-2004
+Date:	15-Nov-2004
 
 			COPYRIGHT NOTICE
 
@@ -205,6 +205,17 @@ control registers for the interrupt system.
 				most recent PC change first
 	WRU		8	interrupt character
 
+The CPU can maintain a history of the most recently executed instructions.
+This is controlled by the SET CPU HISTORY and SHOW CPU HISTORY commands:
+
+	SET CPU HISTORY		clear history buffer
+	SET CPU HISTORY=0	disable history
+	SET CPU HISTORY=n	enable history, length = n
+	SHOW CPU HISTORY	print CPU history
+	SHOW CPU HISTORY=n	print first n entries of CPU history
+
+The maximum length for the history is 65536 entries.
+
 2.2 CPU (32b)
 
 The CPU options include memory size and CPU type:
@@ -270,8 +281,9 @@ This is controlled by the SET CPU HISTORY and SHOW CPU HISTORY commands:
 
 	SET CPU HISTORY		clear history buffer
 	SET CPU HISTORY=0	disable history
-	SET CPU HISTORY=n	enable history, display length = n
+	SET CPU HISTORY=n	enable history, length = n
 	SHOW CPU HISTORY	print CPU history
+	SHOW CPU HISTORY=n	print first n entries of CPU history
 
 The maximum length for the history is 65536 entries.
 
@@ -547,7 +559,7 @@ write locked.
 	SET FDn LOCKED		set unit n write locked
 	SET FDn WRITEENABLED	set unit n write enabled
 
-Units can also be set ONLINE or OFFLINE.
+Units can also be set ENABLED or DISABLED.
 
 The floppy disk supports the BOOT command.  BOOT FDn copies an autoload
 sequence into memory and starts it running.
@@ -658,7 +670,7 @@ write locked, and to select the type of drive:
 	SET DPn 2315		set unit n to 2315 (2.5MB)
 	SET DPn 5440		set unit n to 5440 (10MB)
 
-Units can also be set ONLINE or OFFLINE.
+Units can also be set ENABLED or DISABLED.
 
 The cartridge disk supports the BOOT command.  To boot OS16/32, the hex
 form of the operating system file's extension must be placed in locations
@@ -729,7 +741,7 @@ write enabled or write locked, and to select the type of drive:
 				(300MB formatted)
 
 Note that the disk bootstraps can ONLY boot the MSM80 and MSM300.
-Units can be set ONLINE or OFFLINE.
+Units can also be set ENABLED or DISABLED.
 
 The MSM/IDC controller supports the BOOT command.  To boot OS16/32, the hex
 form of the operating system file's extension must be placed in locations
@@ -791,7 +803,7 @@ or write locked.
 	SET MTn LOCKED		set unit n write locked
 	SET MTn WRITEENABLED	set unit n write enabled
 
-Units can also be set ONLINE or OFFLINE.
+Units can also be set ENABLED or DISABLED.
 
 The magnetic tape supports the BOOT command.  BOOT MTn copies an autoload
 sequence into memory and starts it running.