mirror of
https://github.com/simh/simh.git
synced 2026-04-30 21:38:32 +00:00
Notes For V3.5-0
The source set has been extensively overhauled. For correct viewing, set Visual C++ or Emacs to have tab stops every 4 characters. 1. New Features in 3.4-1 1.1 All Ethernet devices - Added Windows user-defined adapter names (from Timothe Litt) 1.2 Interdata, SDS, HP, PDP-8, PDP-18b terminal multiplexors - Added support for SET <unit>n DISCONNECT 1.3 VAX - Added latent QDSS support - Revised autoconfigure to handle QDSS 1.4 PDP-11 - Revised autoconfigure to handle more casees 2. Bugs Fixed in 3.4-1 2.1 SCP and libraries - Trim trailing spaces on all input (for example, attach file names) - Fixed sim_sock spurious SIGPIPE error in Unix/Linux - Fixed sim_tape misallocation of TPC map array for 64b simulators 2.2 1401 - Fixed bug, CPU reset was clearing SSB through SSG 2.3 PDP-11 - Fixed bug in VH vector display routine - Fixed XU runt packet processing (found by Tim Chapman) 2.4 Interdata - Fixed bug in SHOW PAS CONN/STATS - Fixed potential integer overflow exception in divide 2.5 SDS - Fixed bug in SHOW MUX CONN/STATS 2.6 HP - Fixed bug in SHOW MUX CONN/STATS 2.7 PDP-8 - Fixed bug in SHOW TTIX CONN/STATS - Fixed bug in SET/SHOW TTOXn LOG 2.8 PDP-18b - Fixed bug in SHOW TTIX CONN/STATS - Fixed bug in SET/SHOW TTOXn LOG 2.9 Nova, Eclipse - Fixed potential integer overflow exception in divide
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
ec60bbf329
commit
b7c1eae41f
@@ -19,145 +19,144 @@
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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lp20 line printer
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lp20 line printer
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18-Mar-05 RMS Added attached test to detach routine
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29-Dec-03 RMS Fixed bug in scheduling
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25-Apr-03 RMS Revised for extended file support
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29-Sep-02 RMS Added variable vector support
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Modified to use common Unibus routines
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New data structures
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30-May-02 RMS Widened POS to 32b
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06-Jan-02 RMS Added enable/disable support
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30-Nov-01 RMS Added extended SET/SHOW support
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04-Sep-05 RMS Fixed missing return (found by Peter Schorn)
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07-Jul-05 RMS Removed extraneous externs
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18-Mar-05 RMS Added attached test to detach routine
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29-Dec-03 RMS Fixed bug in scheduling
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25-Apr-03 RMS Revised for extended file support
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29-Sep-02 RMS Added variable vector support
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Modified to use common Unibus routines
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New data structures
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30-May-02 RMS Widened POS to 32b
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06-Jan-02 RMS Added enable/disable support
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30-Nov-01 RMS Added extended SET/SHOW support
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*/
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#include "pdp10_defs.h"
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#define UNIT_DUMMY (1 << UNIT_V_UF)
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#define LP_WIDTH 132 /* printer width */
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#define UNIT_DUMMY (1 << UNIT_V_UF)
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#define LP_WIDTH 132 /* printer width */
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/* DAVFU RAM */
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#define DV_SIZE 143 /* DAVFU size */
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#define DV_DMASK 077 /* data mask per byte */
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#define DV_TOF 0 /* top of form channel */
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#define DV_MAX 11 /* max channel number */
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#define DV_SIZE 143 /* DAVFU size */
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#define DV_DMASK 077 /* data mask per byte */
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#define DV_TOF 0 /* top of form channel */
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#define DV_MAX 11 /* max channel number */
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/* Translation RAM */
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#define TX_SIZE 256 /* translation RAM */
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#define TX_AMASK (TX_SIZE - 1)
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#define TX_DMASK 07777
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#define TX_V_FL 8 /* flags */
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#define TX_M_FL 017
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/* define TX_INTR 04000 /* interrupt */
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#define TX_DELH 02000 /* delimiter */
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/* define TX_XLAT 01000 /* translate */
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/* define TX_DVFU 00400 /* DAVFU */
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#define TX_SLEW 00020 /* chan vs slew */
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#define TX_VMASK 00017 /* spacing mask */
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#define TX_CHR 0 /* states: pr char */
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#define TX_RAM 1 /* pr translation */
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#define TX_DVU 2 /* DAVFU action */
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#define TX_INT 3 /* interrupt */
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#define TX_GETFL(x) (((x) >> TX_V_FL) & TX_M_FL)
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#define TX_SIZE 256 /* translation RAM */
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#define TX_AMASK (TX_SIZE - 1)
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#define TX_DMASK 07777
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#define TX_V_FL 8 /* flags */
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#define TX_M_FL 017
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/* define TX_INTR 04000 /* interrupt */
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#define TX_DELH 02000 /* delimiter */
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/* define TX_XLAT 01000 /* translate */
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/* define TX_DVFU 00400 /* DAVFU */
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#define TX_SLEW 00020 /* chan vs slew */
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#define TX_VMASK 00017 /* spacing mask */
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#define TX_CHR 0 /* states: pr char */
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#define TX_RAM 1 /* pr translation */
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#define TX_DVU 2 /* DAVFU action */
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#define TX_INT 3 /* interrupt */
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#define TX_GETFL(x) (((x) >> TX_V_FL) & TX_M_FL)
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/* LPCSRA (765400) */
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#define CSA_GO 0000001 /* go */
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#define CSA_PAR 0000002 /* parity enable NI */
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#define CSA_V_FNC 2 /* function */
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#define CSA_M_FNC 03
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#define FNC_PR 0 /* print */
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#define FNC_TST 1 /* test */
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#define FNC_DVU 2 /* load DAVFU */
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#define FNC_RAM 3 /* load translation RAM */
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#define FNC_INTERNAL 1 /* internal function */
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#define CSA_FNC (CSA_M_FNC << CSA_V_FNC)
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#define CSA_V_UAE 4 /* Unibus addr extension */
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#define CSA_UAE (03 << CSA_V_UAE)
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#define CSA_IE 0000100 /* interrupt enable */
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#define CSA_DONE 0000200 /* done */
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#define CSA_INIT 0000400 /* init */
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#define CSA_ECLR 0001000 /* clear errors */
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#define CSA_DELH 0002000 /* delimiter hold */
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#define CSA_ONL 0004000 /* online */
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#define CSA_DVON 0010000 /* DAVFU online */
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#define CSA_UNDF 0020000 /* undefined char */
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#define CSA_PZRO 0040000 /* page counter zero */
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#define CSA_ERR 0100000 /* error */
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#define CSA_RW (CSA_DELH | CSA_IE | CSA_UAE | CSA_FNC | CSA_PAR | CSA_GO)
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#define CSA_MBZ (CSA_ECLR | CSA_INIT)
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#define CSA_GETUAE(x) (((x) & CSA_UAE) << (16 - CSA_V_UAE))
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#define CSA_GETFNC(x) (((x) >> CSA_V_FNC) & CSA_M_FNC)
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#define CSA_GO 0000001 /* go */
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#define CSA_PAR 0000002 /* parity enable NI */
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#define CSA_V_FNC 2 /* function */
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#define CSA_M_FNC 03
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#define FNC_PR 0 /* print */
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#define FNC_TST 1 /* test */
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#define FNC_DVU 2 /* load DAVFU */
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#define FNC_RAM 3 /* load translation RAM */
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#define FNC_INTERNAL 1 /* internal function */
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#define CSA_FNC (CSA_M_FNC << CSA_V_FNC)
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#define CSA_V_UAE 4 /* Unibus addr extension */
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#define CSA_UAE (03 << CSA_V_UAE)
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#define CSA_IE 0000100 /* interrupt enable */
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#define CSA_DONE 0000200 /* done */
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#define CSA_INIT 0000400 /* init */
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#define CSA_ECLR 0001000 /* clear errors */
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#define CSA_DELH 0002000 /* delimiter hold */
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#define CSA_ONL 0004000 /* online */
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#define CSA_DVON 0010000 /* DAVFU online */
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#define CSA_UNDF 0020000 /* undefined char */
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#define CSA_PZRO 0040000 /* page counter zero */
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#define CSA_ERR 0100000 /* error */
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#define CSA_RW (CSA_DELH | CSA_IE | CSA_UAE | CSA_FNC | CSA_PAR | CSA_GO)
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#define CSA_MBZ (CSA_ECLR | CSA_INIT)
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#define CSA_GETUAE(x) (((x) & CSA_UAE) << (16 - CSA_V_UAE))
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#define CSA_GETFNC(x) (((x) >> CSA_V_FNC) & CSA_M_FNC)
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/* LPCSRB (765402) */
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#define CSB_GOE 0000001 /* go error */
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#define CSB_DTE 0000002 /* DEM timing error NI */
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#define CSB_MTE 0000004 /* MSYN error (Ubus timeout) */
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#define CSB_RPE 0000010 /* RAM parity error NI */
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#define CSB_MPE 0000020 /* MEM parity error NI */
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#define CSB_LPE 0000040 /* LPT parity error NI */
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#define CSB_DVOF 0000100 /* DAVFU not ready */
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#define CSB_OFFL 0000200 /* offline */
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#define CSB_TEST 0003400 /* test mode */
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#define CSB_OVFU 0004000 /* optical VFU NI */
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#define CSB_PBIT 0010000 /* data parity bit NI */
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#define CSB_NRDY 0020000 /* printer error NI */
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#define CSB_LA180 0040000 /* LA180 printer NI */
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#define CSB_VLD 0100000 /* valid data NI */
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#define CSB_ECLR (CSB_GOE | CSB_DTE | CSB_MTE | CSB_RPE | CSB_MPE | CSB_LPE)
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#define CSB_ERR (CSB_ECLR | CSB_DVOF | CSB_OFFL)
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#define CSB_RW CSB_TEST
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#define CSB_MBZ (CSB_DTE | CSB_RPE | CSB_MPE | CSB_LPE | CSB_OVFU |\
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CSB_PBIT | CSB_NRDY | CSB_LA180 | CSB_VLD)
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#define CSB_GOE 0000001 /* go error */
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#define CSB_DTE 0000002 /* DEM timing error NI */
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#define CSB_MTE 0000004 /* MSYN error (Ubus timeout) */
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#define CSB_RPE 0000010 /* RAM parity error NI */
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#define CSB_MPE 0000020 /* MEM parity error NI */
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#define CSB_LPE 0000040 /* LPT parity error NI */
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#define CSB_DVOF 0000100 /* DAVFU not ready */
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#define CSB_OFFL 0000200 /* offline */
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#define CSB_TEST 0003400 /* test mode */
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#define CSB_OVFU 0004000 /* optical VFU NI */
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#define CSB_PBIT 0010000 /* data parity bit NI */
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#define CSB_NRDY 0020000 /* printer error NI */
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#define CSB_LA180 0040000 /* LA180 printer NI */
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#define CSB_VLD 0100000 /* valid data NI */
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#define CSB_ECLR (CSB_GOE | CSB_DTE | CSB_MTE | CSB_RPE | CSB_MPE | CSB_LPE)
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#define CSB_ERR (CSB_ECLR | CSB_DVOF | CSB_OFFL)
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#define CSB_RW CSB_TEST
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#define CSB_MBZ (CSB_DTE | CSB_RPE | CSB_MPE | CSB_LPE | CSB_OVFU |\
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CSB_PBIT | CSB_NRDY | CSB_LA180 | CSB_VLD)
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/* LPBA (765404) */
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/* LPBC (765506) */
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#define BC_MASK 0007777 /* <15:12> MBZ */
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#define BC_MASK 0007777 /* <15:12> MBZ */
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/* LPPAGC (765510) */
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#define PAGC_MASK 0007777 /* <15:12> MBZ */
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#define PAGC_MASK 0007777 /* <15:12> MBZ */
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/* LPRDAT (765512) */
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#define RDAT_MASK 0007777 /* <15:12> MBZ */
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#define RDAT_MASK 0007777 /* <15:12> MBZ */
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/* LPCOLC/LPCBUF (765514) */
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/* LPCSUM/LPPDAT (765516) */
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extern d10 *M; /* main memory */
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extern int32 int_req;
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extern int32 int_vec[32];
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extern int32 ubcs[UBANUM]; /* UBA csr */
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extern int32 ubmap[UBANUM][UMAP_MEMSIZE]; /* UBA map */
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int32 lpcsa = 0; /* control/status A */
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int32 lpcsb = 0; /* control/status B */
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int32 lpba = 0; /* bus address */
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int32 lpbc = 0; /* byte count */
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int32 lppagc = 0; /* page count */
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int32 lprdat = 0; /* RAM data */
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int32 lpcbuf = 0; /* character buffer */
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int32 lpcolc = 0; /* column count */
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int32 lppdat = 0; /* printer data */
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int32 lpcsum = 0; /* checksum */
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int32 dvptr = 0; /* davfu pointer */
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int32 dvlnt = 0; /* davfu length */
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int32 lp20_irq = 0; /* int request */
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int32 lp20_stopioe = 0; /* stop on error */
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int16 txram[TX_SIZE] = { 0 }; /* translation RAM */
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int16 davfu[DV_SIZE] = { 0 }; /* DAVFU */
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extern d10 *M; /* main memory */
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extern int32 int_req;
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int32 lpcsa = 0; /* control/status A */
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int32 lpcsb = 0; /* control/status B */
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int32 lpba = 0; /* bus address */
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int32 lpbc = 0; /* byte count */
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int32 lppagc = 0; /* page count */
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int32 lprdat = 0; /* RAM data */
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int32 lpcbuf = 0; /* character buffer */
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int32 lpcolc = 0; /* column count */
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int32 lppdat = 0; /* printer data */
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int32 lpcsum = 0; /* checksum */
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int32 dvptr = 0; /* davfu pointer */
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int32 dvlnt = 0; /* davfu length */
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int32 lp20_irq = 0; /* int request */
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int32 lp20_stopioe = 0; /* stop on error */
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int16 txram[TX_SIZE] = { 0 }; /* translation RAM */
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int16 davfu[DV_SIZE] = { 0 }; /* DAVFU */
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DEVICE lp20_dev;
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t_stat lp20_rd (int32 *data, int32 pa, int32 access);
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@@ -175,285 +174,332 @@ void update_lpcs (int32 flg);
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/* LP data structures
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lp20_dev LPT device descriptor
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lp20_unit LPT unit descriptor
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lp20_reg LPT register list
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lp20_dev LPT device descriptor
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lp20_unit LPT unit descriptor
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lp20_reg LPT register list
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*/
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DIB lp20_dib = { IOBA_LP20, IOLN_LP20, &lp20_rd, &lp20_wr,
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1, IVCL (LP20), VEC_LP20, { &lp20_inta } };
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DIB lp20_dib = {
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IOBA_LP20, IOLN_LP20, &lp20_rd, &lp20_wr,
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1, IVCL (LP20), VEC_LP20, { &lp20_inta }
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};
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UNIT lp20_unit = {
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UDATA (&lp20_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
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UDATA (&lp20_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT
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};
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REG lp20_reg[] = {
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{ ORDATA (LPCSA, lpcsa, 16) },
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{ ORDATA (LPCSB, lpcsb, 16) },
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{ ORDATA (LPBA, lpba, 16) },
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{ ORDATA (LPBC, lpbc, 12) },
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{ ORDATA (LPPAGC, lppagc, 12) },
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{ ORDATA (LPRDAT, lprdat, 12) },
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{ ORDATA (LPCBUF, lpcbuf, 8) },
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{ ORDATA (LPCOLC, lpcolc, 8) },
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{ ORDATA (LPPDAT, lppdat, 8) },
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{ ORDATA (LPCSUM, lpcsum, 8) },
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{ ORDATA (DVPTR, dvptr, 7) },
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{ ORDATA (DVLNT, dvlnt, 7), REG_RO + REG_NZ },
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{ FLDATA (INT, int_req, INT_V_LP20) },
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{ FLDATA (IRQ, lp20_irq, 0) },
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{ FLDATA (ERR, lpcsa, CSR_V_ERR) },
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{ FLDATA (DONE, lpcsa, CSR_V_DONE) },
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{ FLDATA (IE, lpcsa, CSR_V_IE) },
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{ DRDATA (POS, lp20_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, lp20_unit.wait, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, lp20_stopioe, 0) },
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{ BRDATA (TXRAM, txram, 8, 12, TX_SIZE) },
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{ BRDATA (DAVFU, davfu, 8, 12, DV_SIZE) },
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{ ORDATA (DEVADDR, lp20_dib.ba, 32), REG_HRO },
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{ ORDATA (DEVVEC, lp20_dib.vec, 16), REG_HRO },
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{ NULL } };
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{ ORDATA (LPCSA, lpcsa, 16) },
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{ ORDATA (LPCSB, lpcsb, 16) },
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{ ORDATA (LPBA, lpba, 16) },
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{ ORDATA (LPBC, lpbc, 12) },
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{ ORDATA (LPPAGC, lppagc, 12) },
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{ ORDATA (LPRDAT, lprdat, 12) },
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{ ORDATA (LPCBUF, lpcbuf, 8) },
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{ ORDATA (LPCOLC, lpcolc, 8) },
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{ ORDATA (LPPDAT, lppdat, 8) },
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{ ORDATA (LPCSUM, lpcsum, 8) },
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{ ORDATA (DVPTR, dvptr, 7) },
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{ ORDATA (DVLNT, dvlnt, 7), REG_RO + REG_NZ },
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{ FLDATA (INT, int_req, INT_V_LP20) },
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{ FLDATA (IRQ, lp20_irq, 0) },
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{ FLDATA (ERR, lpcsa, CSR_V_ERR) },
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{ FLDATA (DONE, lpcsa, CSR_V_DONE) },
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{ FLDATA (IE, lpcsa, CSR_V_IE) },
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{ DRDATA (POS, lp20_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, lp20_unit.wait, 24), PV_LEFT },
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{ FLDATA (STOP_IOE, lp20_stopioe, 0) },
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{ BRDATA (TXRAM, txram, 8, 12, TX_SIZE) },
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{ BRDATA (DAVFU, davfu, 8, 12, DV_SIZE) },
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{ ORDATA (DEVADDR, lp20_dib.ba, 32), REG_HRO },
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{ ORDATA (DEVVEC, lp20_dib.vec, 16), REG_HRO },
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||||
{ NULL }
|
||||
};
|
||||
|
||||
MTAB lp20_mod[] = {
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||||
{ UNIT_DUMMY, 0, NULL, "VFUCLEAR", &lp20_clear_vfu },
|
||||
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
|
||||
&set_addr, &show_addr, NULL },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
|
||||
&set_vec, &show_vec, NULL },
|
||||
{ 0 } };
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||||
{ UNIT_DUMMY, 0, NULL, "VFUCLEAR", &lp20_clear_vfu },
|
||||
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
|
||||
&set_addr, &show_addr, NULL },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
|
||||
&set_vec, &show_vec, NULL },
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||||
{ 0 }
|
||||
};
|
||||
|
||||
DEVICE lp20_dev = {
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||||
"LP20", &lp20_unit, lp20_reg, lp20_mod,
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||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &lp20_reset,
|
||||
NULL, &lp20_attach, &lp20_detach,
|
||||
&lp20_dib, DEV_DISABLE | DEV_UBUS };
|
||||
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||||
"LP20", &lp20_unit, lp20_reg, lp20_mod,
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||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &lp20_reset,
|
||||
NULL, &lp20_attach, &lp20_detach,
|
||||
&lp20_dib, DEV_DISABLE | DEV_UBUS
|
||||
};
|
||||
|
||||
/* Line printer routines
|
||||
|
||||
lp20_rd I/O page read
|
||||
lp20_wr I/O page write
|
||||
lp20_svc process event (printer ready)
|
||||
lp20_reset process reset
|
||||
lp20_attach process attach
|
||||
lp20_detach process detach
|
||||
lp20_rd I/O page read
|
||||
lp20_wr I/O page write
|
||||
lp20_svc process event (printer ready)
|
||||
lp20_reset process reset
|
||||
lp20_attach process attach
|
||||
lp20_detach process detach
|
||||
*/
|
||||
|
||||
t_stat lp20_rd (int32 *data, int32 pa, int32 access)
|
||||
{
|
||||
update_lpcs (0); /* update csr's */
|
||||
switch ((pa >> 1) & 07) { /* case on PA<3:1> */
|
||||
case 00: /* LPCSA */
|
||||
*data = lpcsa = lpcsa & ~CSA_MBZ;
|
||||
break;
|
||||
case 01: /* LPCSB */
|
||||
*data = lpcsb = lpcsb & ~CSB_MBZ;
|
||||
break;
|
||||
case 02: /* LPBA */
|
||||
*data = lpba;
|
||||
break;
|
||||
case 03: /* LPBC */
|
||||
*data = lpbc = lpbc & BC_MASK;
|
||||
break;
|
||||
case 04: /* LPPAGC */
|
||||
*data = lppagc = lppagc & PAGC_MASK;
|
||||
break;
|
||||
case 05: /* LPRDAT */
|
||||
*data = lprdat = lprdat & RDAT_MASK;
|
||||
break;
|
||||
case 06: /* LPCOLC/LPCBUF */
|
||||
*data = (lpcolc << 8) | lpcbuf;
|
||||
break;
|
||||
case 07: /* LPCSUM/LPPDAT */
|
||||
*data = (lpcsum << 8) | lppdat;
|
||||
break; } /* end case PA */
|
||||
update_lpcs (0); /* update csr's */
|
||||
switch ((pa >> 1) & 07) { /* case on PA<3:1> */
|
||||
|
||||
case 00: /* LPCSA */
|
||||
*data = lpcsa = lpcsa & ~CSA_MBZ;
|
||||
break;
|
||||
|
||||
case 01: /* LPCSB */
|
||||
*data = lpcsb = lpcsb & ~CSB_MBZ;
|
||||
break;
|
||||
|
||||
case 02: /* LPBA */
|
||||
*data = lpba;
|
||||
break;
|
||||
|
||||
case 03: /* LPBC */
|
||||
*data = lpbc = lpbc & BC_MASK;
|
||||
break;
|
||||
|
||||
case 04: /* LPPAGC */
|
||||
*data = lppagc = lppagc & PAGC_MASK;
|
||||
break;
|
||||
|
||||
case 05: /* LPRDAT */
|
||||
*data = lprdat = lprdat & RDAT_MASK;
|
||||
break;
|
||||
|
||||
case 06: /* LPCOLC/LPCBUF */
|
||||
*data = (lpcolc << 8) | lpcbuf;
|
||||
break;
|
||||
|
||||
case 07: /* LPCSUM/LPPDAT */
|
||||
*data = (lpcsum << 8) | lppdat;
|
||||
break;
|
||||
} /* end case PA */
|
||||
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
t_stat lp20_wr (int32 data, int32 pa, int32 access)
|
||||
{
|
||||
update_lpcs (0); /* update csr's */
|
||||
switch ((pa >> 1) & 07) { /* case on PA<3:1> */
|
||||
case 00: /* LPCSA */
|
||||
if (access == WRITEB) data = (pa & 1)?
|
||||
(lpcsa & 0377) | (data << 8): (lpcsa & ~0377) | data;
|
||||
if (data & CSA_ECLR) { /* error clear? */
|
||||
lpcsa = (lpcsa | CSA_DONE) & ~CSA_GO; /* set done, clr go */
|
||||
lpcsb = lpcsb & ~CSB_ECLR; /* clear err */
|
||||
sim_cancel (&lp20_unit); } /* cancel I/O */
|
||||
if (data & CSA_INIT) lp20_reset (&lp20_dev); /* init? */
|
||||
if (data & CSA_GO) { /* go set? */
|
||||
if ((lpcsa & CSA_GO) == 0) { /* not set before? */
|
||||
if (lpcsb & CSB_ERR) lpcsb = lpcsb | CSB_GOE;
|
||||
lpcsum = 0; /* clear checksum */
|
||||
sim_activate (&lp20_unit, lp20_unit.wait); } }
|
||||
else sim_cancel (&lp20_unit); /* go clr, stop DMA */
|
||||
lpcsa = (lpcsa & ~CSA_RW) | (data & CSA_RW);
|
||||
break;
|
||||
case 01: /* LPCSB */
|
||||
break; /* ignore writes to TEST */
|
||||
case 02: /* LPBA */
|
||||
if (access == WRITEB) data = (pa & 1)?
|
||||
(lpba & 0377) | (data << 8): (lpba & ~0377) | data;
|
||||
lpba = data;
|
||||
break;
|
||||
case 03: /* LPBC */
|
||||
if (access == WRITEB) data = (pa & 1)?
|
||||
(lpbc & 0377) | (data << 8): (lpbc & ~0377) | data;
|
||||
lpbc = data & BC_MASK;
|
||||
lpcsa = lpcsa & ~CSA_DONE;
|
||||
break;
|
||||
case 04: /* LPPAGC */
|
||||
if (access == WRITEB) data = (pa & 1)?
|
||||
(lppagc & 0377) | (data << 8): (lppagc & ~0377) | data;
|
||||
lppagc = data & PAGC_MASK;
|
||||
break;
|
||||
case 05: /* LPRDAT */
|
||||
if (access == WRITEB) data = (pa & 1)?
|
||||
(lprdat & 0377) | (data << 8): (lprdat & ~0377) | data;
|
||||
lprdat = data & RDAT_MASK;
|
||||
txram[lpcbuf & TX_AMASK] = lprdat; /* load RAM */
|
||||
break;
|
||||
case 06: /* LPCOLC/LPCBUF */
|
||||
if ((access == WRITEB) && (pa & 1)) /* odd byte */
|
||||
lpcolc = data & 0377;
|
||||
else {
|
||||
lpcbuf = data & 0377; /* even byte, word */
|
||||
if (access == WRITE) lpcolc = (data >> 8) & 0377; }
|
||||
break;
|
||||
case 07: /* LPCSUM/LPPDAT */
|
||||
break; } /* read only */
|
||||
update_lpcs (0); /* update csr's */
|
||||
switch ((pa >> 1) & 07) { /* case on PA<3:1> */
|
||||
|
||||
case 00: /* LPCSA */
|
||||
if (access == WRITEB) data = (pa & 1)?
|
||||
(lpcsa & 0377) | (data << 8): (lpcsa & ~0377) | data;
|
||||
if (data & CSA_ECLR) { /* error clear? */
|
||||
lpcsa = (lpcsa | CSA_DONE) & ~CSA_GO; /* set done, clr go */
|
||||
lpcsb = lpcsb & ~CSB_ECLR; /* clear err */
|
||||
sim_cancel (&lp20_unit); /* cancel I/O */
|
||||
}
|
||||
if (data & CSA_INIT) lp20_reset (&lp20_dev); /* init? */
|
||||
if (data & CSA_GO) { /* go set? */
|
||||
if ((lpcsa & CSA_GO) == 0) { /* not set before? */
|
||||
if (lpcsb & CSB_ERR) lpcsb = lpcsb | CSB_GOE;
|
||||
lpcsum = 0; /* clear checksum */
|
||||
sim_activate (&lp20_unit, lp20_unit.wait);
|
||||
}
|
||||
}
|
||||
else sim_cancel (&lp20_unit); /* go clr, stop DMA */
|
||||
lpcsa = (lpcsa & ~CSA_RW) | (data & CSA_RW);
|
||||
break;
|
||||
|
||||
case 01: /* LPCSB */
|
||||
break; /* ignore writes to TEST */
|
||||
|
||||
case 02: /* LPBA */
|
||||
if (access == WRITEB) data = (pa & 1)?
|
||||
(lpba & 0377) | (data << 8): (lpba & ~0377) | data;
|
||||
lpba = data;
|
||||
break;
|
||||
|
||||
case 03: /* LPBC */
|
||||
if (access == WRITEB) data = (pa & 1)?
|
||||
(lpbc & 0377) | (data << 8): (lpbc & ~0377) | data;
|
||||
lpbc = data & BC_MASK;
|
||||
lpcsa = lpcsa & ~CSA_DONE;
|
||||
break;
|
||||
|
||||
case 04: /* LPPAGC */
|
||||
if (access == WRITEB) data = (pa & 1)?
|
||||
(lppagc & 0377) | (data << 8): (lppagc & ~0377) | data;
|
||||
lppagc = data & PAGC_MASK;
|
||||
break;
|
||||
|
||||
case 05: /* LPRDAT */
|
||||
if (access == WRITEB) data = (pa & 1)?
|
||||
(lprdat & 0377) | (data << 8): (lprdat & ~0377) | data;
|
||||
lprdat = data & RDAT_MASK;
|
||||
txram[lpcbuf & TX_AMASK] = lprdat; /* load RAM */
|
||||
break;
|
||||
|
||||
case 06: /* LPCOLC/LPCBUF */
|
||||
if ((access == WRITEB) && (pa & 1)) /* odd byte */
|
||||
lpcolc = data & 0377;
|
||||
else {
|
||||
lpcbuf = data & 0377; /* even byte, word */
|
||||
if (access == WRITE) lpcolc = (data >> 8) & 0377;
|
||||
}
|
||||
break;
|
||||
|
||||
case 07: /* LPCSUM/LPPDAT */
|
||||
break; /* read only */
|
||||
} /* end case PA */
|
||||
|
||||
update_lpcs (0);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
/* Line printer service
|
||||
|
||||
The translation RAM case table is derived from the LP20 spec and
|
||||
verified against the LP20 RAM simulator in TOPS10 7.04 LPTSPL.
|
||||
The equations are:
|
||||
|
||||
flags := inter, delim, xlate, paper, delim_hold (from CSRA)
|
||||
actions : = print_input, print_xlate, davfu_action, interrupt
|
||||
flags := inter, delim, xlate, paper, delim_hold (from CSRA)
|
||||
actions : = print_input, print_xlate, davfu_action, interrupt
|
||||
|
||||
if (inter) {
|
||||
if (!xlate || delim || delim_hold) interrupt;
|
||||
else if (paper) davfu_action;
|
||||
else print_xlate; }
|
||||
else if (paper) {
|
||||
if (xlate || delim || delim_hold) davfu_action;
|
||||
else print_input; }
|
||||
else {
|
||||
if (xlate || delim || delim_hold) print_xlate;
|
||||
else print_input; }
|
||||
if (inter) {
|
||||
if (!xlate || delim || delim_hold) interrupt;
|
||||
else if (paper) davfu_action;
|
||||
else print_xlate;
|
||||
}
|
||||
else if (paper) {
|
||||
if (xlate || delim || delim_hold) davfu_action;
|
||||
else print_input;
|
||||
}
|
||||
else {
|
||||
if (xlate || delim || delim_hold) print_xlate;
|
||||
else print_input;
|
||||
}
|
||||
*/
|
||||
|
||||
t_stat lp20_svc (UNIT *uptr)
|
||||
{
|
||||
int32 fnc, i, tbc, temp, txst;
|
||||
int32 dvld = -2; /* must be even */
|
||||
int32 err = 0;
|
||||
int32 dvld = -2; /* must be even */
|
||||
uint16 wd10;
|
||||
t_bool cont;
|
||||
a10 ba;
|
||||
|
||||
static const uint32 txcase[32] = {
|
||||
TX_CHR, TX_RAM, TX_CHR, TX_DVU, TX_RAM, TX_RAM, TX_DVU, TX_DVU,
|
||||
TX_RAM, TX_RAM, TX_DVU, TX_DVU, TX_RAM, TX_RAM, TX_DVU, TX_DVU,
|
||||
TX_INT, TX_INT, TX_INT, TX_INT, TX_RAM, TX_INT, TX_DVU, TX_INT,
|
||||
TX_INT, TX_INT, TX_INT, TX_INT, TX_INT, TX_INT, TX_INT, TX_INT };
|
||||
TX_CHR, TX_RAM, TX_CHR, TX_DVU, TX_RAM, TX_RAM, TX_DVU, TX_DVU,
|
||||
TX_RAM, TX_RAM, TX_DVU, TX_DVU, TX_RAM, TX_RAM, TX_DVU, TX_DVU,
|
||||
TX_INT, TX_INT, TX_INT, TX_INT, TX_RAM, TX_INT, TX_DVU, TX_INT,
|
||||
TX_INT, TX_INT, TX_INT, TX_INT, TX_INT, TX_INT, TX_INT, TX_INT
|
||||
};
|
||||
|
||||
lpcsa = lpcsa & ~CSA_GO;
|
||||
ba = CSA_GETUAE (lpcsa) | lpba;
|
||||
fnc = CSA_GETFNC (lpcsa);
|
||||
tbc = 010000 - lpbc;
|
||||
if (((fnc & FNC_INTERNAL) == 0) && ((lp20_unit.flags & UNIT_ATT) == 0)) {
|
||||
update_lpcs (CSA_ERR);
|
||||
IORETURN (lp20_stopioe, SCPE_UNATT); }
|
||||
update_lpcs (CSA_ERR);
|
||||
return IORETURN (lp20_stopioe, SCPE_UNATT);
|
||||
}
|
||||
if ((fnc == FNC_PR) && (dvlnt == 0)) {
|
||||
update_lpcs (CSA_ERR);
|
||||
return SCPE_OK; }
|
||||
update_lpcs (CSA_ERR);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
for (i = 0, cont = TRUE; (i < tbc) && cont; ba++, i++) {
|
||||
if (Map_ReadW (ba, 2, &wd10)) { /* get word, err? */
|
||||
lpcsb = lpcsb | CSB_MTE; /* set NXM error */
|
||||
update_lpcs (CSA_ERR); /* set done */
|
||||
break; }
|
||||
lpcbuf = (wd10 >> ((ba & 1)? 8: 0)) & 0377; /* get character */
|
||||
lpcsum = (lpcsum + lpcbuf) & 0377; /* add into checksum */
|
||||
switch (fnc) { /* switch on function */
|
||||
if (Map_ReadW (ba, 2, &wd10)) { /* get word, err? */
|
||||
lpcsb = lpcsb | CSB_MTE; /* set NXM error */
|
||||
update_lpcs (CSA_ERR); /* set done */
|
||||
break;
|
||||
}
|
||||
lpcbuf = (wd10 >> ((ba & 1)? 8: 0)) & 0377; /* get character */
|
||||
lpcsum = (lpcsum + lpcbuf) & 0377; /* add into checksum */
|
||||
switch (fnc) { /* switch on function */
|
||||
|
||||
/* Translation RAM load */
|
||||
|
||||
case FNC_RAM: /* RAM load */
|
||||
txram[(i >> 1) & TX_AMASK] = wd10 & TX_DMASK;
|
||||
break;
|
||||
case FNC_RAM: /* RAM load */
|
||||
txram[(i >> 1) & TX_AMASK] = wd10 & TX_DMASK;
|
||||
break;
|
||||
|
||||
/* DAVFU RAM load. The DAVFU RAM is actually loaded in bytes, delimited by
|
||||
a start (354 to 356) and stop (357) byte pair. If the number of bytes
|
||||
loaded is odd, or no bytes are loaded, the DAVFU is invalid.
|
||||
*/
|
||||
|
||||
case FNC_DVU: /* DVU load */
|
||||
if ((lpcbuf >= 0354) && (lpcbuf <= 0356)) /* start DVU load? */
|
||||
dvld = dvlnt = 0; /* reset lnt */
|
||||
else if (lpcbuf == 0357) { /* stop DVU load? */
|
||||
dvptr = 0; /* reset ptr */
|
||||
if (dvld & 1) dvlnt = 0; } /* if odd, invalid */
|
||||
else if (dvld == 0) { /* even state? */
|
||||
temp = lpcbuf & DV_DMASK;
|
||||
dvld = 1; }
|
||||
else if (dvld == 1) { /* odd state? */
|
||||
if (dvlnt < DV_SIZE) davfu[dvlnt++] =
|
||||
temp | ((lpcbuf & DV_DMASK) << 6);
|
||||
dvld = 0; }
|
||||
break;
|
||||
case FNC_DVU: /* DVU load */
|
||||
if ((lpcbuf >= 0354) && (lpcbuf <= 0356)) /* start DVU load? */
|
||||
dvld = dvlnt = 0; /* reset lnt */
|
||||
else if (lpcbuf == 0357) { /* stop DVU load? */
|
||||
dvptr = 0; /* reset ptr */
|
||||
if (dvld & 1) dvlnt = 0; /* if odd, invalid */
|
||||
}
|
||||
else if (dvld == 0) { /* even state? */
|
||||
temp = lpcbuf & DV_DMASK;
|
||||
dvld = 1;
|
||||
}
|
||||
else if (dvld == 1) { /* odd state? */
|
||||
if (dvlnt < DV_SIZE) davfu[dvlnt++] =
|
||||
temp | ((lpcbuf & DV_DMASK) << 6);
|
||||
dvld = 0;
|
||||
}
|
||||
break;
|
||||
|
||||
/* Print characters */
|
||||
|
||||
case FNC_PR: /* print */
|
||||
lprdat = txram[lpcbuf]; /* get RAM char */
|
||||
txst = (TX_GETFL (lprdat) << 1) | /* get state */
|
||||
((lpcsa & CSA_DELH)? 1: 0); /* plus delim hold */
|
||||
if (lprdat & TX_DELH) lpcsa = lpcsa | CSA_DELH;
|
||||
else lpcsa = lpcsa & ~CSA_DELH;
|
||||
lpcsa = lpcsa & ~CSA_UNDF; /* assume char ok */
|
||||
switch (txcase[txst]) { /* case on state */
|
||||
case TX_CHR: /* take char */
|
||||
cont = lp20_print (lpcbuf);
|
||||
break;
|
||||
case TX_RAM: /* take translation */
|
||||
cont = lp20_print (lprdat);
|
||||
break;
|
||||
case TX_DVU: /* DAVFU action */
|
||||
if (lprdat & TX_SLEW)
|
||||
cont = lp20_adv (lprdat & TX_VMASK, TRUE);
|
||||
else cont = lp20_davfu (lprdat & TX_VMASK);
|
||||
break;
|
||||
case TX_INT: /* interrupt */
|
||||
lpcsa = lpcsa | CSA_UNDF; /* set flag */
|
||||
cont = FALSE; /* force stop */
|
||||
break; } /* end case char state */
|
||||
break;
|
||||
case FNC_TST: /* test */
|
||||
break; } /* end case function */
|
||||
} /* end for */
|
||||
case FNC_PR: /* print */
|
||||
lprdat = txram[lpcbuf]; /* get RAM char */
|
||||
txst = (TX_GETFL (lprdat) << 1) | /* get state */
|
||||
((lpcsa & CSA_DELH)? 1: 0); /* plus delim hold */
|
||||
if (lprdat & TX_DELH) lpcsa = lpcsa | CSA_DELH;
|
||||
else lpcsa = lpcsa & ~CSA_DELH;
|
||||
lpcsa = lpcsa & ~CSA_UNDF; /* assume char ok */
|
||||
switch (txcase[txst]) { /* case on state */
|
||||
|
||||
case TX_CHR: /* take char */
|
||||
cont = lp20_print (lpcbuf);
|
||||
break;
|
||||
|
||||
case TX_RAM: /* take translation */
|
||||
cont = lp20_print (lprdat);
|
||||
break;
|
||||
|
||||
case TX_DVU: /* DAVFU action */
|
||||
if (lprdat & TX_SLEW)
|
||||
cont = lp20_adv (lprdat & TX_VMASK, TRUE);
|
||||
else cont = lp20_davfu (lprdat & TX_VMASK);
|
||||
break;
|
||||
|
||||
case TX_INT: /* interrupt */
|
||||
lpcsa = lpcsa | CSA_UNDF; /* set flag */
|
||||
cont = FALSE; /* force stop */
|
||||
break;
|
||||
} /* end case char state */
|
||||
break;
|
||||
|
||||
case FNC_TST: /* test */
|
||||
break;
|
||||
} /* end case function */
|
||||
} /* end for */
|
||||
lpba = ba & 0177777;
|
||||
lpcsa = (lpcsa & ~CSA_UAE) | ((ba >> (16 - CSA_V_UAE)) & CSA_UAE);
|
||||
lpbc = (lpbc + i) & BC_MASK;
|
||||
if (lpbc) update_lpcs (CSA_MBZ); /* intr, but not done */
|
||||
else update_lpcs (CSA_DONE); /* intr and done */
|
||||
if (lpbc) update_lpcs (CSA_MBZ); /* intr, but not done */
|
||||
else update_lpcs (CSA_DONE); /* intr and done */
|
||||
if ((fnc == FNC_PR) && ferror (lp20_unit.fileref)) {
|
||||
perror ("LP I/O error");
|
||||
clearerr (uptr->fileref);
|
||||
return SCPE_IOERR; }
|
||||
perror ("LP I/O error");
|
||||
clearerr (uptr->fileref);
|
||||
return SCPE_IOERR;
|
||||
}
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
/* Print routines
|
||||
|
||||
lp20_print print a character
|
||||
lp20_adv advance n lines
|
||||
lp20_davfu advance to channel on VFU
|
||||
lp20_print print a character
|
||||
lp20_adv advance n lines
|
||||
lp20_davfu advance to channel on VFU
|
||||
|
||||
Return TRUE to continue printing, FALSE to stop
|
||||
*/
|
||||
@@ -463,20 +509,24 @@ t_bool lp20_print (int32 c)
|
||||
t_bool r = TRUE;
|
||||
int32 i, rpt = 1;
|
||||
|
||||
lppdat = c & 0177; /* mask char to 7b */
|
||||
if (lppdat == 000) return TRUE; /* NUL? no op */
|
||||
if (lppdat == 012) return lp20_adv (1, TRUE); /* LF? adv carriage */
|
||||
if (lppdat == 014) return lp20_davfu (DV_TOF); /* FF? top of form */
|
||||
if (lppdat == 015) lpcolc = 0; /* CR? reset col cntr */
|
||||
else if (lppdat == 011) { /* TAB? simulate */
|
||||
lppdat = ' '; /* with spaces */
|
||||
if (lpcolc >= 128) {
|
||||
r = lp20_adv (1, TRUE); /* eol? adv carriage */
|
||||
rpt = 8; } /* adv to col 9 */
|
||||
else rpt = 8 - (lpcolc & 07); } /* else adv 1 to 8 */
|
||||
else { if (lppdat < 040) lppdat = ' '; /* cvt non-prnt to spc */
|
||||
if (lpcolc >= LP_WIDTH) /* line full? */
|
||||
r = lp20_adv (1, TRUE); } /* adv carriage */
|
||||
lppdat = c & 0177; /* mask char to 7b */
|
||||
if (lppdat == 000) return TRUE; /* NUL? no op */
|
||||
if (lppdat == 012) return lp20_adv (1, TRUE); /* LF? adv carriage */
|
||||
if (lppdat == 014) return lp20_davfu (DV_TOF); /* FF? top of form */
|
||||
if (lppdat == 015) lpcolc = 0; /* CR? reset col cntr */
|
||||
else if (lppdat == 011) { /* TAB? simulate */
|
||||
lppdat = ' '; /* with spaces */
|
||||
if (lpcolc >= 128) {
|
||||
r = lp20_adv (1, TRUE); /* eol? adv carriage */
|
||||
rpt = 8; /* adv to col 9 */
|
||||
}
|
||||
else rpt = 8 - (lpcolc & 07); /* else adv 1 to 8 */
|
||||
}
|
||||
else {
|
||||
if (lppdat < 040) lppdat = ' '; /* cvt non-prnt to spc */
|
||||
if (lpcolc >= LP_WIDTH) /* line full? */
|
||||
r = lp20_adv (1, TRUE); /* adv carriage */
|
||||
}
|
||||
for (i = 0; i < rpt; i++) putc (lppdat, lp20_unit.fileref);
|
||||
lp20_unit.pos = lp20_unit.pos + rpt;
|
||||
lpcolc = lpcolc + rpt;
|
||||
@@ -488,17 +538,20 @@ t_bool lp20_adv (int32 cnt, t_bool dvuadv)
|
||||
int32 i;
|
||||
|
||||
if (cnt == 0) return TRUE;
|
||||
lpcolc = 0; /* reset col cntr */
|
||||
lpcolc = 0; /* reset col cntr */
|
||||
for (i = 0; i < cnt; i++) putc ('\n', lp20_unit.fileref);
|
||||
lp20_unit.pos = lp20_unit.pos + cnt; /* print 'n' newlines */
|
||||
if (dvuadv) dvptr = (dvptr + cnt) % dvlnt; /* update DAVFU ptr */
|
||||
if (davfu[dvptr] & (1 << DV_TOF)) { /* at top of form? */
|
||||
if (lppagc = (lppagc - 1) & PAGC_MASK) { /* decr page cntr */
|
||||
lpcsa = lpcsa & ~CSA_PZRO; /* update status */
|
||||
return TRUE; }
|
||||
else {
|
||||
lpcsa = lpcsa | CSA_PZRO; /* stop if zero */
|
||||
return FALSE; } }
|
||||
lp20_unit.pos = lp20_unit.pos + cnt; /* print 'n' newlines */
|
||||
if (dvuadv) dvptr = (dvptr + cnt) % dvlnt; /* update DAVFU ptr */
|
||||
if (davfu[dvptr] & (1 << DV_TOF)) { /* at top of form? */
|
||||
if (lppagc = (lppagc - 1) & PAGC_MASK) { /* decr page cntr */
|
||||
lpcsa = lpcsa & ~CSA_PZRO; /* update status */
|
||||
return TRUE;
|
||||
}
|
||||
else {
|
||||
lpcsa = lpcsa | CSA_PZRO; /* stop if zero */
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
@@ -506,40 +559,45 @@ t_bool lp20_davfu (int32 cnt)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (cnt > DV_MAX) cnt = 7; /* inval chan? */
|
||||
for (i = 0; i < dvlnt; i++) { /* search DAVFU */
|
||||
dvptr = dvptr + 1; /* adv DAVFU ptr */
|
||||
if (dvptr >= dvlnt) dvptr = 0; /* wrap at end */
|
||||
if (davfu[dvptr] & (1 << cnt)) { /* channel stop set? */
|
||||
if (cnt) return lp20_adv (i + 1, FALSE); /* ~TOF, adv */
|
||||
if (lpcolc) lp20_adv (1, FALSE); /* TOF, need newline? */
|
||||
putc ('\f', lp20_unit.fileref); /* print form feed */
|
||||
lp20_unit.pos = lp20_unit.pos + 1;
|
||||
if (lppagc = (lppagc - 1) & PAGC_MASK) { /* decr page cntr */
|
||||
lpcsa = lpcsa & ~CSA_PZRO; /* update status */
|
||||
return TRUE; }
|
||||
else {
|
||||
lpcsa = lpcsa | CSA_PZRO; /* stop if zero */
|
||||
return FALSE; } }
|
||||
} /* end for */
|
||||
dvlnt = 0; /* DAVFU error */
|
||||
if (cnt > DV_MAX) cnt = 7; /* inval chan? */
|
||||
for (i = 0; i < dvlnt; i++) { /* search DAVFU */
|
||||
dvptr = dvptr + 1; /* adv DAVFU ptr */
|
||||
if (dvptr >= dvlnt) dvptr = 0; /* wrap at end */
|
||||
if (davfu[dvptr] & (1 << cnt)) { /* channel stop set? */
|
||||
if (cnt) return lp20_adv (i + 1, FALSE); /* ~TOF, adv */
|
||||
if (lpcolc) lp20_adv (1, FALSE); /* TOF, need newline? */
|
||||
putc ('\f', lp20_unit.fileref); /* print form feed */
|
||||
lp20_unit.pos = lp20_unit.pos + 1;
|
||||
if (lppagc = (lppagc - 1) & PAGC_MASK) { /* decr page cntr */
|
||||
lpcsa = lpcsa & ~CSA_PZRO; /* update status */
|
||||
return TRUE;
|
||||
}
|
||||
else {
|
||||
lpcsa = lpcsa | CSA_PZRO; /* stop if zero */
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
} /* end for */
|
||||
dvlnt = 0; /* DAVFU error */
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
||||
/* Update LPCSA, optionally request interrupt */
|
||||
|
||||
void update_lpcs (int32 flg)
|
||||
{
|
||||
if (flg) lp20_irq = 1; /* set int req */
|
||||
if (flg) lp20_irq = 1; /* set int req */
|
||||
lpcsa = (lpcsa | flg) & ~(CSA_MBZ | CSA_ERR | CSA_ONL | CSA_DVON);
|
||||
lpcsb = (lpcsb | CSB_OFFL | CSB_DVOF) & ~CSB_MBZ;
|
||||
if (lp20_unit.flags & UNIT_ATT) {
|
||||
lpcsa = lpcsa | CSA_ONL;
|
||||
lpcsb = lpcsb & ~CSB_OFFL; }
|
||||
lpcsa = lpcsa | CSA_ONL;
|
||||
lpcsb = lpcsb & ~CSB_OFFL;
|
||||
}
|
||||
else lpcsa = lpcsa & ~CSA_DONE;
|
||||
if (dvlnt) {
|
||||
lpcsa = lpcsa | CSA_DVON;
|
||||
lpcsb = lpcsb & ~CSB_DVOF; }
|
||||
lpcsa = lpcsa | CSA_DVON;
|
||||
lpcsb = lpcsb & ~CSB_DVOF;
|
||||
}
|
||||
if (lpcsb & CSB_ERR) lpcsa = lpcsa | CSA_ERR;
|
||||
if ((lpcsa & CSA_IE) && lp20_irq) int_req = int_req | INT_LP20;
|
||||
else int_req = int_req & ~INT_LP20;
|
||||
@@ -550,31 +608,31 @@ return;
|
||||
|
||||
int32 lp20_inta (void)
|
||||
{
|
||||
lp20_irq = 0; /* clear int req */
|
||||
lp20_irq = 0; /* clear int req */
|
||||
return lp20_dib.vec;
|
||||
}
|
||||
|
||||
|
||||
t_stat lp20_reset (DEVICE *dptr)
|
||||
{
|
||||
lpcsa = CSA_DONE;
|
||||
lpcsb = 0;
|
||||
lpba = lpbc = lppagc = lpcolc = 0; /* clear registers */
|
||||
lpba = lpbc = lppagc = lpcolc = 0; /* clear registers */
|
||||
lprdat = lppdat = lpcbuf = lpcsum = 0;
|
||||
lp20_irq = 0; /* clear int req */
|
||||
dvptr = 0; /* reset davfu ptr */
|
||||
sim_cancel (&lp20_unit); /* deactivate unit */
|
||||
update_lpcs (0); /* update status */
|
||||
lp20_irq = 0; /* clear int req */
|
||||
dvptr = 0; /* reset davfu ptr */
|
||||
sim_cancel (&lp20_unit); /* deactivate unit */
|
||||
update_lpcs (0); /* update status */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
t_stat lp20_attach (UNIT *uptr, char *cptr)
|
||||
{
|
||||
t_stat reason;
|
||||
|
||||
reason = attach_unit (uptr, cptr); /* attach file */
|
||||
if (lpcsa & CSA_ONL) return reason; /* just file chg? */
|
||||
if (sim_is_active (&lp20_unit)) update_lpcs (0); /* busy? no int */
|
||||
else update_lpcs (CSA_MBZ); /* interrupt */
|
||||
|
||||
reason = attach_unit (uptr, cptr); /* attach file */
|
||||
if (lpcsa & CSA_ONL) return reason; /* just file chg? */
|
||||
if (sim_is_active (&lp20_unit)) update_lpcs (0); /* busy? no int */
|
||||
else update_lpcs (CSA_MBZ); /* interrupt */
|
||||
return reason;
|
||||
}
|
||||
|
||||
@@ -582,7 +640,7 @@ t_stat lp20_detach (UNIT *uptr)
|
||||
{
|
||||
t_stat reason;
|
||||
|
||||
if (!(uptr->flags & UNIT_ATT)) return SCPE_OK; /* attached? */
|
||||
if (!(uptr->flags & UNIT_ATT)) return SCPE_OK; /* attached? */
|
||||
reason = detach_unit (uptr);
|
||||
sim_cancel (&lp20_unit);
|
||||
lpcsa = lpcsa & ~CSA_GO;
|
||||
|
||||
Reference in New Issue
Block a user